ucb1x00-core.c 16 KB

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  1. /*
  2. * linux/drivers/mfd/ucb1x00-core.c
  3. *
  4. * Copyright (C) 2001 Russell King, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License.
  9. *
  10. * The UCB1x00 core driver provides basic services for handling IO,
  11. * the ADC, interrupts, and accessing registers. It is designed
  12. * such that everything goes through this layer, thereby providing
  13. * a consistent locking methodology, as well as allowing the drivers
  14. * to be used on other non-MCP-enabled hardware platforms.
  15. *
  16. * Note that all locks are private to this file. Nothing else may
  17. * touch them.
  18. */
  19. #include <linux/config.h>
  20. #include <linux/module.h>
  21. #include <linux/kernel.h>
  22. #include <linux/slab.h>
  23. #include <linux/init.h>
  24. #include <linux/errno.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/device.h>
  27. #include <linux/mutex.h>
  28. #include <asm/dma.h>
  29. #include <asm/hardware.h>
  30. #include "ucb1x00.h"
  31. static DEFINE_MUTEX(ucb1x00_mutex);
  32. static LIST_HEAD(ucb1x00_drivers);
  33. static LIST_HEAD(ucb1x00_devices);
  34. /**
  35. * ucb1x00_io_set_dir - set IO direction
  36. * @ucb: UCB1x00 structure describing chip
  37. * @in: bitfield of IO pins to be set as inputs
  38. * @out: bitfield of IO pins to be set as outputs
  39. *
  40. * Set the IO direction of the ten general purpose IO pins on
  41. * the UCB1x00 chip. The @in bitfield has priority over the
  42. * @out bitfield, in that if you specify a pin as both input
  43. * and output, it will end up as an input.
  44. *
  45. * ucb1x00_enable must have been called to enable the comms
  46. * before using this function.
  47. *
  48. * This function takes a spinlock, disabling interrupts.
  49. */
  50. void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int in, unsigned int out)
  51. {
  52. unsigned long flags;
  53. spin_lock_irqsave(&ucb->io_lock, flags);
  54. ucb->io_dir |= out;
  55. ucb->io_dir &= ~in;
  56. ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
  57. spin_unlock_irqrestore(&ucb->io_lock, flags);
  58. }
  59. /**
  60. * ucb1x00_io_write - set or clear IO outputs
  61. * @ucb: UCB1x00 structure describing chip
  62. * @set: bitfield of IO pins to set to logic '1'
  63. * @clear: bitfield of IO pins to set to logic '0'
  64. *
  65. * Set the IO output state of the specified IO pins. The value
  66. * is retained if the pins are subsequently configured as inputs.
  67. * The @clear bitfield has priority over the @set bitfield -
  68. * outputs will be cleared.
  69. *
  70. * ucb1x00_enable must have been called to enable the comms
  71. * before using this function.
  72. *
  73. * This function takes a spinlock, disabling interrupts.
  74. */
  75. void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int set, unsigned int clear)
  76. {
  77. unsigned long flags;
  78. spin_lock_irqsave(&ucb->io_lock, flags);
  79. ucb->io_out |= set;
  80. ucb->io_out &= ~clear;
  81. ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
  82. spin_unlock_irqrestore(&ucb->io_lock, flags);
  83. }
  84. /**
  85. * ucb1x00_io_read - read the current state of the IO pins
  86. * @ucb: UCB1x00 structure describing chip
  87. *
  88. * Return a bitfield describing the logic state of the ten
  89. * general purpose IO pins.
  90. *
  91. * ucb1x00_enable must have been called to enable the comms
  92. * before using this function.
  93. *
  94. * This function does not take any semaphores or spinlocks.
  95. */
  96. unsigned int ucb1x00_io_read(struct ucb1x00 *ucb)
  97. {
  98. return ucb1x00_reg_read(ucb, UCB_IO_DATA);
  99. }
  100. /*
  101. * UCB1300 data sheet says we must:
  102. * 1. enable ADC => 5us (including reference startup time)
  103. * 2. select input => 51*tsibclk => 4.3us
  104. * 3. start conversion => 102*tsibclk => 8.5us
  105. * (tsibclk = 1/11981000)
  106. * Period between SIB 128-bit frames = 10.7us
  107. */
  108. /**
  109. * ucb1x00_adc_enable - enable the ADC converter
  110. * @ucb: UCB1x00 structure describing chip
  111. *
  112. * Enable the ucb1x00 and ADC converter on the UCB1x00 for use.
  113. * Any code wishing to use the ADC converter must call this
  114. * function prior to using it.
  115. *
  116. * This function takes the ADC semaphore to prevent two or more
  117. * concurrent uses, and therefore may sleep. As a result, it
  118. * can only be called from process context, not interrupt
  119. * context.
  120. *
  121. * You should release the ADC as soon as possible using
  122. * ucb1x00_adc_disable.
  123. */
  124. void ucb1x00_adc_enable(struct ucb1x00 *ucb)
  125. {
  126. down(&ucb->adc_sem);
  127. ucb->adc_cr |= UCB_ADC_ENA;
  128. ucb1x00_enable(ucb);
  129. ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr);
  130. }
  131. /**
  132. * ucb1x00_adc_read - read the specified ADC channel
  133. * @ucb: UCB1x00 structure describing chip
  134. * @adc_channel: ADC channel mask
  135. * @sync: wait for syncronisation pulse.
  136. *
  137. * Start an ADC conversion and wait for the result. Note that
  138. * synchronised ADC conversions (via the ADCSYNC pin) must wait
  139. * until the trigger is asserted and the conversion is finished.
  140. *
  141. * This function currently spins waiting for the conversion to
  142. * complete (2 frames max without sync).
  143. *
  144. * If called for a synchronised ADC conversion, it may sleep
  145. * with the ADC semaphore held.
  146. */
  147. unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync)
  148. {
  149. unsigned int val;
  150. if (sync)
  151. adc_channel |= UCB_ADC_SYNC_ENA;
  152. ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel);
  153. ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel | UCB_ADC_START);
  154. for (;;) {
  155. val = ucb1x00_reg_read(ucb, UCB_ADC_DATA);
  156. if (val & UCB_ADC_DAT_VAL)
  157. break;
  158. /* yield to other processes */
  159. set_current_state(TASK_INTERRUPTIBLE);
  160. schedule_timeout(1);
  161. }
  162. return UCB_ADC_DAT(val);
  163. }
  164. /**
  165. * ucb1x00_adc_disable - disable the ADC converter
  166. * @ucb: UCB1x00 structure describing chip
  167. *
  168. * Disable the ADC converter and release the ADC semaphore.
  169. */
  170. void ucb1x00_adc_disable(struct ucb1x00 *ucb)
  171. {
  172. ucb->adc_cr &= ~UCB_ADC_ENA;
  173. ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr);
  174. ucb1x00_disable(ucb);
  175. up(&ucb->adc_sem);
  176. }
  177. /*
  178. * UCB1x00 Interrupt handling.
  179. *
  180. * The UCB1x00 can generate interrupts when the SIBCLK is stopped.
  181. * Since we need to read an internal register, we must re-enable
  182. * SIBCLK to talk to the chip. We leave the clock running until
  183. * we have finished processing all interrupts from the chip.
  184. */
  185. static irqreturn_t ucb1x00_irq(int irqnr, void *devid, struct pt_regs *regs)
  186. {
  187. struct ucb1x00 *ucb = devid;
  188. struct ucb1x00_irq *irq;
  189. unsigned int isr, i;
  190. ucb1x00_enable(ucb);
  191. isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS);
  192. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr);
  193. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
  194. for (i = 0, irq = ucb->irq_handler; i < 16 && isr; i++, isr >>= 1, irq++)
  195. if (isr & 1 && irq->fn)
  196. irq->fn(i, irq->devid);
  197. ucb1x00_disable(ucb);
  198. return IRQ_HANDLED;
  199. }
  200. /**
  201. * ucb1x00_hook_irq - hook a UCB1x00 interrupt
  202. * @ucb: UCB1x00 structure describing chip
  203. * @idx: interrupt index
  204. * @fn: function to call when interrupt is triggered
  205. * @devid: device id to pass to interrupt handler
  206. *
  207. * Hook the specified interrupt. You can only register one handler
  208. * for each interrupt source. The interrupt source is not enabled
  209. * by this function; use ucb1x00_enable_irq instead.
  210. *
  211. * Interrupt handlers will be called with other interrupts enabled.
  212. *
  213. * Returns zero on success, or one of the following errors:
  214. * -EINVAL if the interrupt index is invalid
  215. * -EBUSY if the interrupt has already been hooked
  216. */
  217. int ucb1x00_hook_irq(struct ucb1x00 *ucb, unsigned int idx, void (*fn)(int, void *), void *devid)
  218. {
  219. struct ucb1x00_irq *irq;
  220. int ret = -EINVAL;
  221. if (idx < 16) {
  222. irq = ucb->irq_handler + idx;
  223. ret = -EBUSY;
  224. spin_lock_irq(&ucb->lock);
  225. if (irq->fn == NULL) {
  226. irq->devid = devid;
  227. irq->fn = fn;
  228. ret = 0;
  229. }
  230. spin_unlock_irq(&ucb->lock);
  231. }
  232. return ret;
  233. }
  234. /**
  235. * ucb1x00_enable_irq - enable an UCB1x00 interrupt source
  236. * @ucb: UCB1x00 structure describing chip
  237. * @idx: interrupt index
  238. * @edges: interrupt edges to enable
  239. *
  240. * Enable the specified interrupt to trigger on %UCB_RISING,
  241. * %UCB_FALLING or both edges. The interrupt should have been
  242. * hooked by ucb1x00_hook_irq.
  243. */
  244. void ucb1x00_enable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges)
  245. {
  246. unsigned long flags;
  247. if (idx < 16) {
  248. spin_lock_irqsave(&ucb->lock, flags);
  249. ucb1x00_enable(ucb);
  250. if (edges & UCB_RISING) {
  251. ucb->irq_ris_enbl |= 1 << idx;
  252. ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
  253. }
  254. if (edges & UCB_FALLING) {
  255. ucb->irq_fal_enbl |= 1 << idx;
  256. ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
  257. }
  258. ucb1x00_disable(ucb);
  259. spin_unlock_irqrestore(&ucb->lock, flags);
  260. }
  261. }
  262. /**
  263. * ucb1x00_disable_irq - disable an UCB1x00 interrupt source
  264. * @ucb: UCB1x00 structure describing chip
  265. * @edges: interrupt edges to disable
  266. *
  267. * Disable the specified interrupt triggering on the specified
  268. * (%UCB_RISING, %UCB_FALLING or both) edges.
  269. */
  270. void ucb1x00_disable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges)
  271. {
  272. unsigned long flags;
  273. if (idx < 16) {
  274. spin_lock_irqsave(&ucb->lock, flags);
  275. ucb1x00_enable(ucb);
  276. if (edges & UCB_RISING) {
  277. ucb->irq_ris_enbl &= ~(1 << idx);
  278. ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
  279. }
  280. if (edges & UCB_FALLING) {
  281. ucb->irq_fal_enbl &= ~(1 << idx);
  282. ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
  283. }
  284. ucb1x00_disable(ucb);
  285. spin_unlock_irqrestore(&ucb->lock, flags);
  286. }
  287. }
  288. /**
  289. * ucb1x00_free_irq - disable and free the specified UCB1x00 interrupt
  290. * @ucb: UCB1x00 structure describing chip
  291. * @idx: interrupt index
  292. * @devid: device id.
  293. *
  294. * Disable the interrupt source and remove the handler. devid must
  295. * match the devid passed when hooking the interrupt.
  296. *
  297. * Returns zero on success, or one of the following errors:
  298. * -EINVAL if the interrupt index is invalid
  299. * -ENOENT if devid does not match
  300. */
  301. int ucb1x00_free_irq(struct ucb1x00 *ucb, unsigned int idx, void *devid)
  302. {
  303. struct ucb1x00_irq *irq;
  304. int ret;
  305. if (idx >= 16)
  306. goto bad;
  307. irq = ucb->irq_handler + idx;
  308. ret = -ENOENT;
  309. spin_lock_irq(&ucb->lock);
  310. if (irq->devid == devid) {
  311. ucb->irq_ris_enbl &= ~(1 << idx);
  312. ucb->irq_fal_enbl &= ~(1 << idx);
  313. ucb1x00_enable(ucb);
  314. ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
  315. ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
  316. ucb1x00_disable(ucb);
  317. irq->fn = NULL;
  318. irq->devid = NULL;
  319. ret = 0;
  320. }
  321. spin_unlock_irq(&ucb->lock);
  322. return ret;
  323. bad:
  324. printk(KERN_ERR "Freeing bad UCB1x00 irq %d\n", idx);
  325. return -EINVAL;
  326. }
  327. static int ucb1x00_add_dev(struct ucb1x00 *ucb, struct ucb1x00_driver *drv)
  328. {
  329. struct ucb1x00_dev *dev;
  330. int ret = -ENOMEM;
  331. dev = kmalloc(sizeof(struct ucb1x00_dev), GFP_KERNEL);
  332. if (dev) {
  333. dev->ucb = ucb;
  334. dev->drv = drv;
  335. ret = drv->add(dev);
  336. if (ret == 0) {
  337. list_add(&dev->dev_node, &ucb->devs);
  338. list_add(&dev->drv_node, &drv->devs);
  339. } else {
  340. kfree(dev);
  341. }
  342. }
  343. return ret;
  344. }
  345. static void ucb1x00_remove_dev(struct ucb1x00_dev *dev)
  346. {
  347. dev->drv->remove(dev);
  348. list_del(&dev->dev_node);
  349. list_del(&dev->drv_node);
  350. kfree(dev);
  351. }
  352. /*
  353. * Try to probe our interrupt, rather than relying on lots of
  354. * hard-coded machine dependencies. For reference, the expected
  355. * IRQ mappings are:
  356. *
  357. * Machine Default IRQ
  358. * adsbitsy IRQ_GPCIN4
  359. * cerf IRQ_GPIO_UCB1200_IRQ
  360. * flexanet IRQ_GPIO_GUI
  361. * freebird IRQ_GPIO_FREEBIRD_UCB1300_IRQ
  362. * graphicsclient ADS_EXT_IRQ(8)
  363. * graphicsmaster ADS_EXT_IRQ(8)
  364. * lart LART_IRQ_UCB1200
  365. * omnimeter IRQ_GPIO23
  366. * pfs168 IRQ_GPIO_UCB1300_IRQ
  367. * simpad IRQ_GPIO_UCB1300_IRQ
  368. * shannon SHANNON_IRQ_GPIO_IRQ_CODEC
  369. * yopy IRQ_GPIO_UCB1200_IRQ
  370. */
  371. static int ucb1x00_detect_irq(struct ucb1x00 *ucb)
  372. {
  373. unsigned long mask;
  374. mask = probe_irq_on();
  375. if (!mask)
  376. return NO_IRQ;
  377. /*
  378. * Enable the ADC interrupt.
  379. */
  380. ucb1x00_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC);
  381. ucb1x00_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC);
  382. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
  383. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
  384. /*
  385. * Cause an ADC interrupt.
  386. */
  387. ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA);
  388. ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START);
  389. /*
  390. * Wait for the conversion to complete.
  391. */
  392. while ((ucb1x00_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VAL) == 0);
  393. ucb1x00_reg_write(ucb, UCB_ADC_CR, 0);
  394. /*
  395. * Disable and clear interrupt.
  396. */
  397. ucb1x00_reg_write(ucb, UCB_IE_RIS, 0);
  398. ucb1x00_reg_write(ucb, UCB_IE_FAL, 0);
  399. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
  400. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
  401. /*
  402. * Read triggered interrupt.
  403. */
  404. return probe_irq_off(mask);
  405. }
  406. static void ucb1x00_release(struct class_device *dev)
  407. {
  408. struct ucb1x00 *ucb = classdev_to_ucb1x00(dev);
  409. kfree(ucb);
  410. }
  411. static struct class ucb1x00_class = {
  412. .name = "ucb1x00",
  413. .release = ucb1x00_release,
  414. };
  415. static int ucb1x00_probe(struct mcp *mcp)
  416. {
  417. struct ucb1x00 *ucb;
  418. struct ucb1x00_driver *drv;
  419. unsigned int id;
  420. int ret = -ENODEV;
  421. mcp_enable(mcp);
  422. id = mcp_reg_read(mcp, UCB_ID);
  423. if (id != UCB_ID_1200 && id != UCB_ID_1300) {
  424. printk(KERN_WARNING "UCB1x00 ID not found: %04x\n", id);
  425. goto err_disable;
  426. }
  427. ucb = kmalloc(sizeof(struct ucb1x00), GFP_KERNEL);
  428. ret = -ENOMEM;
  429. if (!ucb)
  430. goto err_disable;
  431. memset(ucb, 0, sizeof(struct ucb1x00));
  432. ucb->cdev.class = &ucb1x00_class;
  433. ucb->cdev.dev = &mcp->attached_device;
  434. strlcpy(ucb->cdev.class_id, "ucb1x00", sizeof(ucb->cdev.class_id));
  435. spin_lock_init(&ucb->lock);
  436. spin_lock_init(&ucb->io_lock);
  437. sema_init(&ucb->adc_sem, 1);
  438. ucb->id = id;
  439. ucb->mcp = mcp;
  440. ucb->irq = ucb1x00_detect_irq(ucb);
  441. if (ucb->irq == NO_IRQ) {
  442. printk(KERN_ERR "UCB1x00: IRQ probe failed\n");
  443. ret = -ENODEV;
  444. goto err_free;
  445. }
  446. ret = request_irq(ucb->irq, ucb1x00_irq, SA_TRIGGER_RISING,
  447. "UCB1x00", ucb);
  448. if (ret) {
  449. printk(KERN_ERR "ucb1x00: unable to grab irq%d: %d\n",
  450. ucb->irq, ret);
  451. goto err_free;
  452. }
  453. mcp_set_drvdata(mcp, ucb);
  454. ret = class_device_register(&ucb->cdev);
  455. if (ret)
  456. goto err_irq;
  457. INIT_LIST_HEAD(&ucb->devs);
  458. mutex_lock(&ucb1x00_mutex);
  459. list_add(&ucb->node, &ucb1x00_devices);
  460. list_for_each_entry(drv, &ucb1x00_drivers, node) {
  461. ucb1x00_add_dev(ucb, drv);
  462. }
  463. mutex_unlock(&ucb1x00_mutex);
  464. goto out;
  465. err_irq:
  466. free_irq(ucb->irq, ucb);
  467. err_free:
  468. kfree(ucb);
  469. err_disable:
  470. mcp_disable(mcp);
  471. out:
  472. return ret;
  473. }
  474. static void ucb1x00_remove(struct mcp *mcp)
  475. {
  476. struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
  477. struct list_head *l, *n;
  478. mutex_lock(&ucb1x00_mutex);
  479. list_del(&ucb->node);
  480. list_for_each_safe(l, n, &ucb->devs) {
  481. struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, dev_node);
  482. ucb1x00_remove_dev(dev);
  483. }
  484. mutex_unlock(&ucb1x00_mutex);
  485. free_irq(ucb->irq, ucb);
  486. class_device_unregister(&ucb->cdev);
  487. }
  488. int ucb1x00_register_driver(struct ucb1x00_driver *drv)
  489. {
  490. struct ucb1x00 *ucb;
  491. INIT_LIST_HEAD(&drv->devs);
  492. mutex_lock(&ucb1x00_mutex);
  493. list_add(&drv->node, &ucb1x00_drivers);
  494. list_for_each_entry(ucb, &ucb1x00_devices, node) {
  495. ucb1x00_add_dev(ucb, drv);
  496. }
  497. mutex_unlock(&ucb1x00_mutex);
  498. return 0;
  499. }
  500. void ucb1x00_unregister_driver(struct ucb1x00_driver *drv)
  501. {
  502. struct list_head *n, *l;
  503. mutex_lock(&ucb1x00_mutex);
  504. list_del(&drv->node);
  505. list_for_each_safe(l, n, &drv->devs) {
  506. struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, drv_node);
  507. ucb1x00_remove_dev(dev);
  508. }
  509. mutex_unlock(&ucb1x00_mutex);
  510. }
  511. static int ucb1x00_suspend(struct mcp *mcp, pm_message_t state)
  512. {
  513. struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
  514. struct ucb1x00_dev *dev;
  515. mutex_lock(&ucb1x00_mutex);
  516. list_for_each_entry(dev, &ucb->devs, dev_node) {
  517. if (dev->drv->suspend)
  518. dev->drv->suspend(dev, state);
  519. }
  520. mutex_unlock(&ucb1x00_mutex);
  521. return 0;
  522. }
  523. static int ucb1x00_resume(struct mcp *mcp)
  524. {
  525. struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
  526. struct ucb1x00_dev *dev;
  527. mutex_lock(&ucb1x00_mutex);
  528. list_for_each_entry(dev, &ucb->devs, dev_node) {
  529. if (dev->drv->resume)
  530. dev->drv->resume(dev);
  531. }
  532. mutex_unlock(&ucb1x00_mutex);
  533. return 0;
  534. }
  535. static struct mcp_driver ucb1x00_driver = {
  536. .drv = {
  537. .name = "ucb1x00",
  538. },
  539. .probe = ucb1x00_probe,
  540. .remove = ucb1x00_remove,
  541. .suspend = ucb1x00_suspend,
  542. .resume = ucb1x00_resume,
  543. };
  544. static int __init ucb1x00_init(void)
  545. {
  546. int ret = class_register(&ucb1x00_class);
  547. if (ret == 0) {
  548. ret = mcp_driver_register(&ucb1x00_driver);
  549. if (ret)
  550. class_unregister(&ucb1x00_class);
  551. }
  552. return ret;
  553. }
  554. static void __exit ucb1x00_exit(void)
  555. {
  556. mcp_driver_unregister(&ucb1x00_driver);
  557. class_unregister(&ucb1x00_class);
  558. }
  559. module_init(ucb1x00_init);
  560. module_exit(ucb1x00_exit);
  561. EXPORT_SYMBOL(ucb1x00_io_set_dir);
  562. EXPORT_SYMBOL(ucb1x00_io_write);
  563. EXPORT_SYMBOL(ucb1x00_io_read);
  564. EXPORT_SYMBOL(ucb1x00_adc_enable);
  565. EXPORT_SYMBOL(ucb1x00_adc_read);
  566. EXPORT_SYMBOL(ucb1x00_adc_disable);
  567. EXPORT_SYMBOL(ucb1x00_hook_irq);
  568. EXPORT_SYMBOL(ucb1x00_free_irq);
  569. EXPORT_SYMBOL(ucb1x00_enable_irq);
  570. EXPORT_SYMBOL(ucb1x00_disable_irq);
  571. EXPORT_SYMBOL(ucb1x00_register_driver);
  572. EXPORT_SYMBOL(ucb1x00_unregister_driver);
  573. MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
  574. MODULE_DESCRIPTION("UCB1x00 core driver");
  575. MODULE_LICENSE("GPL");