mthca_main.c 33 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. *
  34. * $Id: mthca_main.c 1396 2004-12-28 04:10:27Z roland $
  35. */
  36. #include <linux/config.h>
  37. #include <linux/module.h>
  38. #include <linux/init.h>
  39. #include <linux/errno.h>
  40. #include <linux/pci.h>
  41. #include <linux/interrupt.h>
  42. #include "mthca_dev.h"
  43. #include "mthca_config_reg.h"
  44. #include "mthca_cmd.h"
  45. #include "mthca_profile.h"
  46. #include "mthca_memfree.h"
  47. MODULE_AUTHOR("Roland Dreier");
  48. MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
  49. MODULE_LICENSE("Dual BSD/GPL");
  50. MODULE_VERSION(DRV_VERSION);
  51. #ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
  52. int mthca_debug_level = 0;
  53. module_param_named(debug_level, mthca_debug_level, int, 0644);
  54. MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  55. #endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
  56. #ifdef CONFIG_PCI_MSI
  57. static int msi_x = 0;
  58. module_param(msi_x, int, 0444);
  59. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  60. static int msi = 0;
  61. module_param(msi, int, 0444);
  62. MODULE_PARM_DESC(msi, "attempt to use MSI if nonzero");
  63. #else /* CONFIG_PCI_MSI */
  64. #define msi_x (0)
  65. #define msi (0)
  66. #endif /* CONFIG_PCI_MSI */
  67. static int tune_pci = 0;
  68. module_param(tune_pci, int, 0444);
  69. MODULE_PARM_DESC(tune_pci, "increase PCI burst from the default set by BIOS if nonzero");
  70. static const char mthca_version[] __devinitdata =
  71. DRV_NAME ": Mellanox InfiniBand HCA driver v"
  72. DRV_VERSION " (" DRV_RELDATE ")\n";
  73. static struct mthca_profile default_profile = {
  74. .num_qp = 1 << 16,
  75. .rdb_per_qp = 4,
  76. .num_cq = 1 << 16,
  77. .num_mcg = 1 << 13,
  78. .num_mpt = 1 << 17,
  79. .num_mtt = 1 << 20,
  80. .num_udav = 1 << 15, /* Tavor only */
  81. .fmr_reserved_mtts = 1 << 18, /* Tavor only */
  82. .uarc_size = 1 << 18, /* Arbel only */
  83. };
  84. static int __devinit mthca_tune_pci(struct mthca_dev *mdev)
  85. {
  86. int cap;
  87. u16 val;
  88. if (!tune_pci)
  89. return 0;
  90. /* First try to max out Read Byte Count */
  91. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX);
  92. if (cap) {
  93. if (pci_read_config_word(mdev->pdev, cap + PCI_X_CMD, &val)) {
  94. mthca_err(mdev, "Couldn't read PCI-X command register, "
  95. "aborting.\n");
  96. return -ENODEV;
  97. }
  98. val = (val & ~PCI_X_CMD_MAX_READ) | (3 << 2);
  99. if (pci_write_config_word(mdev->pdev, cap + PCI_X_CMD, val)) {
  100. mthca_err(mdev, "Couldn't write PCI-X command register, "
  101. "aborting.\n");
  102. return -ENODEV;
  103. }
  104. } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
  105. mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
  106. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP);
  107. if (cap) {
  108. if (pci_read_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, &val)) {
  109. mthca_err(mdev, "Couldn't read PCI Express device control "
  110. "register, aborting.\n");
  111. return -ENODEV;
  112. }
  113. val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
  114. if (pci_write_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, val)) {
  115. mthca_err(mdev, "Couldn't write PCI Express device control "
  116. "register, aborting.\n");
  117. return -ENODEV;
  118. }
  119. } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
  120. mthca_info(mdev, "No PCI Express capability, "
  121. "not setting Max Read Request Size.\n");
  122. return 0;
  123. }
  124. static int __devinit mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
  125. {
  126. int err;
  127. u8 status;
  128. err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status);
  129. if (err) {
  130. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  131. return err;
  132. }
  133. if (status) {
  134. mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, "
  135. "aborting.\n", status);
  136. return -EINVAL;
  137. }
  138. if (dev_lim->min_page_sz > PAGE_SIZE) {
  139. mthca_err(mdev, "HCA minimum page size of %d bigger than "
  140. "kernel PAGE_SIZE of %ld, aborting.\n",
  141. dev_lim->min_page_sz, PAGE_SIZE);
  142. return -ENODEV;
  143. }
  144. if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
  145. mthca_err(mdev, "HCA has %d ports, but we only support %d, "
  146. "aborting.\n",
  147. dev_lim->num_ports, MTHCA_MAX_PORTS);
  148. return -ENODEV;
  149. }
  150. if (dev_lim->uar_size > pci_resource_len(mdev->pdev, 2)) {
  151. mthca_err(mdev, "HCA reported UAR size of 0x%x bigger than "
  152. "PCI resource 2 size of 0x%lx, aborting.\n",
  153. dev_lim->uar_size, pci_resource_len(mdev->pdev, 2));
  154. return -ENODEV;
  155. }
  156. mdev->limits.num_ports = dev_lim->num_ports;
  157. mdev->limits.vl_cap = dev_lim->max_vl;
  158. mdev->limits.mtu_cap = dev_lim->max_mtu;
  159. mdev->limits.gid_table_len = dev_lim->max_gids;
  160. mdev->limits.pkey_table_len = dev_lim->max_pkeys;
  161. mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
  162. mdev->limits.max_sg = dev_lim->max_sg;
  163. mdev->limits.max_wqes = dev_lim->max_qp_sz;
  164. mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp;
  165. mdev->limits.reserved_qps = dev_lim->reserved_qps;
  166. mdev->limits.max_srq_wqes = dev_lim->max_srq_sz;
  167. mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
  168. mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
  169. mdev->limits.max_desc_sz = dev_lim->max_desc_sz;
  170. mdev->limits.max_srq_sge = mthca_max_srq_sge(mdev);
  171. /*
  172. * Subtract 1 from the limit because we need to allocate a
  173. * spare CQE so the HCA HW can tell the difference between an
  174. * empty CQ and a full CQ.
  175. */
  176. mdev->limits.max_cqes = dev_lim->max_cq_sz - 1;
  177. mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
  178. mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
  179. mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
  180. mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
  181. mdev->limits.reserved_uars = dev_lim->reserved_uars;
  182. mdev->limits.reserved_pds = dev_lim->reserved_pds;
  183. mdev->limits.port_width_cap = dev_lim->max_port_width;
  184. mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1);
  185. mdev->limits.flags = dev_lim->flags;
  186. /*
  187. * For old FW that doesn't return static rate support, use a
  188. * value of 0x3 (only static rate values of 0 or 1 are handled),
  189. * except on Sinai, where even old FW can handle static rate
  190. * values of 2 and 3.
  191. */
  192. if (dev_lim->stat_rate_support)
  193. mdev->limits.stat_rate_support = dev_lim->stat_rate_support;
  194. else if (mdev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
  195. mdev->limits.stat_rate_support = 0xf;
  196. else
  197. mdev->limits.stat_rate_support = 0x3;
  198. /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
  199. May be doable since hardware supports it for SRQ.
  200. IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
  201. IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
  202. supported by driver. */
  203. mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  204. IB_DEVICE_PORT_ACTIVE_EVENT |
  205. IB_DEVICE_SYS_IMAGE_GUID |
  206. IB_DEVICE_RC_RNR_NAK_GEN;
  207. if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
  208. mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  209. if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
  210. mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  211. if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
  212. mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
  213. if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
  214. mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  215. if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
  216. mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  217. if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
  218. mdev->mthca_flags |= MTHCA_FLAG_SRQ;
  219. return 0;
  220. }
  221. static int __devinit mthca_init_tavor(struct mthca_dev *mdev)
  222. {
  223. u8 status;
  224. int err;
  225. struct mthca_dev_lim dev_lim;
  226. struct mthca_profile profile;
  227. struct mthca_init_hca_param init_hca;
  228. err = mthca_SYS_EN(mdev, &status);
  229. if (err) {
  230. mthca_err(mdev, "SYS_EN command failed, aborting.\n");
  231. return err;
  232. }
  233. if (status) {
  234. mthca_err(mdev, "SYS_EN returned status 0x%02x, "
  235. "aborting.\n", status);
  236. return -EINVAL;
  237. }
  238. err = mthca_QUERY_FW(mdev, &status);
  239. if (err) {
  240. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  241. goto err_disable;
  242. }
  243. if (status) {
  244. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  245. "aborting.\n", status);
  246. err = -EINVAL;
  247. goto err_disable;
  248. }
  249. err = mthca_QUERY_DDR(mdev, &status);
  250. if (err) {
  251. mthca_err(mdev, "QUERY_DDR command failed, aborting.\n");
  252. goto err_disable;
  253. }
  254. if (status) {
  255. mthca_err(mdev, "QUERY_DDR returned status 0x%02x, "
  256. "aborting.\n", status);
  257. err = -EINVAL;
  258. goto err_disable;
  259. }
  260. err = mthca_dev_lim(mdev, &dev_lim);
  261. if (err) {
  262. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  263. goto err_disable;
  264. }
  265. profile = default_profile;
  266. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  267. profile.uarc_size = 0;
  268. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  269. profile.num_srq = dev_lim.max_srqs;
  270. err = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  271. if (err < 0)
  272. goto err_disable;
  273. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  274. if (err) {
  275. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  276. goto err_disable;
  277. }
  278. if (status) {
  279. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  280. "aborting.\n", status);
  281. err = -EINVAL;
  282. goto err_disable;
  283. }
  284. return 0;
  285. err_disable:
  286. mthca_SYS_DIS(mdev, &status);
  287. return err;
  288. }
  289. static int __devinit mthca_load_fw(struct mthca_dev *mdev)
  290. {
  291. u8 status;
  292. int err;
  293. /* FIXME: use HCA-attached memory for FW if present */
  294. mdev->fw.arbel.fw_icm =
  295. mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
  296. GFP_HIGHUSER | __GFP_NOWARN);
  297. if (!mdev->fw.arbel.fw_icm) {
  298. mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
  299. return -ENOMEM;
  300. }
  301. err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status);
  302. if (err) {
  303. mthca_err(mdev, "MAP_FA command failed, aborting.\n");
  304. goto err_free;
  305. }
  306. if (status) {
  307. mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status);
  308. err = -EINVAL;
  309. goto err_free;
  310. }
  311. err = mthca_RUN_FW(mdev, &status);
  312. if (err) {
  313. mthca_err(mdev, "RUN_FW command failed, aborting.\n");
  314. goto err_unmap_fa;
  315. }
  316. if (status) {
  317. mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status);
  318. err = -EINVAL;
  319. goto err_unmap_fa;
  320. }
  321. return 0;
  322. err_unmap_fa:
  323. mthca_UNMAP_FA(mdev, &status);
  324. err_free:
  325. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  326. return err;
  327. }
  328. static int __devinit mthca_init_icm(struct mthca_dev *mdev,
  329. struct mthca_dev_lim *dev_lim,
  330. struct mthca_init_hca_param *init_hca,
  331. u64 icm_size)
  332. {
  333. u64 aux_pages;
  334. u8 status;
  335. int err;
  336. err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status);
  337. if (err) {
  338. mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n");
  339. return err;
  340. }
  341. if (status) {
  342. mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, "
  343. "aborting.\n", status);
  344. return -EINVAL;
  345. }
  346. mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  347. (unsigned long long) icm_size >> 10,
  348. (unsigned long long) aux_pages << 2);
  349. mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
  350. GFP_HIGHUSER | __GFP_NOWARN);
  351. if (!mdev->fw.arbel.aux_icm) {
  352. mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
  353. return -ENOMEM;
  354. }
  355. err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status);
  356. if (err) {
  357. mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n");
  358. goto err_free_aux;
  359. }
  360. if (status) {
  361. mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status);
  362. err = -EINVAL;
  363. goto err_free_aux;
  364. }
  365. err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
  366. if (err) {
  367. mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
  368. goto err_unmap_aux;
  369. }
  370. mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
  371. MTHCA_MTT_SEG_SIZE,
  372. mdev->limits.num_mtt_segs,
  373. mdev->limits.reserved_mtts, 1);
  374. if (!mdev->mr_table.mtt_table) {
  375. mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
  376. err = -ENOMEM;
  377. goto err_unmap_eq;
  378. }
  379. mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
  380. dev_lim->mpt_entry_sz,
  381. mdev->limits.num_mpts,
  382. mdev->limits.reserved_mrws, 1);
  383. if (!mdev->mr_table.mpt_table) {
  384. mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
  385. err = -ENOMEM;
  386. goto err_unmap_mtt;
  387. }
  388. mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
  389. dev_lim->qpc_entry_sz,
  390. mdev->limits.num_qps,
  391. mdev->limits.reserved_qps, 0);
  392. if (!mdev->qp_table.qp_table) {
  393. mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
  394. err = -ENOMEM;
  395. goto err_unmap_mpt;
  396. }
  397. mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
  398. dev_lim->eqpc_entry_sz,
  399. mdev->limits.num_qps,
  400. mdev->limits.reserved_qps, 0);
  401. if (!mdev->qp_table.eqp_table) {
  402. mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
  403. err = -ENOMEM;
  404. goto err_unmap_qp;
  405. }
  406. mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
  407. MTHCA_RDB_ENTRY_SIZE,
  408. mdev->limits.num_qps <<
  409. mdev->qp_table.rdb_shift,
  410. 0, 0);
  411. if (!mdev->qp_table.rdb_table) {
  412. mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
  413. err = -ENOMEM;
  414. goto err_unmap_eqp;
  415. }
  416. mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
  417. dev_lim->cqc_entry_sz,
  418. mdev->limits.num_cqs,
  419. mdev->limits.reserved_cqs, 0);
  420. if (!mdev->cq_table.table) {
  421. mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
  422. err = -ENOMEM;
  423. goto err_unmap_rdb;
  424. }
  425. if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
  426. mdev->srq_table.table =
  427. mthca_alloc_icm_table(mdev, init_hca->srqc_base,
  428. dev_lim->srq_entry_sz,
  429. mdev->limits.num_srqs,
  430. mdev->limits.reserved_srqs, 0);
  431. if (!mdev->srq_table.table) {
  432. mthca_err(mdev, "Failed to map SRQ context memory, "
  433. "aborting.\n");
  434. err = -ENOMEM;
  435. goto err_unmap_cq;
  436. }
  437. }
  438. /*
  439. * It's not strictly required, but for simplicity just map the
  440. * whole multicast group table now. The table isn't very big
  441. * and it's a lot easier than trying to track ref counts.
  442. */
  443. mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
  444. MTHCA_MGM_ENTRY_SIZE,
  445. mdev->limits.num_mgms +
  446. mdev->limits.num_amgms,
  447. mdev->limits.num_mgms +
  448. mdev->limits.num_amgms,
  449. 0);
  450. if (!mdev->mcg_table.table) {
  451. mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
  452. err = -ENOMEM;
  453. goto err_unmap_srq;
  454. }
  455. return 0;
  456. err_unmap_srq:
  457. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  458. mthca_free_icm_table(mdev, mdev->srq_table.table);
  459. err_unmap_cq:
  460. mthca_free_icm_table(mdev, mdev->cq_table.table);
  461. err_unmap_rdb:
  462. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  463. err_unmap_eqp:
  464. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  465. err_unmap_qp:
  466. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  467. err_unmap_mpt:
  468. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  469. err_unmap_mtt:
  470. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  471. err_unmap_eq:
  472. mthca_unmap_eq_icm(mdev);
  473. err_unmap_aux:
  474. mthca_UNMAP_ICM_AUX(mdev, &status);
  475. err_free_aux:
  476. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  477. return err;
  478. }
  479. static void mthca_free_icms(struct mthca_dev *mdev)
  480. {
  481. u8 status;
  482. mthca_free_icm_table(mdev, mdev->mcg_table.table);
  483. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  484. mthca_free_icm_table(mdev, mdev->srq_table.table);
  485. mthca_free_icm_table(mdev, mdev->cq_table.table);
  486. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  487. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  488. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  489. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  490. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  491. mthca_unmap_eq_icm(mdev);
  492. mthca_UNMAP_ICM_AUX(mdev, &status);
  493. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  494. }
  495. static int __devinit mthca_init_arbel(struct mthca_dev *mdev)
  496. {
  497. struct mthca_dev_lim dev_lim;
  498. struct mthca_profile profile;
  499. struct mthca_init_hca_param init_hca;
  500. u64 icm_size;
  501. u8 status;
  502. int err;
  503. err = mthca_QUERY_FW(mdev, &status);
  504. if (err) {
  505. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  506. return err;
  507. }
  508. if (status) {
  509. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  510. "aborting.\n", status);
  511. return -EINVAL;
  512. }
  513. err = mthca_ENABLE_LAM(mdev, &status);
  514. if (err) {
  515. mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n");
  516. return err;
  517. }
  518. if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) {
  519. mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
  520. mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
  521. } else if (status) {
  522. mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, "
  523. "aborting.\n", status);
  524. return -EINVAL;
  525. }
  526. err = mthca_load_fw(mdev);
  527. if (err) {
  528. mthca_err(mdev, "Failed to start FW, aborting.\n");
  529. goto err_disable;
  530. }
  531. err = mthca_dev_lim(mdev, &dev_lim);
  532. if (err) {
  533. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  534. goto err_stop_fw;
  535. }
  536. profile = default_profile;
  537. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  538. profile.num_udav = 0;
  539. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  540. profile.num_srq = dev_lim.max_srqs;
  541. icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  542. if ((int) icm_size < 0) {
  543. err = icm_size;
  544. goto err_stop_fw;
  545. }
  546. err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
  547. if (err)
  548. goto err_stop_fw;
  549. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  550. if (err) {
  551. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  552. goto err_free_icm;
  553. }
  554. if (status) {
  555. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  556. "aborting.\n", status);
  557. err = -EINVAL;
  558. goto err_free_icm;
  559. }
  560. return 0;
  561. err_free_icm:
  562. mthca_free_icms(mdev);
  563. err_stop_fw:
  564. mthca_UNMAP_FA(mdev, &status);
  565. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  566. err_disable:
  567. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  568. mthca_DISABLE_LAM(mdev, &status);
  569. return err;
  570. }
  571. static void mthca_close_hca(struct mthca_dev *mdev)
  572. {
  573. u8 status;
  574. mthca_CLOSE_HCA(mdev, 0, &status);
  575. if (mthca_is_memfree(mdev)) {
  576. mthca_free_icms(mdev);
  577. mthca_UNMAP_FA(mdev, &status);
  578. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  579. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  580. mthca_DISABLE_LAM(mdev, &status);
  581. } else
  582. mthca_SYS_DIS(mdev, &status);
  583. }
  584. static int __devinit mthca_init_hca(struct mthca_dev *mdev)
  585. {
  586. u8 status;
  587. int err;
  588. struct mthca_adapter adapter;
  589. if (mthca_is_memfree(mdev))
  590. err = mthca_init_arbel(mdev);
  591. else
  592. err = mthca_init_tavor(mdev);
  593. if (err)
  594. return err;
  595. err = mthca_QUERY_ADAPTER(mdev, &adapter, &status);
  596. if (err) {
  597. mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n");
  598. goto err_close;
  599. }
  600. if (status) {
  601. mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, "
  602. "aborting.\n", status);
  603. err = -EINVAL;
  604. goto err_close;
  605. }
  606. mdev->eq_table.inta_pin = adapter.inta_pin;
  607. mdev->rev_id = adapter.revision_id;
  608. memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
  609. return 0;
  610. err_close:
  611. mthca_close_hca(mdev);
  612. return err;
  613. }
  614. static int __devinit mthca_setup_hca(struct mthca_dev *dev)
  615. {
  616. int err;
  617. u8 status;
  618. MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
  619. err = mthca_init_uar_table(dev);
  620. if (err) {
  621. mthca_err(dev, "Failed to initialize "
  622. "user access region table, aborting.\n");
  623. return err;
  624. }
  625. err = mthca_uar_alloc(dev, &dev->driver_uar);
  626. if (err) {
  627. mthca_err(dev, "Failed to allocate driver access region, "
  628. "aborting.\n");
  629. goto err_uar_table_free;
  630. }
  631. dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  632. if (!dev->kar) {
  633. mthca_err(dev, "Couldn't map kernel access region, "
  634. "aborting.\n");
  635. err = -ENOMEM;
  636. goto err_uar_free;
  637. }
  638. err = mthca_init_pd_table(dev);
  639. if (err) {
  640. mthca_err(dev, "Failed to initialize "
  641. "protection domain table, aborting.\n");
  642. goto err_kar_unmap;
  643. }
  644. err = mthca_init_mr_table(dev);
  645. if (err) {
  646. mthca_err(dev, "Failed to initialize "
  647. "memory region table, aborting.\n");
  648. goto err_pd_table_free;
  649. }
  650. err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
  651. if (err) {
  652. mthca_err(dev, "Failed to create driver PD, "
  653. "aborting.\n");
  654. goto err_mr_table_free;
  655. }
  656. err = mthca_init_eq_table(dev);
  657. if (err) {
  658. mthca_err(dev, "Failed to initialize "
  659. "event queue table, aborting.\n");
  660. goto err_pd_free;
  661. }
  662. err = mthca_cmd_use_events(dev);
  663. if (err) {
  664. mthca_err(dev, "Failed to switch to event-driven "
  665. "firmware commands, aborting.\n");
  666. goto err_eq_table_free;
  667. }
  668. err = mthca_NOP(dev, &status);
  669. if (err || status) {
  670. mthca_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting.\n",
  671. dev->mthca_flags & MTHCA_FLAG_MSI_X ?
  672. dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector :
  673. dev->pdev->irq);
  674. if (dev->mthca_flags & (MTHCA_FLAG_MSI | MTHCA_FLAG_MSI_X))
  675. mthca_err(dev, "Try again with MSI/MSI-X disabled.\n");
  676. else
  677. mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  678. goto err_cmd_poll;
  679. }
  680. mthca_dbg(dev, "NOP command IRQ test passed\n");
  681. err = mthca_init_cq_table(dev);
  682. if (err) {
  683. mthca_err(dev, "Failed to initialize "
  684. "completion queue table, aborting.\n");
  685. goto err_cmd_poll;
  686. }
  687. err = mthca_init_srq_table(dev);
  688. if (err) {
  689. mthca_err(dev, "Failed to initialize "
  690. "shared receive queue table, aborting.\n");
  691. goto err_cq_table_free;
  692. }
  693. err = mthca_init_qp_table(dev);
  694. if (err) {
  695. mthca_err(dev, "Failed to initialize "
  696. "queue pair table, aborting.\n");
  697. goto err_srq_table_free;
  698. }
  699. err = mthca_init_av_table(dev);
  700. if (err) {
  701. mthca_err(dev, "Failed to initialize "
  702. "address vector table, aborting.\n");
  703. goto err_qp_table_free;
  704. }
  705. err = mthca_init_mcg_table(dev);
  706. if (err) {
  707. mthca_err(dev, "Failed to initialize "
  708. "multicast group table, aborting.\n");
  709. goto err_av_table_free;
  710. }
  711. return 0;
  712. err_av_table_free:
  713. mthca_cleanup_av_table(dev);
  714. err_qp_table_free:
  715. mthca_cleanup_qp_table(dev);
  716. err_srq_table_free:
  717. mthca_cleanup_srq_table(dev);
  718. err_cq_table_free:
  719. mthca_cleanup_cq_table(dev);
  720. err_cmd_poll:
  721. mthca_cmd_use_polling(dev);
  722. err_eq_table_free:
  723. mthca_cleanup_eq_table(dev);
  724. err_pd_free:
  725. mthca_pd_free(dev, &dev->driver_pd);
  726. err_mr_table_free:
  727. mthca_cleanup_mr_table(dev);
  728. err_pd_table_free:
  729. mthca_cleanup_pd_table(dev);
  730. err_kar_unmap:
  731. iounmap(dev->kar);
  732. err_uar_free:
  733. mthca_uar_free(dev, &dev->driver_uar);
  734. err_uar_table_free:
  735. mthca_cleanup_uar_table(dev);
  736. return err;
  737. }
  738. static int __devinit mthca_request_regions(struct pci_dev *pdev,
  739. int ddr_hidden)
  740. {
  741. int err;
  742. /*
  743. * We can't just use pci_request_regions() because the MSI-X
  744. * table is right in the middle of the first BAR. If we did
  745. * pci_request_region and grab all of the first BAR, then
  746. * setting up MSI-X would fail, since the PCI core wants to do
  747. * request_mem_region on the MSI-X vector table.
  748. *
  749. * So just request what we need right now, and request any
  750. * other regions we need when setting up EQs.
  751. */
  752. if (!request_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  753. MTHCA_HCR_SIZE, DRV_NAME))
  754. return -EBUSY;
  755. err = pci_request_region(pdev, 2, DRV_NAME);
  756. if (err)
  757. goto err_bar2_failed;
  758. if (!ddr_hidden) {
  759. err = pci_request_region(pdev, 4, DRV_NAME);
  760. if (err)
  761. goto err_bar4_failed;
  762. }
  763. return 0;
  764. err_bar4_failed:
  765. pci_release_region(pdev, 2);
  766. err_bar2_failed:
  767. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  768. MTHCA_HCR_SIZE);
  769. return err;
  770. }
  771. static void mthca_release_regions(struct pci_dev *pdev,
  772. int ddr_hidden)
  773. {
  774. if (!ddr_hidden)
  775. pci_release_region(pdev, 4);
  776. pci_release_region(pdev, 2);
  777. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  778. MTHCA_HCR_SIZE);
  779. }
  780. static int __devinit mthca_enable_msi_x(struct mthca_dev *mdev)
  781. {
  782. struct msix_entry entries[3];
  783. int err;
  784. entries[0].entry = 0;
  785. entries[1].entry = 1;
  786. entries[2].entry = 2;
  787. err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
  788. if (err) {
  789. if (err > 0)
  790. mthca_info(mdev, "Only %d MSI-X vectors available, "
  791. "not using MSI-X\n", err);
  792. return err;
  793. }
  794. mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
  795. mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
  796. mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
  797. return 0;
  798. }
  799. /* Types of supported HCA */
  800. enum {
  801. TAVOR, /* MT23108 */
  802. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  803. ARBEL_NATIVE, /* MT25208 with extended features */
  804. SINAI /* MT25204 */
  805. };
  806. #define MTHCA_FW_VER(major, minor, subminor) \
  807. (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
  808. static struct {
  809. u64 latest_fw;
  810. u32 flags;
  811. } mthca_hca_table[] = {
  812. [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 4, 0),
  813. .flags = 0 },
  814. [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 7, 400),
  815. .flags = MTHCA_FLAG_PCIE },
  816. [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 1, 0),
  817. .flags = MTHCA_FLAG_MEMFREE |
  818. MTHCA_FLAG_PCIE },
  819. [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 0, 800),
  820. .flags = MTHCA_FLAG_MEMFREE |
  821. MTHCA_FLAG_PCIE |
  822. MTHCA_FLAG_SINAI_OPT }
  823. };
  824. static int __devinit mthca_init_one(struct pci_dev *pdev,
  825. const struct pci_device_id *id)
  826. {
  827. static int mthca_version_printed = 0;
  828. int ddr_hidden = 0;
  829. int err;
  830. struct mthca_dev *mdev;
  831. if (!mthca_version_printed) {
  832. printk(KERN_INFO "%s", mthca_version);
  833. ++mthca_version_printed;
  834. }
  835. printk(KERN_INFO PFX "Initializing %s\n",
  836. pci_name(pdev));
  837. if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
  838. printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
  839. pci_name(pdev), id->driver_data);
  840. return -ENODEV;
  841. }
  842. err = pci_enable_device(pdev);
  843. if (err) {
  844. dev_err(&pdev->dev, "Cannot enable PCI device, "
  845. "aborting.\n");
  846. return err;
  847. }
  848. /*
  849. * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
  850. * be present)
  851. */
  852. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  853. pci_resource_len(pdev, 0) != 1 << 20) {
  854. dev_err(&pdev->dev, "Missing DCS, aborting.\n");
  855. err = -ENODEV;
  856. goto err_disable_pdev;
  857. }
  858. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  859. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  860. err = -ENODEV;
  861. goto err_disable_pdev;
  862. }
  863. if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
  864. ddr_hidden = 1;
  865. err = mthca_request_regions(pdev, ddr_hidden);
  866. if (err) {
  867. dev_err(&pdev->dev, "Cannot obtain PCI resources, "
  868. "aborting.\n");
  869. goto err_disable_pdev;
  870. }
  871. pci_set_master(pdev);
  872. err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  873. if (err) {
  874. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  875. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  876. if (err) {
  877. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  878. goto err_free_res;
  879. }
  880. }
  881. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  882. if (err) {
  883. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  884. "consistent PCI DMA mask.\n");
  885. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  886. if (err) {
  887. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  888. "aborting.\n");
  889. goto err_free_res;
  890. }
  891. }
  892. mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
  893. if (!mdev) {
  894. dev_err(&pdev->dev, "Device struct alloc failed, "
  895. "aborting.\n");
  896. err = -ENOMEM;
  897. goto err_free_res;
  898. }
  899. mdev->pdev = pdev;
  900. mdev->mthca_flags = mthca_hca_table[id->driver_data].flags;
  901. if (ddr_hidden)
  902. mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
  903. /*
  904. * Now reset the HCA before we touch the PCI capabilities or
  905. * attempt a firmware command, since a boot ROM may have left
  906. * the HCA in an undefined state.
  907. */
  908. err = mthca_reset(mdev);
  909. if (err) {
  910. mthca_err(mdev, "Failed to reset HCA, aborting.\n");
  911. goto err_free_dev;
  912. }
  913. if (msi_x && !mthca_enable_msi_x(mdev))
  914. mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
  915. if (msi && !(mdev->mthca_flags & MTHCA_FLAG_MSI_X) &&
  916. !pci_enable_msi(pdev))
  917. mdev->mthca_flags |= MTHCA_FLAG_MSI;
  918. if (mthca_cmd_init(mdev)) {
  919. mthca_err(mdev, "Failed to init command interface, aborting.\n");
  920. goto err_free_dev;
  921. }
  922. err = mthca_tune_pci(mdev);
  923. if (err)
  924. goto err_cmd;
  925. err = mthca_init_hca(mdev);
  926. if (err)
  927. goto err_cmd;
  928. if (mdev->fw_ver < mthca_hca_table[id->driver_data].latest_fw) {
  929. mthca_warn(mdev, "HCA FW version %d.%d.%d is old (%d.%d.%d is current).\n",
  930. (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
  931. (int) (mdev->fw_ver & 0xffff),
  932. (int) (mthca_hca_table[id->driver_data].latest_fw >> 32),
  933. (int) (mthca_hca_table[id->driver_data].latest_fw >> 16) & 0xffff,
  934. (int) (mthca_hca_table[id->driver_data].latest_fw & 0xffff));
  935. mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
  936. }
  937. err = mthca_setup_hca(mdev);
  938. if (err)
  939. goto err_close;
  940. err = mthca_register_device(mdev);
  941. if (err)
  942. goto err_cleanup;
  943. err = mthca_create_agents(mdev);
  944. if (err)
  945. goto err_unregister;
  946. pci_set_drvdata(pdev, mdev);
  947. return 0;
  948. err_unregister:
  949. mthca_unregister_device(mdev);
  950. err_cleanup:
  951. mthca_cleanup_mcg_table(mdev);
  952. mthca_cleanup_av_table(mdev);
  953. mthca_cleanup_qp_table(mdev);
  954. mthca_cleanup_srq_table(mdev);
  955. mthca_cleanup_cq_table(mdev);
  956. mthca_cmd_use_polling(mdev);
  957. mthca_cleanup_eq_table(mdev);
  958. mthca_pd_free(mdev, &mdev->driver_pd);
  959. mthca_cleanup_mr_table(mdev);
  960. mthca_cleanup_pd_table(mdev);
  961. mthca_cleanup_uar_table(mdev);
  962. err_close:
  963. mthca_close_hca(mdev);
  964. err_cmd:
  965. mthca_cmd_cleanup(mdev);
  966. err_free_dev:
  967. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  968. pci_disable_msix(pdev);
  969. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  970. pci_disable_msi(pdev);
  971. ib_dealloc_device(&mdev->ib_dev);
  972. err_free_res:
  973. mthca_release_regions(pdev, ddr_hidden);
  974. err_disable_pdev:
  975. pci_disable_device(pdev);
  976. pci_set_drvdata(pdev, NULL);
  977. return err;
  978. }
  979. static void __devexit mthca_remove_one(struct pci_dev *pdev)
  980. {
  981. struct mthca_dev *mdev = pci_get_drvdata(pdev);
  982. u8 status;
  983. int p;
  984. if (mdev) {
  985. mthca_free_agents(mdev);
  986. mthca_unregister_device(mdev);
  987. for (p = 1; p <= mdev->limits.num_ports; ++p)
  988. mthca_CLOSE_IB(mdev, p, &status);
  989. mthca_cleanup_mcg_table(mdev);
  990. mthca_cleanup_av_table(mdev);
  991. mthca_cleanup_qp_table(mdev);
  992. mthca_cleanup_srq_table(mdev);
  993. mthca_cleanup_cq_table(mdev);
  994. mthca_cmd_use_polling(mdev);
  995. mthca_cleanup_eq_table(mdev);
  996. mthca_pd_free(mdev, &mdev->driver_pd);
  997. mthca_cleanup_mr_table(mdev);
  998. mthca_cleanup_pd_table(mdev);
  999. iounmap(mdev->kar);
  1000. mthca_uar_free(mdev, &mdev->driver_uar);
  1001. mthca_cleanup_uar_table(mdev);
  1002. mthca_close_hca(mdev);
  1003. mthca_cmd_cleanup(mdev);
  1004. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  1005. pci_disable_msix(pdev);
  1006. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  1007. pci_disable_msi(pdev);
  1008. ib_dealloc_device(&mdev->ib_dev);
  1009. mthca_release_regions(pdev, mdev->mthca_flags &
  1010. MTHCA_FLAG_DDR_HIDDEN);
  1011. pci_disable_device(pdev);
  1012. pci_set_drvdata(pdev, NULL);
  1013. }
  1014. }
  1015. static struct pci_device_id mthca_pci_table[] = {
  1016. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1017. .driver_data = TAVOR },
  1018. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1019. .driver_data = TAVOR },
  1020. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1021. .driver_data = ARBEL_COMPAT },
  1022. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1023. .driver_data = ARBEL_COMPAT },
  1024. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1025. .driver_data = ARBEL_NATIVE },
  1026. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1027. .driver_data = ARBEL_NATIVE },
  1028. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
  1029. .driver_data = SINAI },
  1030. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
  1031. .driver_data = SINAI },
  1032. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1033. .driver_data = SINAI },
  1034. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1035. .driver_data = SINAI },
  1036. { 0, }
  1037. };
  1038. MODULE_DEVICE_TABLE(pci, mthca_pci_table);
  1039. static struct pci_driver mthca_driver = {
  1040. .name = DRV_NAME,
  1041. .id_table = mthca_pci_table,
  1042. .probe = mthca_init_one,
  1043. .remove = __devexit_p(mthca_remove_one)
  1044. };
  1045. static int __init mthca_init(void)
  1046. {
  1047. int ret;
  1048. ret = pci_register_driver(&mthca_driver);
  1049. return ret < 0 ? ret : 0;
  1050. }
  1051. static void __exit mthca_cleanup(void)
  1052. {
  1053. pci_unregister_driver(&mthca_driver);
  1054. }
  1055. module_init(mthca_init);
  1056. module_exit(mthca_cleanup);