mthca_dev.h 18 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.
  5. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  6. * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
  7. *
  8. * This software is available to you under a choice of one of two
  9. * licenses. You may choose to be licensed under the terms of the GNU
  10. * General Public License (GPL) Version 2, available from the file
  11. * COPYING in the main directory of this source tree, or the
  12. * OpenIB.org BSD license below:
  13. *
  14. * Redistribution and use in source and binary forms, with or
  15. * without modification, are permitted provided that the following
  16. * conditions are met:
  17. *
  18. * - Redistributions of source code must retain the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer.
  21. *
  22. * - Redistributions in binary form must reproduce the above
  23. * copyright notice, this list of conditions and the following
  24. * disclaimer in the documentation and/or other materials
  25. * provided with the distribution.
  26. *
  27. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  28. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  29. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  30. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  31. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  32. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  33. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  34. * SOFTWARE.
  35. *
  36. * $Id: mthca_dev.h 1349 2004-12-16 21:09:43Z roland $
  37. */
  38. #ifndef MTHCA_DEV_H
  39. #define MTHCA_DEV_H
  40. #include <linux/spinlock.h>
  41. #include <linux/kernel.h>
  42. #include <linux/pci.h>
  43. #include <linux/dma-mapping.h>
  44. #include <linux/timer.h>
  45. #include <linux/mutex.h>
  46. #include <asm/semaphore.h>
  47. #include "mthca_provider.h"
  48. #include "mthca_doorbell.h"
  49. #define DRV_NAME "ib_mthca"
  50. #define PFX DRV_NAME ": "
  51. #define DRV_VERSION "0.08"
  52. #define DRV_RELDATE "February 14, 2006"
  53. enum {
  54. MTHCA_FLAG_DDR_HIDDEN = 1 << 1,
  55. MTHCA_FLAG_SRQ = 1 << 2,
  56. MTHCA_FLAG_MSI = 1 << 3,
  57. MTHCA_FLAG_MSI_X = 1 << 4,
  58. MTHCA_FLAG_NO_LAM = 1 << 5,
  59. MTHCA_FLAG_FMR = 1 << 6,
  60. MTHCA_FLAG_MEMFREE = 1 << 7,
  61. MTHCA_FLAG_PCIE = 1 << 8,
  62. MTHCA_FLAG_SINAI_OPT = 1 << 9
  63. };
  64. enum {
  65. MTHCA_MAX_PORTS = 2
  66. };
  67. enum {
  68. MTHCA_BOARD_ID_LEN = 64
  69. };
  70. enum {
  71. MTHCA_EQ_CONTEXT_SIZE = 0x40,
  72. MTHCA_CQ_CONTEXT_SIZE = 0x40,
  73. MTHCA_QP_CONTEXT_SIZE = 0x200,
  74. MTHCA_RDB_ENTRY_SIZE = 0x20,
  75. MTHCA_AV_SIZE = 0x20,
  76. MTHCA_MGM_ENTRY_SIZE = 0x40,
  77. /* Arbel FW gives us these, but we need them for Tavor */
  78. MTHCA_MPT_ENTRY_SIZE = 0x40,
  79. MTHCA_MTT_SEG_SIZE = 0x40,
  80. MTHCA_QP_PER_MGM = 4 * (MTHCA_MGM_ENTRY_SIZE / 16 - 2)
  81. };
  82. enum {
  83. MTHCA_EQ_CMD,
  84. MTHCA_EQ_ASYNC,
  85. MTHCA_EQ_COMP,
  86. MTHCA_NUM_EQ
  87. };
  88. enum {
  89. MTHCA_OPCODE_NOP = 0x00,
  90. MTHCA_OPCODE_RDMA_WRITE = 0x08,
  91. MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09,
  92. MTHCA_OPCODE_SEND = 0x0a,
  93. MTHCA_OPCODE_SEND_IMM = 0x0b,
  94. MTHCA_OPCODE_RDMA_READ = 0x10,
  95. MTHCA_OPCODE_ATOMIC_CS = 0x11,
  96. MTHCA_OPCODE_ATOMIC_FA = 0x12,
  97. MTHCA_OPCODE_BIND_MW = 0x18,
  98. MTHCA_OPCODE_INVALID = 0xff
  99. };
  100. enum {
  101. MTHCA_CMD_USE_EVENTS = 1 << 0,
  102. MTHCA_CMD_POST_DOORBELLS = 1 << 1
  103. };
  104. enum {
  105. MTHCA_CMD_NUM_DBELL_DWORDS = 8
  106. };
  107. struct mthca_cmd {
  108. struct pci_pool *pool;
  109. struct mutex hcr_mutex;
  110. struct semaphore poll_sem;
  111. struct semaphore event_sem;
  112. int max_cmds;
  113. spinlock_t context_lock;
  114. int free_head;
  115. struct mthca_cmd_context *context;
  116. u16 token_mask;
  117. u32 flags;
  118. void __iomem *dbell_map;
  119. u16 dbell_offsets[MTHCA_CMD_NUM_DBELL_DWORDS];
  120. };
  121. struct mthca_limits {
  122. int num_ports;
  123. int vl_cap;
  124. int mtu_cap;
  125. int gid_table_len;
  126. int pkey_table_len;
  127. int local_ca_ack_delay;
  128. int num_uars;
  129. int max_sg;
  130. int num_qps;
  131. int max_wqes;
  132. int max_desc_sz;
  133. int max_qp_init_rdma;
  134. int reserved_qps;
  135. int num_srqs;
  136. int max_srq_wqes;
  137. int max_srq_sge;
  138. int reserved_srqs;
  139. int num_eecs;
  140. int reserved_eecs;
  141. int num_cqs;
  142. int max_cqes;
  143. int reserved_cqs;
  144. int num_eqs;
  145. int reserved_eqs;
  146. int num_mpts;
  147. int num_mtt_segs;
  148. int fmr_reserved_mtts;
  149. int reserved_mtts;
  150. int reserved_mrws;
  151. int reserved_uars;
  152. int num_mgms;
  153. int num_amgms;
  154. int reserved_mcgs;
  155. int num_pds;
  156. int reserved_pds;
  157. u32 page_size_cap;
  158. u32 flags;
  159. u16 stat_rate_support;
  160. u8 port_width_cap;
  161. };
  162. struct mthca_alloc {
  163. u32 last;
  164. u32 top;
  165. u32 max;
  166. u32 mask;
  167. spinlock_t lock;
  168. unsigned long *table;
  169. };
  170. struct mthca_array {
  171. struct {
  172. void **page;
  173. int used;
  174. } *page_list;
  175. };
  176. struct mthca_uar_table {
  177. struct mthca_alloc alloc;
  178. u64 uarc_base;
  179. int uarc_size;
  180. };
  181. struct mthca_pd_table {
  182. struct mthca_alloc alloc;
  183. };
  184. struct mthca_buddy {
  185. unsigned long **bits;
  186. int max_order;
  187. spinlock_t lock;
  188. };
  189. struct mthca_mr_table {
  190. struct mthca_alloc mpt_alloc;
  191. struct mthca_buddy mtt_buddy;
  192. struct mthca_buddy *fmr_mtt_buddy;
  193. u64 mtt_base;
  194. u64 mpt_base;
  195. struct mthca_icm_table *mtt_table;
  196. struct mthca_icm_table *mpt_table;
  197. struct {
  198. void __iomem *mpt_base;
  199. void __iomem *mtt_base;
  200. struct mthca_buddy mtt_buddy;
  201. } tavor_fmr;
  202. };
  203. struct mthca_eq_table {
  204. struct mthca_alloc alloc;
  205. void __iomem *clr_int;
  206. u32 clr_mask;
  207. u32 arm_mask;
  208. struct mthca_eq eq[MTHCA_NUM_EQ];
  209. u64 icm_virt;
  210. struct page *icm_page;
  211. dma_addr_t icm_dma;
  212. int have_irq;
  213. u8 inta_pin;
  214. };
  215. struct mthca_cq_table {
  216. struct mthca_alloc alloc;
  217. spinlock_t lock;
  218. struct mthca_array cq;
  219. struct mthca_icm_table *table;
  220. };
  221. struct mthca_srq_table {
  222. struct mthca_alloc alloc;
  223. spinlock_t lock;
  224. struct mthca_array srq;
  225. struct mthca_icm_table *table;
  226. };
  227. struct mthca_qp_table {
  228. struct mthca_alloc alloc;
  229. u32 rdb_base;
  230. int rdb_shift;
  231. int sqp_start;
  232. spinlock_t lock;
  233. struct mthca_array qp;
  234. struct mthca_icm_table *qp_table;
  235. struct mthca_icm_table *eqp_table;
  236. struct mthca_icm_table *rdb_table;
  237. };
  238. struct mthca_av_table {
  239. struct pci_pool *pool;
  240. int num_ddr_avs;
  241. u64 ddr_av_base;
  242. void __iomem *av_map;
  243. struct mthca_alloc alloc;
  244. };
  245. struct mthca_mcg_table {
  246. struct mutex mutex;
  247. struct mthca_alloc alloc;
  248. struct mthca_icm_table *table;
  249. };
  250. struct mthca_catas_err {
  251. u64 addr;
  252. u32 __iomem *map;
  253. unsigned long stop;
  254. u32 size;
  255. struct timer_list timer;
  256. };
  257. struct mthca_dev {
  258. struct ib_device ib_dev;
  259. struct pci_dev *pdev;
  260. int hca_type;
  261. unsigned long mthca_flags;
  262. unsigned long device_cap_flags;
  263. u32 rev_id;
  264. char board_id[MTHCA_BOARD_ID_LEN];
  265. /* firmware info */
  266. u64 fw_ver;
  267. union {
  268. struct {
  269. u64 fw_start;
  270. u64 fw_end;
  271. } tavor;
  272. struct {
  273. u64 clr_int_base;
  274. u64 eq_arm_base;
  275. u64 eq_set_ci_base;
  276. struct mthca_icm *fw_icm;
  277. struct mthca_icm *aux_icm;
  278. u16 fw_pages;
  279. } arbel;
  280. } fw;
  281. u64 ddr_start;
  282. u64 ddr_end;
  283. MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock)
  284. struct mutex cap_mask_mutex;
  285. void __iomem *hcr;
  286. void __iomem *kar;
  287. void __iomem *clr_base;
  288. union {
  289. struct {
  290. void __iomem *ecr_base;
  291. } tavor;
  292. struct {
  293. void __iomem *eq_arm;
  294. void __iomem *eq_set_ci_base;
  295. } arbel;
  296. } eq_regs;
  297. struct mthca_cmd cmd;
  298. struct mthca_limits limits;
  299. struct mthca_uar_table uar_table;
  300. struct mthca_pd_table pd_table;
  301. struct mthca_mr_table mr_table;
  302. struct mthca_eq_table eq_table;
  303. struct mthca_cq_table cq_table;
  304. struct mthca_srq_table srq_table;
  305. struct mthca_qp_table qp_table;
  306. struct mthca_av_table av_table;
  307. struct mthca_mcg_table mcg_table;
  308. struct mthca_catas_err catas_err;
  309. struct mthca_uar driver_uar;
  310. struct mthca_db_table *db_tab;
  311. struct mthca_pd driver_pd;
  312. struct mthca_mr driver_mr;
  313. struct ib_mad_agent *send_agent[MTHCA_MAX_PORTS][2];
  314. struct ib_ah *sm_ah[MTHCA_MAX_PORTS];
  315. spinlock_t sm_lock;
  316. u8 rate[MTHCA_MAX_PORTS];
  317. };
  318. #ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
  319. extern int mthca_debug_level;
  320. #define mthca_dbg(mdev, format, arg...) \
  321. do { \
  322. if (mthca_debug_level) \
  323. dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ## arg); \
  324. } while (0)
  325. #else /* CONFIG_INFINIBAND_MTHCA_DEBUG */
  326. #define mthca_dbg(mdev, format, arg...) do { (void) mdev; } while (0)
  327. #endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
  328. #define mthca_err(mdev, format, arg...) \
  329. dev_err(&mdev->pdev->dev, format, ## arg)
  330. #define mthca_info(mdev, format, arg...) \
  331. dev_info(&mdev->pdev->dev, format, ## arg)
  332. #define mthca_warn(mdev, format, arg...) \
  333. dev_warn(&mdev->pdev->dev, format, ## arg)
  334. extern void __buggy_use_of_MTHCA_GET(void);
  335. extern void __buggy_use_of_MTHCA_PUT(void);
  336. #define MTHCA_GET(dest, source, offset) \
  337. do { \
  338. void *__p = (char *) (source) + (offset); \
  339. switch (sizeof (dest)) { \
  340. case 1: (dest) = *(u8 *) __p; break; \
  341. case 2: (dest) = be16_to_cpup(__p); break; \
  342. case 4: (dest) = be32_to_cpup(__p); break; \
  343. case 8: (dest) = be64_to_cpup(__p); break; \
  344. default: __buggy_use_of_MTHCA_GET(); \
  345. } \
  346. } while (0)
  347. #define MTHCA_PUT(dest, source, offset) \
  348. do { \
  349. void *__d = ((char *) (dest) + (offset)); \
  350. switch (sizeof(source)) { \
  351. case 1: *(u8 *) __d = (source); break; \
  352. case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
  353. case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
  354. case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
  355. default: __buggy_use_of_MTHCA_PUT(); \
  356. } \
  357. } while (0)
  358. int mthca_reset(struct mthca_dev *mdev);
  359. u32 mthca_alloc(struct mthca_alloc *alloc);
  360. void mthca_free(struct mthca_alloc *alloc, u32 obj);
  361. int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask,
  362. u32 reserved);
  363. void mthca_alloc_cleanup(struct mthca_alloc *alloc);
  364. void *mthca_array_get(struct mthca_array *array, int index);
  365. int mthca_array_set(struct mthca_array *array, int index, void *value);
  366. void mthca_array_clear(struct mthca_array *array, int index);
  367. int mthca_array_init(struct mthca_array *array, int nent);
  368. void mthca_array_cleanup(struct mthca_array *array, int nent);
  369. int mthca_buf_alloc(struct mthca_dev *dev, int size, int max_direct,
  370. union mthca_buf *buf, int *is_direct, struct mthca_pd *pd,
  371. int hca_write, struct mthca_mr *mr);
  372. void mthca_buf_free(struct mthca_dev *dev, int size, union mthca_buf *buf,
  373. int is_direct, struct mthca_mr *mr);
  374. int mthca_init_uar_table(struct mthca_dev *dev);
  375. int mthca_init_pd_table(struct mthca_dev *dev);
  376. int mthca_init_mr_table(struct mthca_dev *dev);
  377. int mthca_init_eq_table(struct mthca_dev *dev);
  378. int mthca_init_cq_table(struct mthca_dev *dev);
  379. int mthca_init_srq_table(struct mthca_dev *dev);
  380. int mthca_init_qp_table(struct mthca_dev *dev);
  381. int mthca_init_av_table(struct mthca_dev *dev);
  382. int mthca_init_mcg_table(struct mthca_dev *dev);
  383. void mthca_cleanup_uar_table(struct mthca_dev *dev);
  384. void mthca_cleanup_pd_table(struct mthca_dev *dev);
  385. void mthca_cleanup_mr_table(struct mthca_dev *dev);
  386. void mthca_cleanup_eq_table(struct mthca_dev *dev);
  387. void mthca_cleanup_cq_table(struct mthca_dev *dev);
  388. void mthca_cleanup_srq_table(struct mthca_dev *dev);
  389. void mthca_cleanup_qp_table(struct mthca_dev *dev);
  390. void mthca_cleanup_av_table(struct mthca_dev *dev);
  391. void mthca_cleanup_mcg_table(struct mthca_dev *dev);
  392. int mthca_register_device(struct mthca_dev *dev);
  393. void mthca_unregister_device(struct mthca_dev *dev);
  394. void mthca_start_catas_poll(struct mthca_dev *dev);
  395. void mthca_stop_catas_poll(struct mthca_dev *dev);
  396. int mthca_uar_alloc(struct mthca_dev *dev, struct mthca_uar *uar);
  397. void mthca_uar_free(struct mthca_dev *dev, struct mthca_uar *uar);
  398. int mthca_pd_alloc(struct mthca_dev *dev, int privileged, struct mthca_pd *pd);
  399. void mthca_pd_free(struct mthca_dev *dev, struct mthca_pd *pd);
  400. struct mthca_mtt *mthca_alloc_mtt(struct mthca_dev *dev, int size);
  401. void mthca_free_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt);
  402. int mthca_write_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt,
  403. int start_index, u64 *buffer_list, int list_len);
  404. int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift,
  405. u64 iova, u64 total_size, u32 access, struct mthca_mr *mr);
  406. int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,
  407. u32 access, struct mthca_mr *mr);
  408. int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,
  409. u64 *buffer_list, int buffer_size_shift,
  410. int list_len, u64 iova, u64 total_size,
  411. u32 access, struct mthca_mr *mr);
  412. void mthca_free_mr(struct mthca_dev *dev, struct mthca_mr *mr);
  413. int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd,
  414. u32 access, struct mthca_fmr *fmr);
  415. int mthca_tavor_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
  416. int list_len, u64 iova);
  417. void mthca_tavor_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
  418. int mthca_arbel_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
  419. int list_len, u64 iova);
  420. void mthca_arbel_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
  421. int mthca_free_fmr(struct mthca_dev *dev, struct mthca_fmr *fmr);
  422. int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt);
  423. void mthca_unmap_eq_icm(struct mthca_dev *dev);
  424. int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
  425. struct ib_wc *entry);
  426. int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
  427. int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
  428. int mthca_init_cq(struct mthca_dev *dev, int nent,
  429. struct mthca_ucontext *ctx, u32 pdn,
  430. struct mthca_cq *cq);
  431. void mthca_free_cq(struct mthca_dev *dev,
  432. struct mthca_cq *cq);
  433. void mthca_cq_completion(struct mthca_dev *dev, u32 cqn);
  434. void mthca_cq_event(struct mthca_dev *dev, u32 cqn,
  435. enum ib_event_type event_type);
  436. void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn,
  437. struct mthca_srq *srq);
  438. void mthca_cq_resize_copy_cqes(struct mthca_cq *cq);
  439. int mthca_alloc_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int nent);
  440. void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int cqe);
  441. int mthca_alloc_srq(struct mthca_dev *dev, struct mthca_pd *pd,
  442. struct ib_srq_attr *attr, struct mthca_srq *srq);
  443. void mthca_free_srq(struct mthca_dev *dev, struct mthca_srq *srq);
  444. int mthca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
  445. enum ib_srq_attr_mask attr_mask);
  446. int mthca_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr);
  447. int mthca_max_srq_sge(struct mthca_dev *dev);
  448. void mthca_srq_event(struct mthca_dev *dev, u32 srqn,
  449. enum ib_event_type event_type);
  450. void mthca_free_srq_wqe(struct mthca_srq *srq, u32 wqe_addr);
  451. int mthca_tavor_post_srq_recv(struct ib_srq *srq, struct ib_recv_wr *wr,
  452. struct ib_recv_wr **bad_wr);
  453. int mthca_arbel_post_srq_recv(struct ib_srq *srq, struct ib_recv_wr *wr,
  454. struct ib_recv_wr **bad_wr);
  455. void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
  456. enum ib_event_type event_type);
  457. int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
  458. struct ib_qp_init_attr *qp_init_attr);
  459. int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask);
  460. int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
  461. struct ib_send_wr **bad_wr);
  462. int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
  463. struct ib_recv_wr **bad_wr);
  464. int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
  465. struct ib_send_wr **bad_wr);
  466. int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
  467. struct ib_recv_wr **bad_wr);
  468. void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
  469. int index, int *dbd, __be32 *new_wqe);
  470. int mthca_alloc_qp(struct mthca_dev *dev,
  471. struct mthca_pd *pd,
  472. struct mthca_cq *send_cq,
  473. struct mthca_cq *recv_cq,
  474. enum ib_qp_type type,
  475. enum ib_sig_type send_policy,
  476. struct ib_qp_cap *cap,
  477. struct mthca_qp *qp);
  478. int mthca_alloc_sqp(struct mthca_dev *dev,
  479. struct mthca_pd *pd,
  480. struct mthca_cq *send_cq,
  481. struct mthca_cq *recv_cq,
  482. enum ib_sig_type send_policy,
  483. struct ib_qp_cap *cap,
  484. int qpn,
  485. int port,
  486. struct mthca_sqp *sqp);
  487. void mthca_free_qp(struct mthca_dev *dev, struct mthca_qp *qp);
  488. int mthca_create_ah(struct mthca_dev *dev,
  489. struct mthca_pd *pd,
  490. struct ib_ah_attr *ah_attr,
  491. struct mthca_ah *ah);
  492. int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah);
  493. int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah,
  494. struct ib_ud_header *header);
  495. int mthca_ah_query(struct ib_ah *ibah, struct ib_ah_attr *attr);
  496. int mthca_ah_grh_present(struct mthca_ah *ah);
  497. u8 mthca_get_rate(struct mthca_dev *dev, int static_rate, u8 port);
  498. enum ib_rate mthca_rate_to_ib(struct mthca_dev *dev, u8 mthca_rate, u8 port);
  499. int mthca_multicast_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
  500. int mthca_multicast_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
  501. int mthca_process_mad(struct ib_device *ibdev,
  502. int mad_flags,
  503. u8 port_num,
  504. struct ib_wc *in_wc,
  505. struct ib_grh *in_grh,
  506. struct ib_mad *in_mad,
  507. struct ib_mad *out_mad);
  508. int mthca_create_agents(struct mthca_dev *dev);
  509. void mthca_free_agents(struct mthca_dev *dev);
  510. static inline struct mthca_dev *to_mdev(struct ib_device *ibdev)
  511. {
  512. return container_of(ibdev, struct mthca_dev, ib_dev);
  513. }
  514. static inline int mthca_is_memfree(struct mthca_dev *dev)
  515. {
  516. return dev->mthca_flags & MTHCA_FLAG_MEMFREE;
  517. }
  518. #endif /* MTHCA_DEV_H */