ipath_intr.c 24 KB

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  1. /*
  2. * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/pci.h>
  33. #include "ipath_kernel.h"
  34. #include "ips_common.h"
  35. #include "ipath_layer.h"
  36. #define E_SUM_PKTERRS \
  37. (INFINIPATH_E_RHDRLEN | INFINIPATH_E_RBADTID | \
  38. INFINIPATH_E_RBADVERSION | INFINIPATH_E_RHDR | \
  39. INFINIPATH_E_RLONGPKTLEN | INFINIPATH_E_RSHORTPKTLEN | \
  40. INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RMINPKTLEN | \
  41. INFINIPATH_E_RFORMATERR | INFINIPATH_E_RUNSUPVL | \
  42. INFINIPATH_E_RUNEXPCHAR | INFINIPATH_E_REBP)
  43. #define E_SUM_ERRS \
  44. (INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM | \
  45. INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
  46. INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SUNSUPVL | \
  47. INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \
  48. INFINIPATH_E_INVALIDADDR)
  49. static u64 handle_e_sum_errs(struct ipath_devdata *dd, ipath_err_t errs)
  50. {
  51. unsigned long sbuf[4];
  52. u64 ignore_this_time = 0;
  53. u32 piobcnt;
  54. /* if possible that sendbuffererror could be valid */
  55. piobcnt = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
  56. /* read these before writing errorclear */
  57. sbuf[0] = ipath_read_kreg64(
  58. dd, dd->ipath_kregs->kr_sendbuffererror);
  59. sbuf[1] = ipath_read_kreg64(
  60. dd, dd->ipath_kregs->kr_sendbuffererror + 1);
  61. if (piobcnt > 128) {
  62. sbuf[2] = ipath_read_kreg64(
  63. dd, dd->ipath_kregs->kr_sendbuffererror + 2);
  64. sbuf[3] = ipath_read_kreg64(
  65. dd, dd->ipath_kregs->kr_sendbuffererror + 3);
  66. }
  67. if (sbuf[0] || sbuf[1] || (piobcnt > 128 && (sbuf[2] || sbuf[3]))) {
  68. int i;
  69. ipath_cdbg(PKT, "SendbufErrs %lx %lx ", sbuf[0], sbuf[1]);
  70. if (ipath_debug & __IPATH_PKTDBG && piobcnt > 128)
  71. printk("%lx %lx ", sbuf[2], sbuf[3]);
  72. for (i = 0; i < piobcnt; i++) {
  73. if (test_bit(i, sbuf)) {
  74. u32 __iomem *piobuf;
  75. if (i < dd->ipath_piobcnt2k)
  76. piobuf = (u32 __iomem *)
  77. (dd->ipath_pio2kbase +
  78. i * dd->ipath_palign);
  79. else
  80. piobuf = (u32 __iomem *)
  81. (dd->ipath_pio4kbase +
  82. (i - dd->ipath_piobcnt2k) *
  83. dd->ipath_4kalign);
  84. ipath_cdbg(PKT,
  85. "PIObuf[%u] @%p pbc is %x; ",
  86. i, piobuf, readl(piobuf));
  87. ipath_disarm_piobufs(dd, i, 1);
  88. }
  89. }
  90. if (ipath_debug & __IPATH_PKTDBG)
  91. printk("\n");
  92. }
  93. if ((errs & (INFINIPATH_E_SDROPPEDDATAPKT |
  94. INFINIPATH_E_SDROPPEDSMPPKT |
  95. INFINIPATH_E_SMINPKTLEN)) &&
  96. !(dd->ipath_flags & IPATH_LINKACTIVE)) {
  97. /*
  98. * This can happen when SMA is trying to bring the link
  99. * up, but the IB link changes state at the "wrong" time.
  100. * The IB logic then complains that the packet isn't
  101. * valid. We don't want to confuse people, so we just
  102. * don't print them, except at debug
  103. */
  104. ipath_dbg("Ignoring pktsend errors %llx, because not "
  105. "yet active\n", (unsigned long long) errs);
  106. ignore_this_time = INFINIPATH_E_SDROPPEDDATAPKT |
  107. INFINIPATH_E_SDROPPEDSMPPKT |
  108. INFINIPATH_E_SMINPKTLEN;
  109. }
  110. return ignore_this_time;
  111. }
  112. /* return the strings for the most common link states */
  113. static char *ib_linkstate(u32 linkstate)
  114. {
  115. char *ret;
  116. switch (linkstate) {
  117. case IPATH_IBSTATE_INIT:
  118. ret = "Init";
  119. break;
  120. case IPATH_IBSTATE_ARM:
  121. ret = "Arm";
  122. break;
  123. case IPATH_IBSTATE_ACTIVE:
  124. ret = "Active";
  125. break;
  126. default:
  127. ret = "Down";
  128. }
  129. return ret;
  130. }
  131. static void handle_e_ibstatuschanged(struct ipath_devdata *dd,
  132. ipath_err_t errs, int noprint)
  133. {
  134. u64 val;
  135. u32 ltstate, lstate;
  136. /*
  137. * even if diags are enabled, we want to notice LINKINIT, etc.
  138. * We just don't want to change the LED state, or
  139. * dd->ipath_kregs->kr_ibcctrl
  140. */
  141. val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
  142. lstate = val & IPATH_IBSTATE_MASK;
  143. if (lstate == IPATH_IBSTATE_INIT || lstate == IPATH_IBSTATE_ARM ||
  144. lstate == IPATH_IBSTATE_ACTIVE) {
  145. /*
  146. * only print at SMA if there is a change, debug if not
  147. * (sometimes we want to know that, usually not).
  148. */
  149. if (lstate == ((unsigned) dd->ipath_lastibcstat
  150. & IPATH_IBSTATE_MASK)) {
  151. ipath_dbg("Status change intr but no change (%s)\n",
  152. ib_linkstate(lstate));
  153. }
  154. else
  155. ipath_cdbg(SMA, "Unit %u link state %s, last "
  156. "was %s\n", dd->ipath_unit,
  157. ib_linkstate(lstate),
  158. ib_linkstate((unsigned)
  159. dd->ipath_lastibcstat
  160. & IPATH_IBSTATE_MASK));
  161. }
  162. else {
  163. lstate = dd->ipath_lastibcstat & IPATH_IBSTATE_MASK;
  164. if (lstate == IPATH_IBSTATE_INIT ||
  165. lstate == IPATH_IBSTATE_ARM ||
  166. lstate == IPATH_IBSTATE_ACTIVE)
  167. ipath_cdbg(SMA, "Unit %u link state down"
  168. " (state 0x%x), from %s\n",
  169. dd->ipath_unit,
  170. (u32)val & IPATH_IBSTATE_MASK,
  171. ib_linkstate(lstate));
  172. else
  173. ipath_cdbg(VERBOSE, "Unit %u link state changed "
  174. "to 0x%x from down (%x)\n",
  175. dd->ipath_unit, (u32) val, lstate);
  176. }
  177. ltstate = (val >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) &
  178. INFINIPATH_IBCS_LINKTRAININGSTATE_MASK;
  179. lstate = (val >> INFINIPATH_IBCS_LINKSTATE_SHIFT) &
  180. INFINIPATH_IBCS_LINKSTATE_MASK;
  181. if (ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE ||
  182. ltstate == INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
  183. u32 last_ltstate;
  184. /*
  185. * Ignore cycling back and forth from Polling.Active
  186. * to Polling.Quiet while waiting for the other end of
  187. * the link to come up. We will cycle back and forth
  188. * between them if no cable is plugged in,
  189. * the other device is powered off or disabled, etc.
  190. */
  191. last_ltstate = (dd->ipath_lastibcstat >>
  192. INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT)
  193. & INFINIPATH_IBCS_LINKTRAININGSTATE_MASK;
  194. if (last_ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE
  195. || last_ltstate ==
  196. INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
  197. if (dd->ipath_ibpollcnt > 40) {
  198. dd->ipath_flags |= IPATH_NOCABLE;
  199. *dd->ipath_statusp |=
  200. IPATH_STATUS_IB_NOCABLE;
  201. } else
  202. dd->ipath_ibpollcnt++;
  203. goto skip_ibchange;
  204. }
  205. }
  206. dd->ipath_ibpollcnt = 0; /* some state other than 2 or 3 */
  207. ipath_stats.sps_iblink++;
  208. if (ltstate != INFINIPATH_IBCS_LT_STATE_LINKUP) {
  209. dd->ipath_flags |= IPATH_LINKDOWN;
  210. dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
  211. | IPATH_LINKACTIVE |
  212. IPATH_LINKARMED);
  213. *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
  214. if (!noprint) {
  215. if (((dd->ipath_lastibcstat >>
  216. INFINIPATH_IBCS_LINKSTATE_SHIFT) &
  217. INFINIPATH_IBCS_LINKSTATE_MASK)
  218. == INFINIPATH_IBCS_L_STATE_ACTIVE)
  219. /* if from up to down be more vocal */
  220. ipath_cdbg(SMA,
  221. "Unit %u link now down (%s)\n",
  222. dd->ipath_unit,
  223. ipath_ibcstatus_str[ltstate]);
  224. else
  225. ipath_cdbg(VERBOSE, "Unit %u link is "
  226. "down (%s)\n", dd->ipath_unit,
  227. ipath_ibcstatus_str[ltstate]);
  228. }
  229. dd->ipath_f_setextled(dd, lstate, ltstate);
  230. } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_ACTIVE) {
  231. dd->ipath_flags |= IPATH_LINKACTIVE;
  232. dd->ipath_flags &=
  233. ~(IPATH_LINKUNK | IPATH_LINKINIT | IPATH_LINKDOWN |
  234. IPATH_LINKARMED | IPATH_NOCABLE);
  235. *dd->ipath_statusp &= ~IPATH_STATUS_IB_NOCABLE;
  236. *dd->ipath_statusp |=
  237. IPATH_STATUS_IB_READY | IPATH_STATUS_IB_CONF;
  238. dd->ipath_f_setextled(dd, lstate, ltstate);
  239. __ipath_layer_intr(dd, IPATH_LAYER_INT_IF_UP);
  240. } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_INIT) {
  241. /*
  242. * set INIT and DOWN. Down is checked by most of the other
  243. * code, but INIT is useful to know in a few places.
  244. */
  245. dd->ipath_flags |= IPATH_LINKINIT | IPATH_LINKDOWN;
  246. dd->ipath_flags &=
  247. ~(IPATH_LINKUNK | IPATH_LINKACTIVE | IPATH_LINKARMED
  248. | IPATH_NOCABLE);
  249. *dd->ipath_statusp &= ~(IPATH_STATUS_IB_NOCABLE
  250. | IPATH_STATUS_IB_READY);
  251. dd->ipath_f_setextled(dd, lstate, ltstate);
  252. } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_ARM) {
  253. dd->ipath_flags |= IPATH_LINKARMED;
  254. dd->ipath_flags &=
  255. ~(IPATH_LINKUNK | IPATH_LINKDOWN | IPATH_LINKINIT |
  256. IPATH_LINKACTIVE | IPATH_NOCABLE);
  257. *dd->ipath_statusp &= ~(IPATH_STATUS_IB_NOCABLE
  258. | IPATH_STATUS_IB_READY);
  259. dd->ipath_f_setextled(dd, lstate, ltstate);
  260. } else {
  261. if (!noprint)
  262. ipath_dbg("IBstatuschange unit %u: %s (%x)\n",
  263. dd->ipath_unit,
  264. ipath_ibcstatus_str[ltstate], ltstate);
  265. }
  266. skip_ibchange:
  267. dd->ipath_lastibcstat = val;
  268. }
  269. static void handle_supp_msgs(struct ipath_devdata *dd,
  270. unsigned supp_msgs, char msg[512])
  271. {
  272. /*
  273. * Print the message unless it's ibc status change only, which
  274. * happens so often we never want to count it.
  275. */
  276. if (dd->ipath_lasterror & ~INFINIPATH_E_IBSTATUSCHANGED) {
  277. ipath_decode_err(msg, sizeof msg, dd->ipath_lasterror &
  278. ~INFINIPATH_E_IBSTATUSCHANGED);
  279. if (dd->ipath_lasterror &
  280. ~(INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL))
  281. ipath_dev_err(dd, "Suppressed %u messages for "
  282. "fast-repeating errors (%s) (%llx)\n",
  283. supp_msgs, msg,
  284. (unsigned long long)
  285. dd->ipath_lasterror);
  286. else {
  287. /*
  288. * rcvegrfull and rcvhdrqfull are "normal", for some
  289. * types of processes (mostly benchmarks) that send
  290. * huge numbers of messages, while not processing
  291. * them. So only complain about these at debug
  292. * level.
  293. */
  294. ipath_dbg("Suppressed %u messages for %s\n",
  295. supp_msgs, msg);
  296. }
  297. }
  298. }
  299. static unsigned handle_frequent_errors(struct ipath_devdata *dd,
  300. ipath_err_t errs, char msg[512],
  301. int *noprint)
  302. {
  303. unsigned long nc;
  304. static unsigned long nextmsg_time;
  305. static unsigned nmsgs, supp_msgs;
  306. /*
  307. * Throttle back "fast" messages to no more than 10 per 5 seconds.
  308. * This isn't perfect, but it's a reasonable heuristic. If we get
  309. * more than 10, give a 6x longer delay.
  310. */
  311. nc = jiffies;
  312. if (nmsgs > 10) {
  313. if (time_before(nc, nextmsg_time)) {
  314. *noprint = 1;
  315. if (!supp_msgs++)
  316. nextmsg_time = nc + HZ * 3;
  317. }
  318. else if (supp_msgs) {
  319. handle_supp_msgs(dd, supp_msgs, msg);
  320. supp_msgs = 0;
  321. nmsgs = 0;
  322. }
  323. }
  324. else if (!nmsgs++ || time_after(nc, nextmsg_time))
  325. nextmsg_time = nc + HZ / 2;
  326. return supp_msgs;
  327. }
  328. static void handle_errors(struct ipath_devdata *dd, ipath_err_t errs)
  329. {
  330. char msg[512];
  331. u64 ignore_this_time = 0;
  332. int i;
  333. int chkerrpkts = 0, noprint = 0;
  334. unsigned supp_msgs;
  335. supp_msgs = handle_frequent_errors(dd, errs, msg, &noprint);
  336. /*
  337. * don't report errors that are masked (includes those always
  338. * ignored)
  339. */
  340. errs &= ~dd->ipath_maskederrs;
  341. /* do these first, they are most important */
  342. if (errs & INFINIPATH_E_HARDWARE) {
  343. /* reuse same msg buf */
  344. dd->ipath_f_handle_hwerrors(dd, msg, sizeof msg);
  345. }
  346. if (!noprint && (errs & ~infinipath_e_bitsextant))
  347. ipath_dev_err(dd, "error interrupt with unknown errors "
  348. "%llx set\n", (unsigned long long)
  349. (errs & ~infinipath_e_bitsextant));
  350. if (errs & E_SUM_ERRS)
  351. ignore_this_time = handle_e_sum_errs(dd, errs);
  352. if (supp_msgs == 250000) {
  353. /*
  354. * It's not entirely reasonable assuming that the errors set
  355. * in the last clear period are all responsible for the
  356. * problem, but the alternative is to assume it's the only
  357. * ones on this particular interrupt, which also isn't great
  358. */
  359. dd->ipath_maskederrs |= dd->ipath_lasterror | errs;
  360. ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
  361. ~dd->ipath_maskederrs);
  362. ipath_decode_err(msg, sizeof msg,
  363. (dd->ipath_maskederrs & ~dd->
  364. ipath_ignorederrs));
  365. if ((dd->ipath_maskederrs & ~dd->ipath_ignorederrs) &
  366. ~(INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL))
  367. ipath_dev_err(dd, "Disabling error(s) %llx because "
  368. "occuring too frequently (%s)\n",
  369. (unsigned long long)
  370. (dd->ipath_maskederrs &
  371. ~dd->ipath_ignorederrs), msg);
  372. else {
  373. /*
  374. * rcvegrfull and rcvhdrqfull are "normal",
  375. * for some types of processes (mostly benchmarks)
  376. * that send huge numbers of messages, while not
  377. * processing them. So only complain about
  378. * these at debug level.
  379. */
  380. ipath_dbg("Disabling frequent queue full errors "
  381. "(%s)\n", msg);
  382. }
  383. /*
  384. * Re-enable the masked errors after around 3 minutes. in
  385. * ipath_get_faststats(). If we have a series of fast
  386. * repeating but different errors, the interval will keep
  387. * stretching out, but that's OK, as that's pretty
  388. * catastrophic.
  389. */
  390. dd->ipath_unmasktime = jiffies + HZ * 180;
  391. }
  392. ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, errs);
  393. if (ignore_this_time)
  394. errs &= ~ignore_this_time;
  395. if (errs & ~dd->ipath_lasterror) {
  396. errs &= ~dd->ipath_lasterror;
  397. /* never suppress duplicate hwerrors or ibstatuschange */
  398. dd->ipath_lasterror |= errs &
  399. ~(INFINIPATH_E_HARDWARE |
  400. INFINIPATH_E_IBSTATUSCHANGED);
  401. }
  402. if (!errs)
  403. return;
  404. if (!noprint)
  405. /*
  406. * the ones we mask off are handled specially below or above
  407. */
  408. ipath_decode_err(msg, sizeof msg,
  409. errs & ~(INFINIPATH_E_IBSTATUSCHANGED |
  410. INFINIPATH_E_RRCVEGRFULL |
  411. INFINIPATH_E_RRCVHDRFULL |
  412. INFINIPATH_E_HARDWARE));
  413. else
  414. /* so we don't need if (!noprint) at strlcat's below */
  415. *msg = 0;
  416. if (errs & E_SUM_PKTERRS) {
  417. ipath_stats.sps_pkterrs++;
  418. chkerrpkts = 1;
  419. }
  420. if (errs & E_SUM_ERRS)
  421. ipath_stats.sps_errs++;
  422. if (errs & (INFINIPATH_E_RICRC | INFINIPATH_E_RVCRC)) {
  423. ipath_stats.sps_crcerrs++;
  424. chkerrpkts = 1;
  425. }
  426. /*
  427. * We don't want to print these two as they happen, or we can make
  428. * the situation even worse, because it takes so long to print
  429. * messages to serial consoles. Kernel ports get printed from
  430. * fast_stats, no more than every 5 seconds, user ports get printed
  431. * on close
  432. */
  433. if (errs & INFINIPATH_E_RRCVHDRFULL) {
  434. int any;
  435. u32 hd, tl;
  436. ipath_stats.sps_hdrqfull++;
  437. for (any = i = 0; i < dd->ipath_cfgports; i++) {
  438. struct ipath_portdata *pd = dd->ipath_pd[i];
  439. if (i == 0) {
  440. hd = dd->ipath_port0head;
  441. tl = (u32) le64_to_cpu(
  442. *dd->ipath_hdrqtailptr);
  443. } else if (pd && pd->port_cnt &&
  444. pd->port_rcvhdrtail_kvaddr) {
  445. /*
  446. * don't report same point multiple times,
  447. * except kernel
  448. */
  449. tl = (u32) * pd->port_rcvhdrtail_kvaddr;
  450. if (tl == dd->ipath_lastrcvhdrqtails[i])
  451. continue;
  452. hd = ipath_read_ureg32(dd, ur_rcvhdrhead,
  453. i);
  454. } else
  455. continue;
  456. if (hd == (tl + 1) ||
  457. (!hd && tl == dd->ipath_hdrqlast)) {
  458. dd->ipath_lastrcvhdrqtails[i] = tl;
  459. pd->port_hdrqfull++;
  460. if (i == 0)
  461. chkerrpkts = 1;
  462. }
  463. }
  464. }
  465. if (errs & INFINIPATH_E_RRCVEGRFULL) {
  466. /*
  467. * since this is of less importance and not likely to
  468. * happen without also getting hdrfull, only count
  469. * occurrences; don't check each port (or even the kernel
  470. * vs user)
  471. */
  472. ipath_stats.sps_etidfull++;
  473. if (dd->ipath_port0head !=
  474. (u32) le64_to_cpu(*dd->ipath_hdrqtailptr))
  475. chkerrpkts = 1;
  476. }
  477. /*
  478. * do this before IBSTATUSCHANGED, in case both bits set in a single
  479. * interrupt; we want the STATUSCHANGE to "win", so we do our
  480. * internal copy of state machine correctly
  481. */
  482. if (errs & INFINIPATH_E_RIBLOSTLINK) {
  483. /*
  484. * force through block below
  485. */
  486. errs |= INFINIPATH_E_IBSTATUSCHANGED;
  487. ipath_stats.sps_iblink++;
  488. dd->ipath_flags |= IPATH_LINKDOWN;
  489. dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
  490. | IPATH_LINKARMED | IPATH_LINKACTIVE);
  491. *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
  492. if (!noprint) {
  493. u64 st = ipath_read_kreg64(
  494. dd, dd->ipath_kregs->kr_ibcstatus);
  495. ipath_dbg("Lost link, link now down (%s)\n",
  496. ipath_ibcstatus_str[st & 0xf]);
  497. }
  498. }
  499. if (errs & INFINIPATH_E_IBSTATUSCHANGED)
  500. handle_e_ibstatuschanged(dd, errs, noprint);
  501. if (errs & INFINIPATH_E_RESET) {
  502. if (!noprint)
  503. ipath_dev_err(dd, "Got reset, requires re-init "
  504. "(unload and reload driver)\n");
  505. dd->ipath_flags &= ~IPATH_INITTED; /* needs re-init */
  506. /* mark as having had error */
  507. *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
  508. *dd->ipath_statusp &= ~IPATH_STATUS_IB_CONF;
  509. }
  510. if (!noprint && *msg)
  511. ipath_dev_err(dd, "%s error\n", msg);
  512. if (dd->ipath_sma_state_wanted & dd->ipath_flags) {
  513. ipath_cdbg(VERBOSE, "sma wanted state %x, iflags now %x, "
  514. "waking\n", dd->ipath_sma_state_wanted,
  515. dd->ipath_flags);
  516. wake_up_interruptible(&ipath_sma_state_wait);
  517. }
  518. if (chkerrpkts)
  519. /* process possible error packets in hdrq */
  520. ipath_kreceive(dd);
  521. }
  522. /* this is separate to allow for better optimization of ipath_intr() */
  523. static void ipath_bad_intr(struct ipath_devdata *dd, u32 * unexpectp)
  524. {
  525. /*
  526. * sometimes happen during driver init and unload, don't want
  527. * to process any interrupts at that point
  528. */
  529. /* this is just a bandaid, not a fix, if something goes badly
  530. * wrong */
  531. if (++*unexpectp > 100) {
  532. if (++*unexpectp > 105) {
  533. /*
  534. * ok, we must be taking somebody else's interrupts,
  535. * due to a messed up mptable and/or PIRQ table, so
  536. * unregister the interrupt. We've seen this during
  537. * linuxbios development work, and it may happen in
  538. * the future again.
  539. */
  540. if (dd->pcidev && dd->pcidev->irq) {
  541. ipath_dev_err(dd, "Now %u unexpected "
  542. "interrupts, unregistering "
  543. "interrupt handler\n",
  544. *unexpectp);
  545. ipath_dbg("free_irq of irq %x\n",
  546. dd->pcidev->irq);
  547. free_irq(dd->pcidev->irq, dd);
  548. }
  549. }
  550. if (ipath_read_kreg32(dd, dd->ipath_kregs->kr_intmask)) {
  551. ipath_dev_err(dd, "%u unexpected interrupts, "
  552. "disabling interrupts completely\n",
  553. *unexpectp);
  554. /*
  555. * disable all interrupts, something is very wrong
  556. */
  557. ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
  558. 0ULL);
  559. }
  560. } else if (*unexpectp > 1)
  561. ipath_dbg("Interrupt when not ready, should not happen, "
  562. "ignoring\n");
  563. }
  564. static void ipath_bad_regread(struct ipath_devdata *dd)
  565. {
  566. static int allbits;
  567. /* separate routine, for better optimization of ipath_intr() */
  568. /*
  569. * We print the message and disable interrupts, in hope of
  570. * having a better chance of debugging the problem.
  571. */
  572. ipath_dev_err(dd,
  573. "Read of interrupt status failed (all bits set)\n");
  574. if (allbits++) {
  575. /* disable all interrupts, something is very wrong */
  576. ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
  577. if (allbits == 2) {
  578. ipath_dev_err(dd, "Still bad interrupt status, "
  579. "unregistering interrupt\n");
  580. free_irq(dd->pcidev->irq, dd);
  581. } else if (allbits > 2) {
  582. if ((allbits % 10000) == 0)
  583. printk(".");
  584. } else
  585. ipath_dev_err(dd, "Disabling interrupts, "
  586. "multiple errors\n");
  587. }
  588. }
  589. static void handle_port_pioavail(struct ipath_devdata *dd)
  590. {
  591. u32 i;
  592. /*
  593. * start from port 1, since for now port 0 is never using
  594. * wait_event for PIO
  595. */
  596. for (i = 1; dd->ipath_portpiowait && i < dd->ipath_cfgports; i++) {
  597. struct ipath_portdata *pd = dd->ipath_pd[i];
  598. if (pd && pd->port_cnt &&
  599. dd->ipath_portpiowait & (1U << i)) {
  600. clear_bit(i, &dd->ipath_portpiowait);
  601. if (test_bit(IPATH_PORT_WAITING_PIO,
  602. &pd->port_flag)) {
  603. clear_bit(IPATH_PORT_WAITING_PIO,
  604. &pd->port_flag);
  605. wake_up_interruptible(&pd->port_wait);
  606. }
  607. }
  608. }
  609. }
  610. static void handle_layer_pioavail(struct ipath_devdata *dd)
  611. {
  612. int ret;
  613. ret = __ipath_layer_intr(dd, IPATH_LAYER_INT_SEND_CONTINUE);
  614. if (ret > 0)
  615. goto clear;
  616. ret = __ipath_verbs_piobufavail(dd);
  617. if (ret > 0)
  618. goto clear;
  619. return;
  620. clear:
  621. set_bit(IPATH_S_PIOINTBUFAVAIL, &dd->ipath_sendctrl);
  622. ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
  623. dd->ipath_sendctrl);
  624. }
  625. static void handle_rcv(struct ipath_devdata *dd, u32 istat)
  626. {
  627. u64 portr;
  628. int i;
  629. int rcvdint = 0;
  630. portr = ((istat >> INFINIPATH_I_RCVAVAIL_SHIFT) &
  631. infinipath_i_rcvavail_mask)
  632. | ((istat >> INFINIPATH_I_RCVURG_SHIFT) &
  633. infinipath_i_rcvurg_mask);
  634. for (i = 0; i < dd->ipath_cfgports; i++) {
  635. struct ipath_portdata *pd = dd->ipath_pd[i];
  636. if (portr & (1 << i) && pd &&
  637. pd->port_cnt) {
  638. if (i == 0)
  639. ipath_kreceive(dd);
  640. else if (test_bit(IPATH_PORT_WAITING_RCV,
  641. &pd->port_flag)) {
  642. int rcbit;
  643. clear_bit(IPATH_PORT_WAITING_RCV,
  644. &pd->port_flag);
  645. rcbit = i + INFINIPATH_R_INTRAVAIL_SHIFT;
  646. clear_bit(1UL << rcbit, &dd->ipath_rcvctrl);
  647. wake_up_interruptible(&pd->port_wait);
  648. rcvdint = 1;
  649. }
  650. }
  651. }
  652. if (rcvdint) {
  653. /* only want to take one interrupt, so turn off the rcv
  654. * interrupt for all the ports that we did the wakeup on
  655. * (but never for kernel port)
  656. */
  657. ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
  658. dd->ipath_rcvctrl);
  659. }
  660. }
  661. irqreturn_t ipath_intr(int irq, void *data, struct pt_regs *regs)
  662. {
  663. struct ipath_devdata *dd = data;
  664. u32 istat = ipath_read_kreg32(dd, dd->ipath_kregs->kr_intstatus);
  665. ipath_err_t estat = 0;
  666. static unsigned unexpected = 0;
  667. irqreturn_t ret;
  668. if (unlikely(!istat)) {
  669. ipath_stats.sps_nullintr++;
  670. ret = IRQ_NONE; /* not our interrupt, or already handled */
  671. goto bail;
  672. }
  673. if (unlikely(istat == -1)) {
  674. ipath_bad_regread(dd);
  675. /* don't know if it was our interrupt or not */
  676. ret = IRQ_NONE;
  677. goto bail;
  678. }
  679. ipath_stats.sps_ints++;
  680. /*
  681. * this needs to be flags&initted, not statusp, so we keep
  682. * taking interrupts even after link goes down, etc.
  683. * Also, we *must* clear the interrupt at some point, or we won't
  684. * take it again, which can be real bad for errors, etc...
  685. */
  686. if (!(dd->ipath_flags & IPATH_INITTED)) {
  687. ipath_bad_intr(dd, &unexpected);
  688. ret = IRQ_NONE;
  689. goto bail;
  690. }
  691. if (unexpected)
  692. unexpected = 0;
  693. ipath_cdbg(VERBOSE, "intr stat=0x%x\n", istat);
  694. if (istat & ~infinipath_i_bitsextant)
  695. ipath_dev_err(dd,
  696. "interrupt with unknown interrupts %x set\n",
  697. istat & (u32) ~ infinipath_i_bitsextant);
  698. if (istat & INFINIPATH_I_ERROR) {
  699. ipath_stats.sps_errints++;
  700. estat = ipath_read_kreg64(dd,
  701. dd->ipath_kregs->kr_errorstatus);
  702. if (!estat)
  703. dev_info(&dd->pcidev->dev, "error interrupt (%x), "
  704. "but no error bits set!\n", istat);
  705. else if (estat == -1LL)
  706. /*
  707. * should we try clearing all, or hope next read
  708. * works?
  709. */
  710. ipath_dev_err(dd, "Read of error status failed "
  711. "(all bits set); ignoring\n");
  712. else
  713. handle_errors(dd, estat);
  714. }
  715. if (istat & INFINIPATH_I_GPIO) {
  716. if (unlikely(!(dd->ipath_flags & IPATH_GPIO_INTR))) {
  717. u32 gpiostatus;
  718. gpiostatus = ipath_read_kreg32(
  719. dd, dd->ipath_kregs->kr_gpio_status);
  720. ipath_dbg("Unexpected GPIO interrupt bits %x\n",
  721. gpiostatus);
  722. ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear,
  723. gpiostatus);
  724. }
  725. else {
  726. /* Clear GPIO status bit 2 */
  727. ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear,
  728. (u64) (1 << 2));
  729. /*
  730. * Packets are available in the port 0 rcv queue.
  731. * Eventually this needs to be generalized to check
  732. * IPATH_GPIO_INTR, and the specific GPIO bit, if
  733. * GPIO interrupts are used for anything else.
  734. */
  735. ipath_kreceive(dd);
  736. }
  737. }
  738. /*
  739. * clear the ones we will deal with on this round
  740. * We clear it early, mostly for receive interrupts, so we
  741. * know the chip will have seen this by the time we process
  742. * the queue, and will re-interrupt if necessary. The processor
  743. * itself won't take the interrupt again until we return.
  744. */
  745. ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat);
  746. if (istat & INFINIPATH_I_SPIOBUFAVAIL) {
  747. clear_bit(IPATH_S_PIOINTBUFAVAIL, &dd->ipath_sendctrl);
  748. ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
  749. dd->ipath_sendctrl);
  750. if (dd->ipath_portpiowait)
  751. handle_port_pioavail(dd);
  752. handle_layer_pioavail(dd);
  753. }
  754. /*
  755. * we check for both transition from empty to non-empty, and urgent
  756. * packets (those with the interrupt bit set in the header)
  757. */
  758. if (istat & ((infinipath_i_rcvavail_mask <<
  759. INFINIPATH_I_RCVAVAIL_SHIFT)
  760. | (infinipath_i_rcvurg_mask <<
  761. INFINIPATH_I_RCVURG_SHIFT)))
  762. handle_rcv(dd, istat);
  763. ret = IRQ_HANDLED;
  764. bail:
  765. return ret;
  766. }