tlclk.c 23 KB

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  1. /*
  2. * Telecom Clock driver for Intel NetStructure(tm) MPCBL0010
  3. *
  4. * Copyright (C) 2005 Kontron Canada
  5. *
  6. * All rights reserved.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or (at
  11. * your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  16. * NON INFRINGEMENT. See the GNU General Public License for more
  17. * details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. *
  23. * Send feedback to <sebastien.bouchard@ca.kontron.com> and the current
  24. * Maintainer <mark.gross@intel.com>
  25. *
  26. * Description : This is the TELECOM CLOCK module driver for the ATCA
  27. * MPCBL0010 ATCA computer.
  28. */
  29. #include <linux/config.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/sched.h>
  33. #include <linux/kernel.h> /* printk() */
  34. #include <linux/fs.h> /* everything... */
  35. #include <linux/errno.h> /* error codes */
  36. #include <linux/slab.h>
  37. #include <linux/ioport.h>
  38. #include <linux/interrupt.h>
  39. #include <linux/spinlock.h>
  40. #include <linux/timer.h>
  41. #include <linux/sysfs.h>
  42. #include <linux/device.h>
  43. #include <linux/miscdevice.h>
  44. #include <linux/platform_device.h>
  45. #include <asm/io.h> /* inb/outb */
  46. #include <asm/uaccess.h>
  47. MODULE_AUTHOR("Sebastien Bouchard <sebastien.bouchard@ca.kontron.com>");
  48. MODULE_LICENSE("GPL");
  49. /*Hardware Reset of the PLL */
  50. #define RESET_ON 0x00
  51. #define RESET_OFF 0x01
  52. /* MODE SELECT */
  53. #define NORMAL_MODE 0x00
  54. #define HOLDOVER_MODE 0x10
  55. #define FREERUN_MODE 0x20
  56. /* FILTER SELECT */
  57. #define FILTER_6HZ 0x04
  58. #define FILTER_12HZ 0x00
  59. /* SELECT REFERENCE FREQUENCY */
  60. #define REF_CLK1_8kHz 0x00
  61. #define REF_CLK2_19_44MHz 0x02
  62. /* Select primary or secondary redundant clock */
  63. #define PRIMARY_CLOCK 0x00
  64. #define SECONDARY_CLOCK 0x01
  65. /* CLOCK TRANSMISSION DEFINE */
  66. #define CLK_8kHz 0xff
  67. #define CLK_16_384MHz 0xfb
  68. #define CLK_1_544MHz 0x00
  69. #define CLK_2_048MHz 0x01
  70. #define CLK_4_096MHz 0x02
  71. #define CLK_6_312MHz 0x03
  72. #define CLK_8_192MHz 0x04
  73. #define CLK_19_440MHz 0x06
  74. #define CLK_8_592MHz 0x08
  75. #define CLK_11_184MHz 0x09
  76. #define CLK_34_368MHz 0x0b
  77. #define CLK_44_736MHz 0x0a
  78. /* RECEIVED REFERENCE */
  79. #define AMC_B1 0
  80. #define AMC_B2 1
  81. /* HARDWARE SWITCHING DEFINE */
  82. #define HW_ENABLE 0x80
  83. #define HW_DISABLE 0x00
  84. /* HARDWARE SWITCHING MODE DEFINE */
  85. #define PLL_HOLDOVER 0x40
  86. #define LOST_CLOCK 0x00
  87. /* ALARMS DEFINE */
  88. #define UNLOCK_MASK 0x10
  89. #define HOLDOVER_MASK 0x20
  90. #define SEC_LOST_MASK 0x40
  91. #define PRI_LOST_MASK 0x80
  92. /* INTERRUPT CAUSE DEFINE */
  93. #define PRI_LOS_01_MASK 0x01
  94. #define PRI_LOS_10_MASK 0x02
  95. #define SEC_LOS_01_MASK 0x04
  96. #define SEC_LOS_10_MASK 0x08
  97. #define HOLDOVER_01_MASK 0x10
  98. #define HOLDOVER_10_MASK 0x20
  99. #define UNLOCK_01_MASK 0x40
  100. #define UNLOCK_10_MASK 0x80
  101. struct tlclk_alarms {
  102. __u32 lost_clocks;
  103. __u32 lost_primary_clock;
  104. __u32 lost_secondary_clock;
  105. __u32 primary_clock_back;
  106. __u32 secondary_clock_back;
  107. __u32 switchover_primary;
  108. __u32 switchover_secondary;
  109. __u32 pll_holdover;
  110. __u32 pll_end_holdover;
  111. __u32 pll_lost_sync;
  112. __u32 pll_sync;
  113. };
  114. /* Telecom clock I/O register definition */
  115. #define TLCLK_BASE 0xa08
  116. #define TLCLK_REG0 TLCLK_BASE
  117. #define TLCLK_REG1 (TLCLK_BASE+1)
  118. #define TLCLK_REG2 (TLCLK_BASE+2)
  119. #define TLCLK_REG3 (TLCLK_BASE+3)
  120. #define TLCLK_REG4 (TLCLK_BASE+4)
  121. #define TLCLK_REG5 (TLCLK_BASE+5)
  122. #define TLCLK_REG6 (TLCLK_BASE+6)
  123. #define TLCLK_REG7 (TLCLK_BASE+7)
  124. #define SET_PORT_BITS(port, mask, val) outb(((inb(port) & mask) | val), port)
  125. /* 0 = Dynamic allocation of the major device number */
  126. #define TLCLK_MAJOR 0
  127. /* sysfs interface definition:
  128. Upon loading the driver will create a sysfs directory under
  129. /sys/devices/platform/telco_clock.
  130. This directory exports the following interfaces. There operation is
  131. documented in the MCPBL0010 TPS under the Telecom Clock API section, 11.4.
  132. alarms :
  133. current_ref :
  134. received_ref_clk3a :
  135. received_ref_clk3b :
  136. enable_clk3a_output :
  137. enable_clk3b_output :
  138. enable_clka0_output :
  139. enable_clka1_output :
  140. enable_clkb0_output :
  141. enable_clkb1_output :
  142. filter_select :
  143. hardware_switching :
  144. hardware_switching_mode :
  145. telclock_version :
  146. mode_select :
  147. refalign :
  148. reset :
  149. select_amcb1_transmit_clock :
  150. select_amcb2_transmit_clock :
  151. select_redundant_clock :
  152. select_ref_frequency :
  153. All sysfs interfaces are integers in hex format, i.e echo 99 > refalign
  154. has the same effect as echo 0x99 > refalign.
  155. */
  156. static unsigned int telclk_interrupt;
  157. static int int_events; /* Event that generate a interrupt */
  158. static int got_event; /* if events processing have been done */
  159. static void switchover_timeout(unsigned long data);
  160. static struct timer_list switchover_timer =
  161. TIMER_INITIALIZER(switchover_timeout , 0, 0);
  162. static struct tlclk_alarms *alarm_events;
  163. static DEFINE_SPINLOCK(event_lock);
  164. static int tlclk_major = TLCLK_MAJOR;
  165. static irqreturn_t tlclk_interrupt(int irq, void *dev_id, struct pt_regs *regs);
  166. static DECLARE_WAIT_QUEUE_HEAD(wq);
  167. static int tlclk_open(struct inode *inode, struct file *filp)
  168. {
  169. int result;
  170. /* Make sure there is no interrupt pending while
  171. * initialising interrupt handler */
  172. inb(TLCLK_REG6);
  173. /* This device is wired through the FPGA IO space of the ATCA blade
  174. * we can't share this IRQ */
  175. result = request_irq(telclk_interrupt, &tlclk_interrupt,
  176. SA_INTERRUPT, "telco_clock", tlclk_interrupt);
  177. if (result == -EBUSY) {
  178. printk(KERN_ERR "tlclk: Interrupt can't be reserved.\n");
  179. return -EBUSY;
  180. }
  181. inb(TLCLK_REG6); /* Clear interrupt events */
  182. return 0;
  183. }
  184. static int tlclk_release(struct inode *inode, struct file *filp)
  185. {
  186. free_irq(telclk_interrupt, tlclk_interrupt);
  187. return 0;
  188. }
  189. static ssize_t tlclk_read(struct file *filp, char __user *buf, size_t count,
  190. loff_t *f_pos)
  191. {
  192. if (count < sizeof(struct tlclk_alarms))
  193. return -EIO;
  194. wait_event_interruptible(wq, got_event);
  195. if (copy_to_user(buf, alarm_events, sizeof(struct tlclk_alarms)))
  196. return -EFAULT;
  197. memset(alarm_events, 0, sizeof(struct tlclk_alarms));
  198. got_event = 0;
  199. return sizeof(struct tlclk_alarms);
  200. }
  201. static ssize_t tlclk_write(struct file *filp, const char __user *buf, size_t count,
  202. loff_t *f_pos)
  203. {
  204. return 0;
  205. }
  206. static struct file_operations tlclk_fops = {
  207. .read = tlclk_read,
  208. .write = tlclk_write,
  209. .open = tlclk_open,
  210. .release = tlclk_release,
  211. };
  212. static struct miscdevice tlclk_miscdev = {
  213. .minor = MISC_DYNAMIC_MINOR,
  214. .name = "telco_clock",
  215. .fops = &tlclk_fops,
  216. };
  217. static ssize_t show_current_ref(struct device *d,
  218. struct device_attribute *attr, char *buf)
  219. {
  220. unsigned long ret_val;
  221. unsigned long flags;
  222. spin_lock_irqsave(&event_lock, flags);
  223. ret_val = ((inb(TLCLK_REG1) & 0x08) >> 3);
  224. spin_unlock_irqrestore(&event_lock, flags);
  225. return sprintf(buf, "0x%lX\n", ret_val);
  226. }
  227. static DEVICE_ATTR(current_ref, S_IRUGO, show_current_ref, NULL);
  228. static ssize_t show_telclock_version(struct device *d,
  229. struct device_attribute *attr, char *buf)
  230. {
  231. unsigned long ret_val;
  232. unsigned long flags;
  233. spin_lock_irqsave(&event_lock, flags);
  234. ret_val = inb(TLCLK_REG5);
  235. spin_unlock_irqrestore(&event_lock, flags);
  236. return sprintf(buf, "0x%lX\n", ret_val);
  237. }
  238. static DEVICE_ATTR(telclock_version, S_IRUGO,
  239. show_telclock_version, NULL);
  240. static ssize_t show_alarms(struct device *d,
  241. struct device_attribute *attr, char *buf)
  242. {
  243. unsigned long ret_val;
  244. unsigned long flags;
  245. spin_lock_irqsave(&event_lock, flags);
  246. ret_val = (inb(TLCLK_REG2) & 0xf0);
  247. spin_unlock_irqrestore(&event_lock, flags);
  248. return sprintf(buf, "0x%lX\n", ret_val);
  249. }
  250. static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
  251. static ssize_t store_received_ref_clk3a(struct device *d,
  252. struct device_attribute *attr, const char *buf, size_t count)
  253. {
  254. unsigned long tmp;
  255. unsigned char val;
  256. unsigned long flags;
  257. sscanf(buf, "%lX", &tmp);
  258. dev_dbg(d, ": tmp = 0x%lX\n", tmp);
  259. val = (unsigned char)tmp;
  260. spin_lock_irqsave(&event_lock, flags);
  261. SET_PORT_BITS(TLCLK_REG1, 0xef, val);
  262. spin_unlock_irqrestore(&event_lock, flags);
  263. return strnlen(buf, count);
  264. }
  265. static DEVICE_ATTR(received_ref_clk3a, (S_IWUSR|S_IWGRP), NULL,
  266. store_received_ref_clk3a);
  267. static ssize_t store_received_ref_clk3b(struct device *d,
  268. struct device_attribute *attr, const char *buf, size_t count)
  269. {
  270. unsigned long tmp;
  271. unsigned char val;
  272. unsigned long flags;
  273. sscanf(buf, "%lX", &tmp);
  274. dev_dbg(d, ": tmp = 0x%lX\n", tmp);
  275. val = (unsigned char)tmp;
  276. spin_lock_irqsave(&event_lock, flags);
  277. SET_PORT_BITS(TLCLK_REG1, 0xef, val << 1);
  278. spin_unlock_irqrestore(&event_lock, flags);
  279. return strnlen(buf, count);
  280. }
  281. static DEVICE_ATTR(received_ref_clk3b, (S_IWUSR|S_IWGRP), NULL,
  282. store_received_ref_clk3b);
  283. static ssize_t store_enable_clk3b_output(struct device *d,
  284. struct device_attribute *attr, const char *buf, size_t count)
  285. {
  286. unsigned long tmp;
  287. unsigned char val;
  288. unsigned long flags;
  289. sscanf(buf, "%lX", &tmp);
  290. dev_dbg(d, ": tmp = 0x%lX\n", tmp);
  291. val = (unsigned char)tmp;
  292. spin_lock_irqsave(&event_lock, flags);
  293. SET_PORT_BITS(TLCLK_REG3, 0x7f, val << 7);
  294. spin_unlock_irqrestore(&event_lock, flags);
  295. return strnlen(buf, count);
  296. }
  297. static DEVICE_ATTR(enable_clk3b_output, (S_IWUSR|S_IWGRP), NULL,
  298. store_enable_clk3b_output);
  299. static ssize_t store_enable_clk3a_output(struct device *d,
  300. struct device_attribute *attr, const char *buf, size_t count)
  301. {
  302. unsigned long flags;
  303. unsigned long tmp;
  304. unsigned char val;
  305. sscanf(buf, "%lX", &tmp);
  306. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  307. val = (unsigned char)tmp;
  308. spin_lock_irqsave(&event_lock, flags);
  309. SET_PORT_BITS(TLCLK_REG3, 0xbf, val << 6);
  310. spin_unlock_irqrestore(&event_lock, flags);
  311. return strnlen(buf, count);
  312. }
  313. static DEVICE_ATTR(enable_clk3a_output, (S_IWUSR|S_IWGRP), NULL,
  314. store_enable_clk3a_output);
  315. static ssize_t store_enable_clkb1_output(struct device *d,
  316. struct device_attribute *attr, const char *buf, size_t count)
  317. {
  318. unsigned long flags;
  319. unsigned long tmp;
  320. unsigned char val;
  321. sscanf(buf, "%lX", &tmp);
  322. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  323. val = (unsigned char)tmp;
  324. spin_lock_irqsave(&event_lock, flags);
  325. SET_PORT_BITS(TLCLK_REG2, 0xf7, val << 3);
  326. spin_unlock_irqrestore(&event_lock, flags);
  327. return strnlen(buf, count);
  328. }
  329. static DEVICE_ATTR(enable_clkb1_output, (S_IWUSR|S_IWGRP), NULL,
  330. store_enable_clkb1_output);
  331. static ssize_t store_enable_clka1_output(struct device *d,
  332. struct device_attribute *attr, const char *buf, size_t count)
  333. {
  334. unsigned long flags;
  335. unsigned long tmp;
  336. unsigned char val;
  337. sscanf(buf, "%lX", &tmp);
  338. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  339. val = (unsigned char)tmp;
  340. spin_lock_irqsave(&event_lock, flags);
  341. SET_PORT_BITS(TLCLK_REG2, 0xfb, val << 2);
  342. spin_unlock_irqrestore(&event_lock, flags);
  343. return strnlen(buf, count);
  344. }
  345. static DEVICE_ATTR(enable_clka1_output, (S_IWUSR|S_IWGRP), NULL,
  346. store_enable_clka1_output);
  347. static ssize_t store_enable_clkb0_output(struct device *d,
  348. struct device_attribute *attr, const char *buf, size_t count)
  349. {
  350. unsigned long flags;
  351. unsigned long tmp;
  352. unsigned char val;
  353. sscanf(buf, "%lX", &tmp);
  354. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  355. val = (unsigned char)tmp;
  356. spin_lock_irqsave(&event_lock, flags);
  357. SET_PORT_BITS(TLCLK_REG2, 0xfd, val << 1);
  358. spin_unlock_irqrestore(&event_lock, flags);
  359. return strnlen(buf, count);
  360. }
  361. static DEVICE_ATTR(enable_clkb0_output, (S_IWUSR|S_IWGRP), NULL,
  362. store_enable_clkb0_output);
  363. static ssize_t store_enable_clka0_output(struct device *d,
  364. struct device_attribute *attr, const char *buf, size_t count)
  365. {
  366. unsigned long flags;
  367. unsigned long tmp;
  368. unsigned char val;
  369. sscanf(buf, "%lX", &tmp);
  370. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  371. val = (unsigned char)tmp;
  372. spin_lock_irqsave(&event_lock, flags);
  373. SET_PORT_BITS(TLCLK_REG2, 0xfe, val);
  374. spin_unlock_irqrestore(&event_lock, flags);
  375. return strnlen(buf, count);
  376. }
  377. static DEVICE_ATTR(enable_clka0_output, (S_IWUSR|S_IWGRP), NULL,
  378. store_enable_clka0_output);
  379. static ssize_t store_select_amcb2_transmit_clock(struct device *d,
  380. struct device_attribute *attr, const char *buf, size_t count)
  381. {
  382. unsigned long flags;
  383. unsigned long tmp;
  384. unsigned char val;
  385. sscanf(buf, "%lX", &tmp);
  386. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  387. val = (unsigned char)tmp;
  388. spin_lock_irqsave(&event_lock, flags);
  389. if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) {
  390. SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x28);
  391. SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val);
  392. } else if (val >= CLK_8_592MHz) {
  393. SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x38);
  394. switch (val) {
  395. case CLK_8_592MHz:
  396. SET_PORT_BITS(TLCLK_REG0, 0xfc, 2);
  397. break;
  398. case CLK_11_184MHz:
  399. SET_PORT_BITS(TLCLK_REG0, 0xfc, 0);
  400. break;
  401. case CLK_34_368MHz:
  402. SET_PORT_BITS(TLCLK_REG0, 0xfc, 3);
  403. break;
  404. case CLK_44_736MHz:
  405. SET_PORT_BITS(TLCLK_REG0, 0xfc, 1);
  406. break;
  407. }
  408. } else
  409. SET_PORT_BITS(TLCLK_REG3, 0xc7, val << 3);
  410. spin_unlock_irqrestore(&event_lock, flags);
  411. return strnlen(buf, count);
  412. }
  413. static DEVICE_ATTR(select_amcb2_transmit_clock, (S_IWUSR|S_IWGRP), NULL,
  414. store_select_amcb2_transmit_clock);
  415. static ssize_t store_select_amcb1_transmit_clock(struct device *d,
  416. struct device_attribute *attr, const char *buf, size_t count)
  417. {
  418. unsigned long tmp;
  419. unsigned char val;
  420. unsigned long flags;
  421. sscanf(buf, "%lX", &tmp);
  422. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  423. val = (unsigned char)tmp;
  424. spin_lock_irqsave(&event_lock, flags);
  425. if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) {
  426. SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x5);
  427. SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val);
  428. } else if (val >= CLK_8_592MHz) {
  429. SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x7);
  430. switch (val) {
  431. case CLK_8_592MHz:
  432. SET_PORT_BITS(TLCLK_REG0, 0xfc, 1);
  433. break;
  434. case CLK_11_184MHz:
  435. SET_PORT_BITS(TLCLK_REG0, 0xfc, 0);
  436. break;
  437. case CLK_34_368MHz:
  438. SET_PORT_BITS(TLCLK_REG0, 0xfc, 3);
  439. break;
  440. case CLK_44_736MHz:
  441. SET_PORT_BITS(TLCLK_REG0, 0xfc, 2);
  442. break;
  443. }
  444. } else
  445. SET_PORT_BITS(TLCLK_REG3, 0xf8, val);
  446. spin_unlock_irqrestore(&event_lock, flags);
  447. return strnlen(buf, count);
  448. }
  449. static DEVICE_ATTR(select_amcb1_transmit_clock, (S_IWUSR|S_IWGRP), NULL,
  450. store_select_amcb1_transmit_clock);
  451. static ssize_t store_select_redundant_clock(struct device *d,
  452. struct device_attribute *attr, const char *buf, size_t count)
  453. {
  454. unsigned long tmp;
  455. unsigned char val;
  456. unsigned long flags;
  457. sscanf(buf, "%lX", &tmp);
  458. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  459. val = (unsigned char)tmp;
  460. spin_lock_irqsave(&event_lock, flags);
  461. SET_PORT_BITS(TLCLK_REG1, 0xfe, val);
  462. spin_unlock_irqrestore(&event_lock, flags);
  463. return strnlen(buf, count);
  464. }
  465. static DEVICE_ATTR(select_redundant_clock, (S_IWUSR|S_IWGRP), NULL,
  466. store_select_redundant_clock);
  467. static ssize_t store_select_ref_frequency(struct device *d,
  468. struct device_attribute *attr, const char *buf, size_t count)
  469. {
  470. unsigned long tmp;
  471. unsigned char val;
  472. unsigned long flags;
  473. sscanf(buf, "%lX", &tmp);
  474. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  475. val = (unsigned char)tmp;
  476. spin_lock_irqsave(&event_lock, flags);
  477. SET_PORT_BITS(TLCLK_REG1, 0xfd, val);
  478. spin_unlock_irqrestore(&event_lock, flags);
  479. return strnlen(buf, count);
  480. }
  481. static DEVICE_ATTR(select_ref_frequency, (S_IWUSR|S_IWGRP), NULL,
  482. store_select_ref_frequency);
  483. static ssize_t store_filter_select(struct device *d,
  484. struct device_attribute *attr, const char *buf, size_t count)
  485. {
  486. unsigned long tmp;
  487. unsigned char val;
  488. unsigned long flags;
  489. sscanf(buf, "%lX", &tmp);
  490. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  491. val = (unsigned char)tmp;
  492. spin_lock_irqsave(&event_lock, flags);
  493. SET_PORT_BITS(TLCLK_REG0, 0xfb, val);
  494. spin_unlock_irqrestore(&event_lock, flags);
  495. return strnlen(buf, count);
  496. }
  497. static DEVICE_ATTR(filter_select, (S_IWUSR|S_IWGRP), NULL, store_filter_select);
  498. static ssize_t store_hardware_switching_mode(struct device *d,
  499. struct device_attribute *attr, const char *buf, size_t count)
  500. {
  501. unsigned long tmp;
  502. unsigned char val;
  503. unsigned long flags;
  504. sscanf(buf, "%lX", &tmp);
  505. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  506. val = (unsigned char)tmp;
  507. spin_lock_irqsave(&event_lock, flags);
  508. SET_PORT_BITS(TLCLK_REG0, 0xbf, val);
  509. spin_unlock_irqrestore(&event_lock, flags);
  510. return strnlen(buf, count);
  511. }
  512. static DEVICE_ATTR(hardware_switching_mode, (S_IWUSR|S_IWGRP), NULL,
  513. store_hardware_switching_mode);
  514. static ssize_t store_hardware_switching(struct device *d,
  515. struct device_attribute *attr, const char *buf, size_t count)
  516. {
  517. unsigned long tmp;
  518. unsigned char val;
  519. unsigned long flags;
  520. sscanf(buf, "%lX", &tmp);
  521. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  522. val = (unsigned char)tmp;
  523. spin_lock_irqsave(&event_lock, flags);
  524. SET_PORT_BITS(TLCLK_REG0, 0x7f, val);
  525. spin_unlock_irqrestore(&event_lock, flags);
  526. return strnlen(buf, count);
  527. }
  528. static DEVICE_ATTR(hardware_switching, (S_IWUSR|S_IWGRP), NULL,
  529. store_hardware_switching);
  530. static ssize_t store_refalign (struct device *d,
  531. struct device_attribute *attr, const char *buf, size_t count)
  532. {
  533. unsigned long tmp;
  534. unsigned long flags;
  535. sscanf(buf, "%lX", &tmp);
  536. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  537. spin_lock_irqsave(&event_lock, flags);
  538. SET_PORT_BITS(TLCLK_REG0, 0xf7, 0);
  539. SET_PORT_BITS(TLCLK_REG0, 0xf7, 0x08);
  540. SET_PORT_BITS(TLCLK_REG0, 0xf7, 0);
  541. spin_unlock_irqrestore(&event_lock, flags);
  542. return strnlen(buf, count);
  543. }
  544. static DEVICE_ATTR(refalign, (S_IWUSR|S_IWGRP), NULL, store_refalign);
  545. static ssize_t store_mode_select (struct device *d,
  546. struct device_attribute *attr, const char *buf, size_t count)
  547. {
  548. unsigned long tmp;
  549. unsigned char val;
  550. unsigned long flags;
  551. sscanf(buf, "%lX", &tmp);
  552. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  553. val = (unsigned char)tmp;
  554. spin_lock_irqsave(&event_lock, flags);
  555. SET_PORT_BITS(TLCLK_REG0, 0xcf, val);
  556. spin_unlock_irqrestore(&event_lock, flags);
  557. return strnlen(buf, count);
  558. }
  559. static DEVICE_ATTR(mode_select, (S_IWUSR|S_IWGRP), NULL, store_mode_select);
  560. static ssize_t store_reset (struct device *d,
  561. struct device_attribute *attr, const char *buf, size_t count)
  562. {
  563. unsigned long tmp;
  564. unsigned char val;
  565. unsigned long flags;
  566. sscanf(buf, "%lX", &tmp);
  567. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  568. val = (unsigned char)tmp;
  569. spin_lock_irqsave(&event_lock, flags);
  570. SET_PORT_BITS(TLCLK_REG4, 0xfd, val);
  571. spin_unlock_irqrestore(&event_lock, flags);
  572. return strnlen(buf, count);
  573. }
  574. static DEVICE_ATTR(reset, (S_IWUSR|S_IWGRP), NULL, store_reset);
  575. static struct attribute *tlclk_sysfs_entries[] = {
  576. &dev_attr_current_ref.attr,
  577. &dev_attr_telclock_version.attr,
  578. &dev_attr_alarms.attr,
  579. &dev_attr_received_ref_clk3a.attr,
  580. &dev_attr_received_ref_clk3b.attr,
  581. &dev_attr_enable_clk3a_output.attr,
  582. &dev_attr_enable_clk3b_output.attr,
  583. &dev_attr_enable_clkb1_output.attr,
  584. &dev_attr_enable_clka1_output.attr,
  585. &dev_attr_enable_clkb0_output.attr,
  586. &dev_attr_enable_clka0_output.attr,
  587. &dev_attr_select_amcb1_transmit_clock.attr,
  588. &dev_attr_select_amcb2_transmit_clock.attr,
  589. &dev_attr_select_redundant_clock.attr,
  590. &dev_attr_select_ref_frequency.attr,
  591. &dev_attr_filter_select.attr,
  592. &dev_attr_hardware_switching_mode.attr,
  593. &dev_attr_hardware_switching.attr,
  594. &dev_attr_refalign.attr,
  595. &dev_attr_mode_select.attr,
  596. &dev_attr_reset.attr,
  597. NULL
  598. };
  599. static struct attribute_group tlclk_attribute_group = {
  600. .name = NULL, /* put in device directory */
  601. .attrs = tlclk_sysfs_entries,
  602. };
  603. static struct platform_device *tlclk_device;
  604. static int __init tlclk_init(void)
  605. {
  606. int ret;
  607. ret = register_chrdev(tlclk_major, "telco_clock", &tlclk_fops);
  608. if (ret < 0) {
  609. printk(KERN_ERR "tlclk: can't get major %d.\n", tlclk_major);
  610. return ret;
  611. }
  612. tlclk_major = ret;
  613. alarm_events = kzalloc( sizeof(struct tlclk_alarms), GFP_KERNEL);
  614. if (!alarm_events)
  615. goto out1;
  616. /* Read telecom clock IRQ number (Set by BIOS) */
  617. if (!request_region(TLCLK_BASE, 8, "telco_clock")) {
  618. printk(KERN_ERR "tlclk: request_region 0x%X failed.\n",
  619. TLCLK_BASE);
  620. ret = -EBUSY;
  621. goto out2;
  622. }
  623. telclk_interrupt = (inb(TLCLK_REG7) & 0x0f);
  624. if (0x0F == telclk_interrupt ) { /* not MCPBL0010 ? */
  625. printk(KERN_ERR "telclk_interrup = 0x%x non-mcpbl0010 hw.\n",
  626. telclk_interrupt);
  627. ret = -ENXIO;
  628. goto out3;
  629. }
  630. init_timer(&switchover_timer);
  631. ret = misc_register(&tlclk_miscdev);
  632. if (ret < 0) {
  633. printk(KERN_ERR "tlclk: misc_register returns %d.\n", ret);
  634. ret = -EBUSY;
  635. goto out3;
  636. }
  637. tlclk_device = platform_device_register_simple("telco_clock",
  638. -1, NULL, 0);
  639. if (!tlclk_device) {
  640. printk(KERN_ERR "tlclk: platform_device_register failed.\n");
  641. ret = -EBUSY;
  642. goto out4;
  643. }
  644. ret = sysfs_create_group(&tlclk_device->dev.kobj,
  645. &tlclk_attribute_group);
  646. if (ret) {
  647. printk(KERN_ERR "tlclk: failed to create sysfs device attributes.\n");
  648. sysfs_remove_group(&tlclk_device->dev.kobj,
  649. &tlclk_attribute_group);
  650. goto out5;
  651. }
  652. return 0;
  653. out5:
  654. platform_device_unregister(tlclk_device);
  655. out4:
  656. misc_deregister(&tlclk_miscdev);
  657. out3:
  658. release_region(TLCLK_BASE, 8);
  659. out2:
  660. kfree(alarm_events);
  661. out1:
  662. unregister_chrdev(tlclk_major, "telco_clock");
  663. return ret;
  664. }
  665. static void __exit tlclk_cleanup(void)
  666. {
  667. sysfs_remove_group(&tlclk_device->dev.kobj, &tlclk_attribute_group);
  668. platform_device_unregister(tlclk_device);
  669. misc_deregister(&tlclk_miscdev);
  670. unregister_chrdev(tlclk_major, "telco_clock");
  671. release_region(TLCLK_BASE, 8);
  672. del_timer_sync(&switchover_timer);
  673. kfree(alarm_events);
  674. }
  675. static void switchover_timeout(unsigned long data)
  676. {
  677. if ((data & 1)) {
  678. if ((inb(TLCLK_REG1) & 0x08) != (data & 0x08))
  679. alarm_events->switchover_primary++;
  680. } else {
  681. if ((inb(TLCLK_REG1) & 0x08) != (data & 0x08))
  682. alarm_events->switchover_secondary++;
  683. }
  684. /* Alarm processing is done, wake up read task */
  685. del_timer(&switchover_timer);
  686. got_event = 1;
  687. wake_up(&wq);
  688. }
  689. static irqreturn_t tlclk_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  690. {
  691. unsigned long flags;
  692. spin_lock_irqsave(&event_lock, flags);
  693. /* Read and clear interrupt events */
  694. int_events = inb(TLCLK_REG6);
  695. /* Primary_Los changed from 0 to 1 ? */
  696. if (int_events & PRI_LOS_01_MASK) {
  697. if (inb(TLCLK_REG2) & SEC_LOST_MASK)
  698. alarm_events->lost_clocks++;
  699. else
  700. alarm_events->lost_primary_clock++;
  701. }
  702. /* Primary_Los changed from 1 to 0 ? */
  703. if (int_events & PRI_LOS_10_MASK) {
  704. alarm_events->primary_clock_back++;
  705. SET_PORT_BITS(TLCLK_REG1, 0xFE, 1);
  706. }
  707. /* Secondary_Los changed from 0 to 1 ? */
  708. if (int_events & SEC_LOS_01_MASK) {
  709. if (inb(TLCLK_REG2) & PRI_LOST_MASK)
  710. alarm_events->lost_clocks++;
  711. else
  712. alarm_events->lost_secondary_clock++;
  713. }
  714. /* Secondary_Los changed from 1 to 0 ? */
  715. if (int_events & SEC_LOS_10_MASK) {
  716. alarm_events->secondary_clock_back++;
  717. SET_PORT_BITS(TLCLK_REG1, 0xFE, 0);
  718. }
  719. if (int_events & HOLDOVER_10_MASK)
  720. alarm_events->pll_end_holdover++;
  721. if (int_events & UNLOCK_01_MASK)
  722. alarm_events->pll_lost_sync++;
  723. if (int_events & UNLOCK_10_MASK)
  724. alarm_events->pll_sync++;
  725. /* Holdover changed from 0 to 1 ? */
  726. if (int_events & HOLDOVER_01_MASK) {
  727. alarm_events->pll_holdover++;
  728. /* TIMEOUT in ~10ms */
  729. switchover_timer.expires = jiffies + msecs_to_jiffies(10);
  730. switchover_timer.data = inb(TLCLK_REG1);
  731. add_timer(&switchover_timer);
  732. } else {
  733. got_event = 1;
  734. wake_up(&wq);
  735. }
  736. spin_unlock_irqrestore(&event_lock, flags);
  737. return IRQ_HANDLED;
  738. }
  739. module_init(tlclk_init);
  740. module_exit(tlclk_cleanup);