cciss.h 6.8 KB

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  1. #ifndef CCISS_H
  2. #define CCISS_H
  3. #include <linux/genhd.h>
  4. #include "cciss_cmd.h"
  5. #define NWD 16
  6. #define NWD_SHIFT 4
  7. #define MAX_PART (1 << NWD_SHIFT)
  8. #define IO_OK 0
  9. #define IO_ERROR 1
  10. struct ctlr_info;
  11. typedef struct ctlr_info ctlr_info_t;
  12. struct access_method {
  13. void (*submit_command)(ctlr_info_t *h, CommandList_struct *c);
  14. void (*set_intr_mask)(ctlr_info_t *h, unsigned long val);
  15. unsigned long (*fifo_full)(ctlr_info_t *h);
  16. unsigned long (*intr_pending)(ctlr_info_t *h);
  17. unsigned long (*command_completed)(ctlr_info_t *h);
  18. };
  19. typedef struct _drive_info_struct
  20. {
  21. __u32 LunID;
  22. int usage_count;
  23. struct request_queue *queue;
  24. sector_t nr_blocks;
  25. int block_size;
  26. int heads;
  27. int sectors;
  28. int cylinders;
  29. int raid_level; /* set to -1 to indicate that
  30. * the drive is not in use/configured
  31. */
  32. int busy_configuring; /*This is set when the drive is being removed
  33. *to prevent it from being opened or it's queue
  34. *from being started.
  35. */
  36. } drive_info_struct;
  37. #ifdef CONFIG_CISS_SCSI_TAPE
  38. struct sendcmd_reject_list {
  39. int ncompletions;
  40. unsigned long *complete; /* array of NR_CMDS tags */
  41. };
  42. #endif
  43. struct ctlr_info
  44. {
  45. int ctlr;
  46. char devname[8];
  47. char *product_name;
  48. char firm_ver[4]; // Firmware version
  49. struct pci_dev *pdev;
  50. __u32 board_id;
  51. void __iomem *vaddr;
  52. unsigned long paddr;
  53. unsigned long io_mem_addr;
  54. unsigned long io_mem_length;
  55. CfgTable_struct __iomem *cfgtable;
  56. int interrupts_enabled;
  57. int major;
  58. int max_commands;
  59. int commands_outstanding;
  60. int max_outstanding; /* Debug */
  61. int num_luns;
  62. int highest_lun;
  63. int usage_count; /* number of opens all all minor devices */
  64. # define DOORBELL_INT 0
  65. # define PERF_MODE_INT 1
  66. # define SIMPLE_MODE_INT 2
  67. # define MEMQ_MODE_INT 3
  68. unsigned int intr[4];
  69. unsigned int msix_vector;
  70. unsigned int msi_vector;
  71. // information about each logical volume
  72. drive_info_struct drv[CISS_MAX_LUN];
  73. struct access_method access;
  74. /* queue and queue Info */
  75. CommandList_struct *reqQ;
  76. CommandList_struct *cmpQ;
  77. unsigned int Qdepth;
  78. unsigned int maxQsinceinit;
  79. unsigned int maxSG;
  80. spinlock_t lock;
  81. //* pointers to command and error info pool */
  82. CommandList_struct *cmd_pool;
  83. dma_addr_t cmd_pool_dhandle;
  84. ErrorInfo_struct *errinfo_pool;
  85. dma_addr_t errinfo_pool_dhandle;
  86. unsigned long *cmd_pool_bits;
  87. int nr_allocs;
  88. int nr_frees;
  89. int busy_configuring;
  90. int busy_initializing;
  91. /* This element holds the zero based queue number of the last
  92. * queue to be started. It is used for fairness.
  93. */
  94. int next_to_run;
  95. // Disk structures we need to pass back
  96. struct gendisk *gendisk[NWD];
  97. #ifdef CONFIG_CISS_SCSI_TAPE
  98. void *scsi_ctlr; /* ptr to structure containing scsi related stuff */
  99. /* list of block side commands the scsi error handling sucked up */
  100. /* and saved for later processing */
  101. struct sendcmd_reject_list scsi_rejects;
  102. #endif
  103. unsigned char alive;
  104. };
  105. /* Defining the diffent access_menthods */
  106. /*
  107. * Memory mapped FIFO interface (SMART 53xx cards)
  108. */
  109. #define SA5_DOORBELL 0x20
  110. #define SA5_REQUEST_PORT_OFFSET 0x40
  111. #define SA5_REPLY_INTR_MASK_OFFSET 0x34
  112. #define SA5_REPLY_PORT_OFFSET 0x44
  113. #define SA5_INTR_STATUS 0x30
  114. #define SA5_SCRATCHPAD_OFFSET 0xB0
  115. #define SA5_CTCFG_OFFSET 0xB4
  116. #define SA5_CTMEM_OFFSET 0xB8
  117. #define SA5_INTR_OFF 0x08
  118. #define SA5B_INTR_OFF 0x04
  119. #define SA5_INTR_PENDING 0x08
  120. #define SA5B_INTR_PENDING 0x04
  121. #define FIFO_EMPTY 0xffffffff
  122. #define CCISS_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
  123. #define CISS_ERROR_BIT 0x02
  124. #define CCISS_INTR_ON 1
  125. #define CCISS_INTR_OFF 0
  126. /*
  127. Send the command to the hardware
  128. */
  129. static void SA5_submit_command( ctlr_info_t *h, CommandList_struct *c)
  130. {
  131. #ifdef CCISS_DEBUG
  132. printk("Sending %x - down to controller\n", c->busaddr );
  133. #endif /* CCISS_DEBUG */
  134. writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
  135. h->commands_outstanding++;
  136. if ( h->commands_outstanding > h->max_outstanding)
  137. h->max_outstanding = h->commands_outstanding;
  138. }
  139. /*
  140. * This card is the opposite of the other cards.
  141. * 0 turns interrupts on...
  142. * 0x08 turns them off...
  143. */
  144. static void SA5_intr_mask(ctlr_info_t *h, unsigned long val)
  145. {
  146. if (val)
  147. { /* Turn interrupts on */
  148. h->interrupts_enabled = 1;
  149. writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  150. } else /* Turn them off */
  151. {
  152. h->interrupts_enabled = 0;
  153. writel( SA5_INTR_OFF,
  154. h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  155. }
  156. }
  157. /*
  158. * This card is the opposite of the other cards.
  159. * 0 turns interrupts on...
  160. * 0x04 turns them off...
  161. */
  162. static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val)
  163. {
  164. if (val)
  165. { /* Turn interrupts on */
  166. h->interrupts_enabled = 1;
  167. writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  168. } else /* Turn them off */
  169. {
  170. h->interrupts_enabled = 0;
  171. writel( SA5B_INTR_OFF,
  172. h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  173. }
  174. }
  175. /*
  176. * Returns true if fifo is full.
  177. *
  178. */
  179. static unsigned long SA5_fifo_full(ctlr_info_t *h)
  180. {
  181. if( h->commands_outstanding >= h->max_commands)
  182. return(1);
  183. else
  184. return(0);
  185. }
  186. /*
  187. * returns value read from hardware.
  188. * returns FIFO_EMPTY if there is nothing to read
  189. */
  190. static unsigned long SA5_completed(ctlr_info_t *h)
  191. {
  192. unsigned long register_value
  193. = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
  194. if(register_value != FIFO_EMPTY)
  195. {
  196. h->commands_outstanding--;
  197. #ifdef CCISS_DEBUG
  198. printk("cciss: Read %lx back from board\n", register_value);
  199. #endif /* CCISS_DEBUG */
  200. }
  201. #ifdef CCISS_DEBUG
  202. else
  203. {
  204. printk("cciss: FIFO Empty read\n");
  205. }
  206. #endif
  207. return ( register_value);
  208. }
  209. /*
  210. * Returns true if an interrupt is pending..
  211. */
  212. static unsigned long SA5_intr_pending(ctlr_info_t *h)
  213. {
  214. unsigned long register_value =
  215. readl(h->vaddr + SA5_INTR_STATUS);
  216. #ifdef CCISS_DEBUG
  217. printk("cciss: intr_pending %lx\n", register_value);
  218. #endif /* CCISS_DEBUG */
  219. if( register_value & SA5_INTR_PENDING)
  220. return 1;
  221. return 0 ;
  222. }
  223. /*
  224. * Returns true if an interrupt is pending..
  225. */
  226. static unsigned long SA5B_intr_pending(ctlr_info_t *h)
  227. {
  228. unsigned long register_value =
  229. readl(h->vaddr + SA5_INTR_STATUS);
  230. #ifdef CCISS_DEBUG
  231. printk("cciss: intr_pending %lx\n", register_value);
  232. #endif /* CCISS_DEBUG */
  233. if( register_value & SA5B_INTR_PENDING)
  234. return 1;
  235. return 0 ;
  236. }
  237. static struct access_method SA5_access = {
  238. SA5_submit_command,
  239. SA5_intr_mask,
  240. SA5_fifo_full,
  241. SA5_intr_pending,
  242. SA5_completed,
  243. };
  244. static struct access_method SA5B_access = {
  245. SA5_submit_command,
  246. SA5B_intr_mask,
  247. SA5_fifo_full,
  248. SA5B_intr_pending,
  249. SA5_completed,
  250. };
  251. struct board_type {
  252. __u32 board_id;
  253. char *product_name;
  254. struct access_method *access;
  255. };
  256. #define CCISS_LOCK(i) (&hba[i]->lock)
  257. #endif /* CCISS_H */