he.c 82 KB

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  1. /* $Id: he.c,v 1.18 2003/05/06 22:57:15 chas Exp $ */
  2. /*
  3. he.c
  4. ForeRunnerHE ATM Adapter driver for ATM on Linux
  5. Copyright (C) 1999-2001 Naval Research Laboratory
  6. This library is free software; you can redistribute it and/or
  7. modify it under the terms of the GNU Lesser General Public
  8. License as published by the Free Software Foundation; either
  9. version 2.1 of the License, or (at your option) any later version.
  10. This library is distributed in the hope that it will be useful,
  11. but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. Lesser General Public License for more details.
  14. You should have received a copy of the GNU Lesser General Public
  15. License along with this library; if not, write to the Free Software
  16. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  17. */
  18. /*
  19. he.c
  20. ForeRunnerHE ATM Adapter driver for ATM on Linux
  21. Copyright (C) 1999-2001 Naval Research Laboratory
  22. Permission to use, copy, modify and distribute this software and its
  23. documentation is hereby granted, provided that both the copyright
  24. notice and this permission notice appear in all copies of the software,
  25. derivative works or modified versions, and any portions thereof, and
  26. that both notices appear in supporting documentation.
  27. NRL ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" CONDITION AND
  28. DISCLAIMS ANY LIABILITY OF ANY KIND FOR ANY DAMAGES WHATSOEVER
  29. RESULTING FROM THE USE OF THIS SOFTWARE.
  30. This driver was written using the "Programmer's Reference Manual for
  31. ForeRunnerHE(tm)", MANU0361-01 - Rev. A, 08/21/98.
  32. AUTHORS:
  33. chas williams <chas@cmf.nrl.navy.mil>
  34. eric kinzie <ekinzie@cmf.nrl.navy.mil>
  35. NOTES:
  36. 4096 supported 'connections'
  37. group 0 is used for all traffic
  38. interrupt queue 0 is used for all interrupts
  39. aal0 support (based on work from ulrich.u.muller@nokia.com)
  40. */
  41. #include <linux/config.h>
  42. #include <linux/module.h>
  43. #include <linux/kernel.h>
  44. #include <linux/skbuff.h>
  45. #include <linux/pci.h>
  46. #include <linux/errno.h>
  47. #include <linux/types.h>
  48. #include <linux/string.h>
  49. #include <linux/delay.h>
  50. #include <linux/init.h>
  51. #include <linux/mm.h>
  52. #include <linux/sched.h>
  53. #include <linux/timer.h>
  54. #include <linux/interrupt.h>
  55. #include <linux/dma-mapping.h>
  56. #include <asm/io.h>
  57. #include <asm/byteorder.h>
  58. #include <asm/uaccess.h>
  59. #include <linux/atmdev.h>
  60. #include <linux/atm.h>
  61. #include <linux/sonet.h>
  62. #define USE_TASKLET
  63. #undef USE_SCATTERGATHER
  64. #undef USE_CHECKSUM_HW /* still confused about this */
  65. #define USE_RBPS
  66. #undef USE_RBPS_POOL /* if memory is tight try this */
  67. #undef USE_RBPL_POOL /* if memory is tight try this */
  68. #define USE_TPD_POOL
  69. /* #undef CONFIG_ATM_HE_USE_SUNI */
  70. /* #undef HE_DEBUG */
  71. #include "he.h"
  72. #include "suni.h"
  73. #include <linux/atm_he.h>
  74. #define hprintk(fmt,args...) printk(KERN_ERR DEV_LABEL "%d: " fmt, he_dev->number , ##args)
  75. #ifdef HE_DEBUG
  76. #define HPRINTK(fmt,args...) printk(KERN_DEBUG DEV_LABEL "%d: " fmt, he_dev->number , ##args)
  77. #else /* !HE_DEBUG */
  78. #define HPRINTK(fmt,args...) do { } while (0)
  79. #endif /* HE_DEBUG */
  80. /* version definition */
  81. static char *version = "$Id: he.c,v 1.18 2003/05/06 22:57:15 chas Exp $";
  82. /* declarations */
  83. static int he_open(struct atm_vcc *vcc);
  84. static void he_close(struct atm_vcc *vcc);
  85. static int he_send(struct atm_vcc *vcc, struct sk_buff *skb);
  86. static int he_ioctl(struct atm_dev *dev, unsigned int cmd, void __user *arg);
  87. static irqreturn_t he_irq_handler(int irq, void *dev_id, struct pt_regs *regs);
  88. static void he_tasklet(unsigned long data);
  89. static int he_proc_read(struct atm_dev *dev,loff_t *pos,char *page);
  90. static int he_start(struct atm_dev *dev);
  91. static void he_stop(struct he_dev *dev);
  92. static void he_phy_put(struct atm_dev *, unsigned char, unsigned long);
  93. static unsigned char he_phy_get(struct atm_dev *, unsigned long);
  94. static u8 read_prom_byte(struct he_dev *he_dev, int addr);
  95. /* globals */
  96. static struct he_dev *he_devs;
  97. static int disable64;
  98. static short nvpibits = -1;
  99. static short nvcibits = -1;
  100. static short rx_skb_reserve = 16;
  101. static int irq_coalesce = 1;
  102. static int sdh = 0;
  103. /* Read from EEPROM = 0000 0011b */
  104. static unsigned int readtab[] = {
  105. CS_HIGH | CLK_HIGH,
  106. CS_LOW | CLK_LOW,
  107. CLK_HIGH, /* 0 */
  108. CLK_LOW,
  109. CLK_HIGH, /* 0 */
  110. CLK_LOW,
  111. CLK_HIGH, /* 0 */
  112. CLK_LOW,
  113. CLK_HIGH, /* 0 */
  114. CLK_LOW,
  115. CLK_HIGH, /* 0 */
  116. CLK_LOW,
  117. CLK_HIGH, /* 0 */
  118. CLK_LOW | SI_HIGH,
  119. CLK_HIGH | SI_HIGH, /* 1 */
  120. CLK_LOW | SI_HIGH,
  121. CLK_HIGH | SI_HIGH /* 1 */
  122. };
  123. /* Clock to read from/write to the EEPROM */
  124. static unsigned int clocktab[] = {
  125. CLK_LOW,
  126. CLK_HIGH,
  127. CLK_LOW,
  128. CLK_HIGH,
  129. CLK_LOW,
  130. CLK_HIGH,
  131. CLK_LOW,
  132. CLK_HIGH,
  133. CLK_LOW,
  134. CLK_HIGH,
  135. CLK_LOW,
  136. CLK_HIGH,
  137. CLK_LOW,
  138. CLK_HIGH,
  139. CLK_LOW,
  140. CLK_HIGH,
  141. CLK_LOW
  142. };
  143. static struct atmdev_ops he_ops =
  144. {
  145. .open = he_open,
  146. .close = he_close,
  147. .ioctl = he_ioctl,
  148. .send = he_send,
  149. .phy_put = he_phy_put,
  150. .phy_get = he_phy_get,
  151. .proc_read = he_proc_read,
  152. .owner = THIS_MODULE
  153. };
  154. #define he_writel(dev, val, reg) do { writel(val, (dev)->membase + (reg)); wmb(); } while (0)
  155. #define he_readl(dev, reg) readl((dev)->membase + (reg))
  156. /* section 2.12 connection memory access */
  157. static __inline__ void
  158. he_writel_internal(struct he_dev *he_dev, unsigned val, unsigned addr,
  159. unsigned flags)
  160. {
  161. he_writel(he_dev, val, CON_DAT);
  162. (void) he_readl(he_dev, CON_DAT); /* flush posted writes */
  163. he_writel(he_dev, flags | CON_CTL_WRITE | CON_CTL_ADDR(addr), CON_CTL);
  164. while (he_readl(he_dev, CON_CTL) & CON_CTL_BUSY);
  165. }
  166. #define he_writel_rcm(dev, val, reg) \
  167. he_writel_internal(dev, val, reg, CON_CTL_RCM)
  168. #define he_writel_tcm(dev, val, reg) \
  169. he_writel_internal(dev, val, reg, CON_CTL_TCM)
  170. #define he_writel_mbox(dev, val, reg) \
  171. he_writel_internal(dev, val, reg, CON_CTL_MBOX)
  172. static unsigned
  173. he_readl_internal(struct he_dev *he_dev, unsigned addr, unsigned flags)
  174. {
  175. he_writel(he_dev, flags | CON_CTL_READ | CON_CTL_ADDR(addr), CON_CTL);
  176. while (he_readl(he_dev, CON_CTL) & CON_CTL_BUSY);
  177. return he_readl(he_dev, CON_DAT);
  178. }
  179. #define he_readl_rcm(dev, reg) \
  180. he_readl_internal(dev, reg, CON_CTL_RCM)
  181. #define he_readl_tcm(dev, reg) \
  182. he_readl_internal(dev, reg, CON_CTL_TCM)
  183. #define he_readl_mbox(dev, reg) \
  184. he_readl_internal(dev, reg, CON_CTL_MBOX)
  185. /* figure 2.2 connection id */
  186. #define he_mkcid(dev, vpi, vci) (((vpi << (dev)->vcibits) | vci) & 0x1fff)
  187. /* 2.5.1 per connection transmit state registers */
  188. #define he_writel_tsr0(dev, val, cid) \
  189. he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 0)
  190. #define he_readl_tsr0(dev, cid) \
  191. he_readl_tcm(dev, CONFIG_TSRA | (cid << 3) | 0)
  192. #define he_writel_tsr1(dev, val, cid) \
  193. he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 1)
  194. #define he_writel_tsr2(dev, val, cid) \
  195. he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 2)
  196. #define he_writel_tsr3(dev, val, cid) \
  197. he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 3)
  198. #define he_writel_tsr4(dev, val, cid) \
  199. he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 4)
  200. /* from page 2-20
  201. *
  202. * NOTE While the transmit connection is active, bits 23 through 0
  203. * of this register must not be written by the host. Byte
  204. * enables should be used during normal operation when writing
  205. * the most significant byte.
  206. */
  207. #define he_writel_tsr4_upper(dev, val, cid) \
  208. he_writel_internal(dev, val, CONFIG_TSRA | (cid << 3) | 4, \
  209. CON_CTL_TCM \
  210. | CON_BYTE_DISABLE_2 \
  211. | CON_BYTE_DISABLE_1 \
  212. | CON_BYTE_DISABLE_0)
  213. #define he_readl_tsr4(dev, cid) \
  214. he_readl_tcm(dev, CONFIG_TSRA | (cid << 3) | 4)
  215. #define he_writel_tsr5(dev, val, cid) \
  216. he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 5)
  217. #define he_writel_tsr6(dev, val, cid) \
  218. he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 6)
  219. #define he_writel_tsr7(dev, val, cid) \
  220. he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 7)
  221. #define he_writel_tsr8(dev, val, cid) \
  222. he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 0)
  223. #define he_writel_tsr9(dev, val, cid) \
  224. he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 1)
  225. #define he_writel_tsr10(dev, val, cid) \
  226. he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 2)
  227. #define he_writel_tsr11(dev, val, cid) \
  228. he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 3)
  229. #define he_writel_tsr12(dev, val, cid) \
  230. he_writel_tcm(dev, val, CONFIG_TSRC | (cid << 1) | 0)
  231. #define he_writel_tsr13(dev, val, cid) \
  232. he_writel_tcm(dev, val, CONFIG_TSRC | (cid << 1) | 1)
  233. #define he_writel_tsr14(dev, val, cid) \
  234. he_writel_tcm(dev, val, CONFIG_TSRD | cid)
  235. #define he_writel_tsr14_upper(dev, val, cid) \
  236. he_writel_internal(dev, val, CONFIG_TSRD | cid, \
  237. CON_CTL_TCM \
  238. | CON_BYTE_DISABLE_2 \
  239. | CON_BYTE_DISABLE_1 \
  240. | CON_BYTE_DISABLE_0)
  241. /* 2.7.1 per connection receive state registers */
  242. #define he_writel_rsr0(dev, val, cid) \
  243. he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 0)
  244. #define he_readl_rsr0(dev, cid) \
  245. he_readl_rcm(dev, 0x00000 | (cid << 3) | 0)
  246. #define he_writel_rsr1(dev, val, cid) \
  247. he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 1)
  248. #define he_writel_rsr2(dev, val, cid) \
  249. he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 2)
  250. #define he_writel_rsr3(dev, val, cid) \
  251. he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 3)
  252. #define he_writel_rsr4(dev, val, cid) \
  253. he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 4)
  254. #define he_writel_rsr5(dev, val, cid) \
  255. he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 5)
  256. #define he_writel_rsr6(dev, val, cid) \
  257. he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 6)
  258. #define he_writel_rsr7(dev, val, cid) \
  259. he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 7)
  260. static __inline__ struct atm_vcc*
  261. __find_vcc(struct he_dev *he_dev, unsigned cid)
  262. {
  263. struct hlist_head *head;
  264. struct atm_vcc *vcc;
  265. struct hlist_node *node;
  266. struct sock *s;
  267. short vpi;
  268. int vci;
  269. vpi = cid >> he_dev->vcibits;
  270. vci = cid & ((1 << he_dev->vcibits) - 1);
  271. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  272. sk_for_each(s, node, head) {
  273. vcc = atm_sk(s);
  274. if (vcc->dev == he_dev->atm_dev &&
  275. vcc->vci == vci && vcc->vpi == vpi &&
  276. vcc->qos.rxtp.traffic_class != ATM_NONE) {
  277. return vcc;
  278. }
  279. }
  280. return NULL;
  281. }
  282. static int __devinit
  283. he_init_one(struct pci_dev *pci_dev, const struct pci_device_id *pci_ent)
  284. {
  285. struct atm_dev *atm_dev = NULL;
  286. struct he_dev *he_dev = NULL;
  287. int err = 0;
  288. printk(KERN_INFO "he: %s\n", version);
  289. if (pci_enable_device(pci_dev))
  290. return -EIO;
  291. if (pci_set_dma_mask(pci_dev, DMA_32BIT_MASK) != 0) {
  292. printk(KERN_WARNING "he: no suitable dma available\n");
  293. err = -EIO;
  294. goto init_one_failure;
  295. }
  296. atm_dev = atm_dev_register(DEV_LABEL, &he_ops, -1, NULL);
  297. if (!atm_dev) {
  298. err = -ENODEV;
  299. goto init_one_failure;
  300. }
  301. pci_set_drvdata(pci_dev, atm_dev);
  302. he_dev = (struct he_dev *) kmalloc(sizeof(struct he_dev),
  303. GFP_KERNEL);
  304. if (!he_dev) {
  305. err = -ENOMEM;
  306. goto init_one_failure;
  307. }
  308. memset(he_dev, 0, sizeof(struct he_dev));
  309. he_dev->pci_dev = pci_dev;
  310. he_dev->atm_dev = atm_dev;
  311. he_dev->atm_dev->dev_data = he_dev;
  312. atm_dev->dev_data = he_dev;
  313. he_dev->number = atm_dev->number;
  314. if (he_start(atm_dev)) {
  315. he_stop(he_dev);
  316. err = -ENODEV;
  317. goto init_one_failure;
  318. }
  319. he_dev->next = NULL;
  320. if (he_devs)
  321. he_dev->next = he_devs;
  322. he_devs = he_dev;
  323. return 0;
  324. init_one_failure:
  325. if (atm_dev)
  326. atm_dev_deregister(atm_dev);
  327. kfree(he_dev);
  328. pci_disable_device(pci_dev);
  329. return err;
  330. }
  331. static void __devexit
  332. he_remove_one (struct pci_dev *pci_dev)
  333. {
  334. struct atm_dev *atm_dev;
  335. struct he_dev *he_dev;
  336. atm_dev = pci_get_drvdata(pci_dev);
  337. he_dev = HE_DEV(atm_dev);
  338. /* need to remove from he_devs */
  339. he_stop(he_dev);
  340. atm_dev_deregister(atm_dev);
  341. kfree(he_dev);
  342. pci_set_drvdata(pci_dev, NULL);
  343. pci_disable_device(pci_dev);
  344. }
  345. static unsigned
  346. rate_to_atmf(unsigned rate) /* cps to atm forum format */
  347. {
  348. #define NONZERO (1 << 14)
  349. unsigned exp = 0;
  350. if (rate == 0)
  351. return 0;
  352. rate <<= 9;
  353. while (rate > 0x3ff) {
  354. ++exp;
  355. rate >>= 1;
  356. }
  357. return (NONZERO | (exp << 9) | (rate & 0x1ff));
  358. }
  359. static void __init
  360. he_init_rx_lbfp0(struct he_dev *he_dev)
  361. {
  362. unsigned i, lbm_offset, lbufd_index, lbuf_addr, lbuf_count;
  363. unsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;
  364. unsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;
  365. unsigned row_offset = he_dev->r0_startrow * he_dev->bytes_per_row;
  366. lbufd_index = 0;
  367. lbm_offset = he_readl(he_dev, RCMLBM_BA);
  368. he_writel(he_dev, lbufd_index, RLBF0_H);
  369. for (i = 0, lbuf_count = 0; i < he_dev->r0_numbuffs; ++i) {
  370. lbufd_index += 2;
  371. lbuf_addr = (row_offset + (lbuf_count * lbuf_bufsize)) / 32;
  372. he_writel_rcm(he_dev, lbuf_addr, lbm_offset);
  373. he_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);
  374. if (++lbuf_count == lbufs_per_row) {
  375. lbuf_count = 0;
  376. row_offset += he_dev->bytes_per_row;
  377. }
  378. lbm_offset += 4;
  379. }
  380. he_writel(he_dev, lbufd_index - 2, RLBF0_T);
  381. he_writel(he_dev, he_dev->r0_numbuffs, RLBF0_C);
  382. }
  383. static void __init
  384. he_init_rx_lbfp1(struct he_dev *he_dev)
  385. {
  386. unsigned i, lbm_offset, lbufd_index, lbuf_addr, lbuf_count;
  387. unsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;
  388. unsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;
  389. unsigned row_offset = he_dev->r1_startrow * he_dev->bytes_per_row;
  390. lbufd_index = 1;
  391. lbm_offset = he_readl(he_dev, RCMLBM_BA) + (2 * lbufd_index);
  392. he_writel(he_dev, lbufd_index, RLBF1_H);
  393. for (i = 0, lbuf_count = 0; i < he_dev->r1_numbuffs; ++i) {
  394. lbufd_index += 2;
  395. lbuf_addr = (row_offset + (lbuf_count * lbuf_bufsize)) / 32;
  396. he_writel_rcm(he_dev, lbuf_addr, lbm_offset);
  397. he_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);
  398. if (++lbuf_count == lbufs_per_row) {
  399. lbuf_count = 0;
  400. row_offset += he_dev->bytes_per_row;
  401. }
  402. lbm_offset += 4;
  403. }
  404. he_writel(he_dev, lbufd_index - 2, RLBF1_T);
  405. he_writel(he_dev, he_dev->r1_numbuffs, RLBF1_C);
  406. }
  407. static void __init
  408. he_init_tx_lbfp(struct he_dev *he_dev)
  409. {
  410. unsigned i, lbm_offset, lbufd_index, lbuf_addr, lbuf_count;
  411. unsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;
  412. unsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;
  413. unsigned row_offset = he_dev->tx_startrow * he_dev->bytes_per_row;
  414. lbufd_index = he_dev->r0_numbuffs + he_dev->r1_numbuffs;
  415. lbm_offset = he_readl(he_dev, RCMLBM_BA) + (2 * lbufd_index);
  416. he_writel(he_dev, lbufd_index, TLBF_H);
  417. for (i = 0, lbuf_count = 0; i < he_dev->tx_numbuffs; ++i) {
  418. lbufd_index += 1;
  419. lbuf_addr = (row_offset + (lbuf_count * lbuf_bufsize)) / 32;
  420. he_writel_rcm(he_dev, lbuf_addr, lbm_offset);
  421. he_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);
  422. if (++lbuf_count == lbufs_per_row) {
  423. lbuf_count = 0;
  424. row_offset += he_dev->bytes_per_row;
  425. }
  426. lbm_offset += 2;
  427. }
  428. he_writel(he_dev, lbufd_index - 1, TLBF_T);
  429. }
  430. static int __init
  431. he_init_tpdrq(struct he_dev *he_dev)
  432. {
  433. he_dev->tpdrq_base = pci_alloc_consistent(he_dev->pci_dev,
  434. CONFIG_TPDRQ_SIZE * sizeof(struct he_tpdrq), &he_dev->tpdrq_phys);
  435. if (he_dev->tpdrq_base == NULL) {
  436. hprintk("failed to alloc tpdrq\n");
  437. return -ENOMEM;
  438. }
  439. memset(he_dev->tpdrq_base, 0,
  440. CONFIG_TPDRQ_SIZE * sizeof(struct he_tpdrq));
  441. he_dev->tpdrq_tail = he_dev->tpdrq_base;
  442. he_dev->tpdrq_head = he_dev->tpdrq_base;
  443. he_writel(he_dev, he_dev->tpdrq_phys, TPDRQ_B_H);
  444. he_writel(he_dev, 0, TPDRQ_T);
  445. he_writel(he_dev, CONFIG_TPDRQ_SIZE - 1, TPDRQ_S);
  446. return 0;
  447. }
  448. static void __init
  449. he_init_cs_block(struct he_dev *he_dev)
  450. {
  451. unsigned clock, rate, delta;
  452. int reg;
  453. /* 5.1.7 cs block initialization */
  454. for (reg = 0; reg < 0x20; ++reg)
  455. he_writel_mbox(he_dev, 0x0, CS_STTIM0 + reg);
  456. /* rate grid timer reload values */
  457. clock = he_is622(he_dev) ? 66667000 : 50000000;
  458. rate = he_dev->atm_dev->link_rate;
  459. delta = rate / 16 / 2;
  460. for (reg = 0; reg < 0x10; ++reg) {
  461. /* 2.4 internal transmit function
  462. *
  463. * we initialize the first row in the rate grid.
  464. * values are period (in clock cycles) of timer
  465. */
  466. unsigned period = clock / rate;
  467. he_writel_mbox(he_dev, period, CS_TGRLD0 + reg);
  468. rate -= delta;
  469. }
  470. if (he_is622(he_dev)) {
  471. /* table 5.2 (4 cells per lbuf) */
  472. he_writel_mbox(he_dev, 0x000800fa, CS_ERTHR0);
  473. he_writel_mbox(he_dev, 0x000c33cb, CS_ERTHR1);
  474. he_writel_mbox(he_dev, 0x0010101b, CS_ERTHR2);
  475. he_writel_mbox(he_dev, 0x00181dac, CS_ERTHR3);
  476. he_writel_mbox(he_dev, 0x00280600, CS_ERTHR4);
  477. /* table 5.3, 5.4, 5.5, 5.6, 5.7 */
  478. he_writel_mbox(he_dev, 0x023de8b3, CS_ERCTL0);
  479. he_writel_mbox(he_dev, 0x1801, CS_ERCTL1);
  480. he_writel_mbox(he_dev, 0x68b3, CS_ERCTL2);
  481. he_writel_mbox(he_dev, 0x1280, CS_ERSTAT0);
  482. he_writel_mbox(he_dev, 0x68b3, CS_ERSTAT1);
  483. he_writel_mbox(he_dev, 0x14585, CS_RTFWR);
  484. he_writel_mbox(he_dev, 0x4680, CS_RTATR);
  485. /* table 5.8 */
  486. he_writel_mbox(he_dev, 0x00159ece, CS_TFBSET);
  487. he_writel_mbox(he_dev, 0x68b3, CS_WCRMAX);
  488. he_writel_mbox(he_dev, 0x5eb3, CS_WCRMIN);
  489. he_writel_mbox(he_dev, 0xe8b3, CS_WCRINC);
  490. he_writel_mbox(he_dev, 0xdeb3, CS_WCRDEC);
  491. he_writel_mbox(he_dev, 0x68b3, CS_WCRCEIL);
  492. /* table 5.9 */
  493. he_writel_mbox(he_dev, 0x5, CS_OTPPER);
  494. he_writel_mbox(he_dev, 0x14, CS_OTWPER);
  495. } else {
  496. /* table 5.1 (4 cells per lbuf) */
  497. he_writel_mbox(he_dev, 0x000400ea, CS_ERTHR0);
  498. he_writel_mbox(he_dev, 0x00063388, CS_ERTHR1);
  499. he_writel_mbox(he_dev, 0x00081018, CS_ERTHR2);
  500. he_writel_mbox(he_dev, 0x000c1dac, CS_ERTHR3);
  501. he_writel_mbox(he_dev, 0x0014051a, CS_ERTHR4);
  502. /* table 5.3, 5.4, 5.5, 5.6, 5.7 */
  503. he_writel_mbox(he_dev, 0x0235e4b1, CS_ERCTL0);
  504. he_writel_mbox(he_dev, 0x4701, CS_ERCTL1);
  505. he_writel_mbox(he_dev, 0x64b1, CS_ERCTL2);
  506. he_writel_mbox(he_dev, 0x1280, CS_ERSTAT0);
  507. he_writel_mbox(he_dev, 0x64b1, CS_ERSTAT1);
  508. he_writel_mbox(he_dev, 0xf424, CS_RTFWR);
  509. he_writel_mbox(he_dev, 0x4680, CS_RTATR);
  510. /* table 5.8 */
  511. he_writel_mbox(he_dev, 0x000563b7, CS_TFBSET);
  512. he_writel_mbox(he_dev, 0x64b1, CS_WCRMAX);
  513. he_writel_mbox(he_dev, 0x5ab1, CS_WCRMIN);
  514. he_writel_mbox(he_dev, 0xe4b1, CS_WCRINC);
  515. he_writel_mbox(he_dev, 0xdab1, CS_WCRDEC);
  516. he_writel_mbox(he_dev, 0x64b1, CS_WCRCEIL);
  517. /* table 5.9 */
  518. he_writel_mbox(he_dev, 0x6, CS_OTPPER);
  519. he_writel_mbox(he_dev, 0x1e, CS_OTWPER);
  520. }
  521. he_writel_mbox(he_dev, 0x8, CS_OTTLIM);
  522. for (reg = 0; reg < 0x8; ++reg)
  523. he_writel_mbox(he_dev, 0x0, CS_HGRRT0 + reg);
  524. }
  525. static int __init
  526. he_init_cs_block_rcm(struct he_dev *he_dev)
  527. {
  528. unsigned (*rategrid)[16][16];
  529. unsigned rate, delta;
  530. int i, j, reg;
  531. unsigned rate_atmf, exp, man;
  532. unsigned long long rate_cps;
  533. int mult, buf, buf_limit = 4;
  534. rategrid = kmalloc( sizeof(unsigned) * 16 * 16, GFP_KERNEL);
  535. if (!rategrid)
  536. return -ENOMEM;
  537. /* initialize rate grid group table */
  538. for (reg = 0x0; reg < 0xff; ++reg)
  539. he_writel_rcm(he_dev, 0x0, CONFIG_RCMABR + reg);
  540. /* initialize rate controller groups */
  541. for (reg = 0x100; reg < 0x1ff; ++reg)
  542. he_writel_rcm(he_dev, 0x0, CONFIG_RCMABR + reg);
  543. /* initialize tNrm lookup table */
  544. /* the manual makes reference to a routine in a sample driver
  545. for proper configuration; fortunately, we only need this
  546. in order to support abr connection */
  547. /* initialize rate to group table */
  548. rate = he_dev->atm_dev->link_rate;
  549. delta = rate / 32;
  550. /*
  551. * 2.4 transmit internal functions
  552. *
  553. * we construct a copy of the rate grid used by the scheduler
  554. * in order to construct the rate to group table below
  555. */
  556. for (j = 0; j < 16; j++) {
  557. (*rategrid)[0][j] = rate;
  558. rate -= delta;
  559. }
  560. for (i = 1; i < 16; i++)
  561. for (j = 0; j < 16; j++)
  562. if (i > 14)
  563. (*rategrid)[i][j] = (*rategrid)[i - 1][j] / 4;
  564. else
  565. (*rategrid)[i][j] = (*rategrid)[i - 1][j] / 2;
  566. /*
  567. * 2.4 transmit internal function
  568. *
  569. * this table maps the upper 5 bits of exponent and mantissa
  570. * of the atm forum representation of the rate into an index
  571. * on rate grid
  572. */
  573. rate_atmf = 0;
  574. while (rate_atmf < 0x400) {
  575. man = (rate_atmf & 0x1f) << 4;
  576. exp = rate_atmf >> 5;
  577. /*
  578. instead of '/ 512', use '>> 9' to prevent a call
  579. to divdu3 on x86 platforms
  580. */
  581. rate_cps = (unsigned long long) (1 << exp) * (man + 512) >> 9;
  582. if (rate_cps < 10)
  583. rate_cps = 10; /* 2.2.1 minimum payload rate is 10 cps */
  584. for (i = 255; i > 0; i--)
  585. if ((*rategrid)[i/16][i%16] >= rate_cps)
  586. break; /* pick nearest rate instead? */
  587. /*
  588. * each table entry is 16 bits: (rate grid index (8 bits)
  589. * and a buffer limit (8 bits)
  590. * there are two table entries in each 32-bit register
  591. */
  592. #ifdef notdef
  593. buf = rate_cps * he_dev->tx_numbuffs /
  594. (he_dev->atm_dev->link_rate * 2);
  595. #else
  596. /* this is pretty, but avoids _divdu3 and is mostly correct */
  597. mult = he_dev->atm_dev->link_rate / ATM_OC3_PCR;
  598. if (rate_cps > (272 * mult))
  599. buf = 4;
  600. else if (rate_cps > (204 * mult))
  601. buf = 3;
  602. else if (rate_cps > (136 * mult))
  603. buf = 2;
  604. else if (rate_cps > (68 * mult))
  605. buf = 1;
  606. else
  607. buf = 0;
  608. #endif
  609. if (buf > buf_limit)
  610. buf = buf_limit;
  611. reg = (reg << 16) | ((i << 8) | buf);
  612. #define RTGTBL_OFFSET 0x400
  613. if (rate_atmf & 0x1)
  614. he_writel_rcm(he_dev, reg,
  615. CONFIG_RCMABR + RTGTBL_OFFSET + (rate_atmf >> 1));
  616. ++rate_atmf;
  617. }
  618. kfree(rategrid);
  619. return 0;
  620. }
  621. static int __init
  622. he_init_group(struct he_dev *he_dev, int group)
  623. {
  624. int i;
  625. #ifdef USE_RBPS
  626. /* small buffer pool */
  627. #ifdef USE_RBPS_POOL
  628. he_dev->rbps_pool = pci_pool_create("rbps", he_dev->pci_dev,
  629. CONFIG_RBPS_BUFSIZE, 8, 0);
  630. if (he_dev->rbps_pool == NULL) {
  631. hprintk("unable to create rbps pages\n");
  632. return -ENOMEM;
  633. }
  634. #else /* !USE_RBPS_POOL */
  635. he_dev->rbps_pages = pci_alloc_consistent(he_dev->pci_dev,
  636. CONFIG_RBPS_SIZE * CONFIG_RBPS_BUFSIZE, &he_dev->rbps_pages_phys);
  637. if (he_dev->rbps_pages == NULL) {
  638. hprintk("unable to create rbps page pool\n");
  639. return -ENOMEM;
  640. }
  641. #endif /* USE_RBPS_POOL */
  642. he_dev->rbps_base = pci_alloc_consistent(he_dev->pci_dev,
  643. CONFIG_RBPS_SIZE * sizeof(struct he_rbp), &he_dev->rbps_phys);
  644. if (he_dev->rbps_base == NULL) {
  645. hprintk("failed to alloc rbps\n");
  646. return -ENOMEM;
  647. }
  648. memset(he_dev->rbps_base, 0, CONFIG_RBPS_SIZE * sizeof(struct he_rbp));
  649. he_dev->rbps_virt = kmalloc(CONFIG_RBPS_SIZE * sizeof(struct he_virt), GFP_KERNEL);
  650. for (i = 0; i < CONFIG_RBPS_SIZE; ++i) {
  651. dma_addr_t dma_handle;
  652. void *cpuaddr;
  653. #ifdef USE_RBPS_POOL
  654. cpuaddr = pci_pool_alloc(he_dev->rbps_pool, SLAB_KERNEL|SLAB_DMA, &dma_handle);
  655. if (cpuaddr == NULL)
  656. return -ENOMEM;
  657. #else
  658. cpuaddr = he_dev->rbps_pages + (i * CONFIG_RBPS_BUFSIZE);
  659. dma_handle = he_dev->rbps_pages_phys + (i * CONFIG_RBPS_BUFSIZE);
  660. #endif
  661. he_dev->rbps_virt[i].virt = cpuaddr;
  662. he_dev->rbps_base[i].status = RBP_LOANED | RBP_SMALLBUF | (i << RBP_INDEX_OFF);
  663. he_dev->rbps_base[i].phys = dma_handle;
  664. }
  665. he_dev->rbps_tail = &he_dev->rbps_base[CONFIG_RBPS_SIZE - 1];
  666. he_writel(he_dev, he_dev->rbps_phys, G0_RBPS_S + (group * 32));
  667. he_writel(he_dev, RBPS_MASK(he_dev->rbps_tail),
  668. G0_RBPS_T + (group * 32));
  669. he_writel(he_dev, CONFIG_RBPS_BUFSIZE/4,
  670. G0_RBPS_BS + (group * 32));
  671. he_writel(he_dev,
  672. RBP_THRESH(CONFIG_RBPS_THRESH) |
  673. RBP_QSIZE(CONFIG_RBPS_SIZE - 1) |
  674. RBP_INT_ENB,
  675. G0_RBPS_QI + (group * 32));
  676. #else /* !USE_RBPS */
  677. he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32));
  678. he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32));
  679. he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32));
  680. he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
  681. G0_RBPS_BS + (group * 32));
  682. #endif /* USE_RBPS */
  683. /* large buffer pool */
  684. #ifdef USE_RBPL_POOL
  685. he_dev->rbpl_pool = pci_pool_create("rbpl", he_dev->pci_dev,
  686. CONFIG_RBPL_BUFSIZE, 8, 0);
  687. if (he_dev->rbpl_pool == NULL) {
  688. hprintk("unable to create rbpl pool\n");
  689. return -ENOMEM;
  690. }
  691. #else /* !USE_RBPL_POOL */
  692. he_dev->rbpl_pages = (void *) pci_alloc_consistent(he_dev->pci_dev,
  693. CONFIG_RBPL_SIZE * CONFIG_RBPL_BUFSIZE, &he_dev->rbpl_pages_phys);
  694. if (he_dev->rbpl_pages == NULL) {
  695. hprintk("unable to create rbpl pages\n");
  696. return -ENOMEM;
  697. }
  698. #endif /* USE_RBPL_POOL */
  699. he_dev->rbpl_base = pci_alloc_consistent(he_dev->pci_dev,
  700. CONFIG_RBPL_SIZE * sizeof(struct he_rbp), &he_dev->rbpl_phys);
  701. if (he_dev->rbpl_base == NULL) {
  702. hprintk("failed to alloc rbpl\n");
  703. return -ENOMEM;
  704. }
  705. memset(he_dev->rbpl_base, 0, CONFIG_RBPL_SIZE * sizeof(struct he_rbp));
  706. he_dev->rbpl_virt = kmalloc(CONFIG_RBPL_SIZE * sizeof(struct he_virt), GFP_KERNEL);
  707. for (i = 0; i < CONFIG_RBPL_SIZE; ++i) {
  708. dma_addr_t dma_handle;
  709. void *cpuaddr;
  710. #ifdef USE_RBPL_POOL
  711. cpuaddr = pci_pool_alloc(he_dev->rbpl_pool, SLAB_KERNEL|SLAB_DMA, &dma_handle);
  712. if (cpuaddr == NULL)
  713. return -ENOMEM;
  714. #else
  715. cpuaddr = he_dev->rbpl_pages + (i * CONFIG_RBPL_BUFSIZE);
  716. dma_handle = he_dev->rbpl_pages_phys + (i * CONFIG_RBPL_BUFSIZE);
  717. #endif
  718. he_dev->rbpl_virt[i].virt = cpuaddr;
  719. he_dev->rbpl_base[i].status = RBP_LOANED | (i << RBP_INDEX_OFF);
  720. he_dev->rbpl_base[i].phys = dma_handle;
  721. }
  722. he_dev->rbpl_tail = &he_dev->rbpl_base[CONFIG_RBPL_SIZE - 1];
  723. he_writel(he_dev, he_dev->rbpl_phys, G0_RBPL_S + (group * 32));
  724. he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail),
  725. G0_RBPL_T + (group * 32));
  726. he_writel(he_dev, CONFIG_RBPL_BUFSIZE/4,
  727. G0_RBPL_BS + (group * 32));
  728. he_writel(he_dev,
  729. RBP_THRESH(CONFIG_RBPL_THRESH) |
  730. RBP_QSIZE(CONFIG_RBPL_SIZE - 1) |
  731. RBP_INT_ENB,
  732. G0_RBPL_QI + (group * 32));
  733. /* rx buffer ready queue */
  734. he_dev->rbrq_base = pci_alloc_consistent(he_dev->pci_dev,
  735. CONFIG_RBRQ_SIZE * sizeof(struct he_rbrq), &he_dev->rbrq_phys);
  736. if (he_dev->rbrq_base == NULL) {
  737. hprintk("failed to allocate rbrq\n");
  738. return -ENOMEM;
  739. }
  740. memset(he_dev->rbrq_base, 0, CONFIG_RBRQ_SIZE * sizeof(struct he_rbrq));
  741. he_dev->rbrq_head = he_dev->rbrq_base;
  742. he_writel(he_dev, he_dev->rbrq_phys, G0_RBRQ_ST + (group * 16));
  743. he_writel(he_dev, 0, G0_RBRQ_H + (group * 16));
  744. he_writel(he_dev,
  745. RBRQ_THRESH(CONFIG_RBRQ_THRESH) | RBRQ_SIZE(CONFIG_RBRQ_SIZE - 1),
  746. G0_RBRQ_Q + (group * 16));
  747. if (irq_coalesce) {
  748. hprintk("coalescing interrupts\n");
  749. he_writel(he_dev, RBRQ_TIME(768) | RBRQ_COUNT(7),
  750. G0_RBRQ_I + (group * 16));
  751. } else
  752. he_writel(he_dev, RBRQ_TIME(0) | RBRQ_COUNT(1),
  753. G0_RBRQ_I + (group * 16));
  754. /* tx buffer ready queue */
  755. he_dev->tbrq_base = pci_alloc_consistent(he_dev->pci_dev,
  756. CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq), &he_dev->tbrq_phys);
  757. if (he_dev->tbrq_base == NULL) {
  758. hprintk("failed to allocate tbrq\n");
  759. return -ENOMEM;
  760. }
  761. memset(he_dev->tbrq_base, 0, CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq));
  762. he_dev->tbrq_head = he_dev->tbrq_base;
  763. he_writel(he_dev, he_dev->tbrq_phys, G0_TBRQ_B_T + (group * 16));
  764. he_writel(he_dev, 0, G0_TBRQ_H + (group * 16));
  765. he_writel(he_dev, CONFIG_TBRQ_SIZE - 1, G0_TBRQ_S + (group * 16));
  766. he_writel(he_dev, CONFIG_TBRQ_THRESH, G0_TBRQ_THRESH + (group * 16));
  767. return 0;
  768. }
  769. static int __init
  770. he_init_irq(struct he_dev *he_dev)
  771. {
  772. int i;
  773. /* 2.9.3.5 tail offset for each interrupt queue is located after the
  774. end of the interrupt queue */
  775. he_dev->irq_base = pci_alloc_consistent(he_dev->pci_dev,
  776. (CONFIG_IRQ_SIZE+1) * sizeof(struct he_irq), &he_dev->irq_phys);
  777. if (he_dev->irq_base == NULL) {
  778. hprintk("failed to allocate irq\n");
  779. return -ENOMEM;
  780. }
  781. he_dev->irq_tailoffset = (unsigned *)
  782. &he_dev->irq_base[CONFIG_IRQ_SIZE];
  783. *he_dev->irq_tailoffset = 0;
  784. he_dev->irq_head = he_dev->irq_base;
  785. he_dev->irq_tail = he_dev->irq_base;
  786. for (i = 0; i < CONFIG_IRQ_SIZE; ++i)
  787. he_dev->irq_base[i].isw = ITYPE_INVALID;
  788. he_writel(he_dev, he_dev->irq_phys, IRQ0_BASE);
  789. he_writel(he_dev,
  790. IRQ_SIZE(CONFIG_IRQ_SIZE) | IRQ_THRESH(CONFIG_IRQ_THRESH),
  791. IRQ0_HEAD);
  792. he_writel(he_dev, IRQ_INT_A | IRQ_TYPE_LINE, IRQ0_CNTL);
  793. he_writel(he_dev, 0x0, IRQ0_DATA);
  794. he_writel(he_dev, 0x0, IRQ1_BASE);
  795. he_writel(he_dev, 0x0, IRQ1_HEAD);
  796. he_writel(he_dev, 0x0, IRQ1_CNTL);
  797. he_writel(he_dev, 0x0, IRQ1_DATA);
  798. he_writel(he_dev, 0x0, IRQ2_BASE);
  799. he_writel(he_dev, 0x0, IRQ2_HEAD);
  800. he_writel(he_dev, 0x0, IRQ2_CNTL);
  801. he_writel(he_dev, 0x0, IRQ2_DATA);
  802. he_writel(he_dev, 0x0, IRQ3_BASE);
  803. he_writel(he_dev, 0x0, IRQ3_HEAD);
  804. he_writel(he_dev, 0x0, IRQ3_CNTL);
  805. he_writel(he_dev, 0x0, IRQ3_DATA);
  806. /* 2.9.3.2 interrupt queue mapping registers */
  807. he_writel(he_dev, 0x0, GRP_10_MAP);
  808. he_writel(he_dev, 0x0, GRP_32_MAP);
  809. he_writel(he_dev, 0x0, GRP_54_MAP);
  810. he_writel(he_dev, 0x0, GRP_76_MAP);
  811. if (request_irq(he_dev->pci_dev->irq, he_irq_handler, SA_INTERRUPT|SA_SHIRQ, DEV_LABEL, he_dev)) {
  812. hprintk("irq %d already in use\n", he_dev->pci_dev->irq);
  813. return -EINVAL;
  814. }
  815. he_dev->irq = he_dev->pci_dev->irq;
  816. return 0;
  817. }
  818. static int __init
  819. he_start(struct atm_dev *dev)
  820. {
  821. struct he_dev *he_dev;
  822. struct pci_dev *pci_dev;
  823. unsigned long membase;
  824. u16 command;
  825. u32 gen_cntl_0, host_cntl, lb_swap;
  826. u8 cache_size, timer;
  827. unsigned err;
  828. unsigned int status, reg;
  829. int i, group;
  830. he_dev = HE_DEV(dev);
  831. pci_dev = he_dev->pci_dev;
  832. membase = pci_resource_start(pci_dev, 0);
  833. HPRINTK("membase = 0x%lx irq = %d.\n", membase, pci_dev->irq);
  834. /*
  835. * pci bus controller initialization
  836. */
  837. /* 4.3 pci bus controller-specific initialization */
  838. if (pci_read_config_dword(pci_dev, GEN_CNTL_0, &gen_cntl_0) != 0) {
  839. hprintk("can't read GEN_CNTL_0\n");
  840. return -EINVAL;
  841. }
  842. gen_cntl_0 |= (MRL_ENB | MRM_ENB | IGNORE_TIMEOUT);
  843. if (pci_write_config_dword(pci_dev, GEN_CNTL_0, gen_cntl_0) != 0) {
  844. hprintk("can't write GEN_CNTL_0.\n");
  845. return -EINVAL;
  846. }
  847. if (pci_read_config_word(pci_dev, PCI_COMMAND, &command) != 0) {
  848. hprintk("can't read PCI_COMMAND.\n");
  849. return -EINVAL;
  850. }
  851. command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
  852. if (pci_write_config_word(pci_dev, PCI_COMMAND, command) != 0) {
  853. hprintk("can't enable memory.\n");
  854. return -EINVAL;
  855. }
  856. if (pci_read_config_byte(pci_dev, PCI_CACHE_LINE_SIZE, &cache_size)) {
  857. hprintk("can't read cache line size?\n");
  858. return -EINVAL;
  859. }
  860. if (cache_size < 16) {
  861. cache_size = 16;
  862. if (pci_write_config_byte(pci_dev, PCI_CACHE_LINE_SIZE, cache_size))
  863. hprintk("can't set cache line size to %d\n", cache_size);
  864. }
  865. if (pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &timer)) {
  866. hprintk("can't read latency timer?\n");
  867. return -EINVAL;
  868. }
  869. /* from table 3.9
  870. *
  871. * LAT_TIMER = 1 + AVG_LAT + BURST_SIZE/BUS_SIZE
  872. *
  873. * AVG_LAT: The average first data read/write latency [maximum 16 clock cycles]
  874. * BURST_SIZE: 1536 bytes (read) for 622, 768 bytes (read) for 155 [192 clock cycles]
  875. *
  876. */
  877. #define LAT_TIMER 209
  878. if (timer < LAT_TIMER) {
  879. HPRINTK("latency timer was %d, setting to %d\n", timer, LAT_TIMER);
  880. timer = LAT_TIMER;
  881. if (pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, timer))
  882. hprintk("can't set latency timer to %d\n", timer);
  883. }
  884. if (!(he_dev->membase = ioremap(membase, HE_REGMAP_SIZE))) {
  885. hprintk("can't set up page mapping\n");
  886. return -EINVAL;
  887. }
  888. /* 4.4 card reset */
  889. he_writel(he_dev, 0x0, RESET_CNTL);
  890. he_writel(he_dev, 0xff, RESET_CNTL);
  891. udelay(16*1000); /* 16 ms */
  892. status = he_readl(he_dev, RESET_CNTL);
  893. if ((status & BOARD_RST_STATUS) == 0) {
  894. hprintk("reset failed\n");
  895. return -EINVAL;
  896. }
  897. /* 4.5 set bus width */
  898. host_cntl = he_readl(he_dev, HOST_CNTL);
  899. if (host_cntl & PCI_BUS_SIZE64)
  900. gen_cntl_0 |= ENBL_64;
  901. else
  902. gen_cntl_0 &= ~ENBL_64;
  903. if (disable64 == 1) {
  904. hprintk("disabling 64-bit pci bus transfers\n");
  905. gen_cntl_0 &= ~ENBL_64;
  906. }
  907. if (gen_cntl_0 & ENBL_64)
  908. hprintk("64-bit transfers enabled\n");
  909. pci_write_config_dword(pci_dev, GEN_CNTL_0, gen_cntl_0);
  910. /* 4.7 read prom contents */
  911. for (i = 0; i < PROD_ID_LEN; ++i)
  912. he_dev->prod_id[i] = read_prom_byte(he_dev, PROD_ID + i);
  913. he_dev->media = read_prom_byte(he_dev, MEDIA);
  914. for (i = 0; i < 6; ++i)
  915. dev->esi[i] = read_prom_byte(he_dev, MAC_ADDR + i);
  916. hprintk("%s%s, %x:%x:%x:%x:%x:%x\n",
  917. he_dev->prod_id,
  918. he_dev->media & 0x40 ? "SM" : "MM",
  919. dev->esi[0],
  920. dev->esi[1],
  921. dev->esi[2],
  922. dev->esi[3],
  923. dev->esi[4],
  924. dev->esi[5]);
  925. he_dev->atm_dev->link_rate = he_is622(he_dev) ?
  926. ATM_OC12_PCR : ATM_OC3_PCR;
  927. /* 4.6 set host endianess */
  928. lb_swap = he_readl(he_dev, LB_SWAP);
  929. if (he_is622(he_dev))
  930. lb_swap &= ~XFER_SIZE; /* 4 cells */
  931. else
  932. lb_swap |= XFER_SIZE; /* 8 cells */
  933. #ifdef __BIG_ENDIAN
  934. lb_swap |= DESC_WR_SWAP | INTR_SWAP | BIG_ENDIAN_HOST;
  935. #else
  936. lb_swap &= ~(DESC_WR_SWAP | INTR_SWAP | BIG_ENDIAN_HOST |
  937. DATA_WR_SWAP | DATA_RD_SWAP | DESC_RD_SWAP);
  938. #endif /* __BIG_ENDIAN */
  939. he_writel(he_dev, lb_swap, LB_SWAP);
  940. /* 4.8 sdram controller initialization */
  941. he_writel(he_dev, he_is622(he_dev) ? LB_64_ENB : 0x0, SDRAM_CTL);
  942. /* 4.9 initialize rnum value */
  943. lb_swap |= SWAP_RNUM_MAX(0xf);
  944. he_writel(he_dev, lb_swap, LB_SWAP);
  945. /* 4.10 initialize the interrupt queues */
  946. if ((err = he_init_irq(he_dev)) != 0)
  947. return err;
  948. #ifdef USE_TASKLET
  949. tasklet_init(&he_dev->tasklet, he_tasklet, (unsigned long) he_dev);
  950. #endif
  951. spin_lock_init(&he_dev->global_lock);
  952. /* 4.11 enable pci bus controller state machines */
  953. host_cntl |= (OUTFF_ENB | CMDFF_ENB |
  954. QUICK_RD_RETRY | QUICK_WR_RETRY | PERR_INT_ENB);
  955. he_writel(he_dev, host_cntl, HOST_CNTL);
  956. gen_cntl_0 |= INT_PROC_ENBL|INIT_ENB;
  957. pci_write_config_dword(pci_dev, GEN_CNTL_0, gen_cntl_0);
  958. /*
  959. * atm network controller initialization
  960. */
  961. /* 5.1.1 generic configuration state */
  962. /*
  963. * local (cell) buffer memory map
  964. *
  965. * HE155 HE622
  966. *
  967. * 0 ____________1023 bytes 0 _______________________2047 bytes
  968. * | | | | |
  969. * | utility | | rx0 | |
  970. * 5|____________| 255|___________________| u |
  971. * 6| | 256| | t |
  972. * | | | | i |
  973. * | rx0 | row | tx | l |
  974. * | | | | i |
  975. * | | 767|___________________| t |
  976. * 517|____________| 768| | y |
  977. * row 518| | | rx1 | |
  978. * | | 1023|___________________|___|
  979. * | |
  980. * | tx |
  981. * | |
  982. * | |
  983. * 1535|____________|
  984. * 1536| |
  985. * | rx1 |
  986. * 2047|____________|
  987. *
  988. */
  989. /* total 4096 connections */
  990. he_dev->vcibits = CONFIG_DEFAULT_VCIBITS;
  991. he_dev->vpibits = CONFIG_DEFAULT_VPIBITS;
  992. if (nvpibits != -1 && nvcibits != -1 && nvpibits+nvcibits != HE_MAXCIDBITS) {
  993. hprintk("nvpibits + nvcibits != %d\n", HE_MAXCIDBITS);
  994. return -ENODEV;
  995. }
  996. if (nvpibits != -1) {
  997. he_dev->vpibits = nvpibits;
  998. he_dev->vcibits = HE_MAXCIDBITS - nvpibits;
  999. }
  1000. if (nvcibits != -1) {
  1001. he_dev->vcibits = nvcibits;
  1002. he_dev->vpibits = HE_MAXCIDBITS - nvcibits;
  1003. }
  1004. if (he_is622(he_dev)) {
  1005. he_dev->cells_per_row = 40;
  1006. he_dev->bytes_per_row = 2048;
  1007. he_dev->r0_numrows = 256;
  1008. he_dev->tx_numrows = 512;
  1009. he_dev->r1_numrows = 256;
  1010. he_dev->r0_startrow = 0;
  1011. he_dev->tx_startrow = 256;
  1012. he_dev->r1_startrow = 768;
  1013. } else {
  1014. he_dev->cells_per_row = 20;
  1015. he_dev->bytes_per_row = 1024;
  1016. he_dev->r0_numrows = 512;
  1017. he_dev->tx_numrows = 1018;
  1018. he_dev->r1_numrows = 512;
  1019. he_dev->r0_startrow = 6;
  1020. he_dev->tx_startrow = 518;
  1021. he_dev->r1_startrow = 1536;
  1022. }
  1023. he_dev->cells_per_lbuf = 4;
  1024. he_dev->buffer_limit = 4;
  1025. he_dev->r0_numbuffs = he_dev->r0_numrows *
  1026. he_dev->cells_per_row / he_dev->cells_per_lbuf;
  1027. if (he_dev->r0_numbuffs > 2560)
  1028. he_dev->r0_numbuffs = 2560;
  1029. he_dev->r1_numbuffs = he_dev->r1_numrows *
  1030. he_dev->cells_per_row / he_dev->cells_per_lbuf;
  1031. if (he_dev->r1_numbuffs > 2560)
  1032. he_dev->r1_numbuffs = 2560;
  1033. he_dev->tx_numbuffs = he_dev->tx_numrows *
  1034. he_dev->cells_per_row / he_dev->cells_per_lbuf;
  1035. if (he_dev->tx_numbuffs > 5120)
  1036. he_dev->tx_numbuffs = 5120;
  1037. /* 5.1.2 configure hardware dependent registers */
  1038. he_writel(he_dev,
  1039. SLICE_X(0x2) | ARB_RNUM_MAX(0xf) | TH_PRTY(0x3) |
  1040. RH_PRTY(0x3) | TL_PRTY(0x2) | RL_PRTY(0x1) |
  1041. (he_is622(he_dev) ? BUS_MULTI(0x28) : BUS_MULTI(0x46)) |
  1042. (he_is622(he_dev) ? NET_PREF(0x50) : NET_PREF(0x8c)),
  1043. LBARB);
  1044. he_writel(he_dev, BANK_ON |
  1045. (he_is622(he_dev) ? (REF_RATE(0x384) | WIDE_DATA) : REF_RATE(0x150)),
  1046. SDRAMCON);
  1047. he_writel(he_dev,
  1048. (he_is622(he_dev) ? RM_BANK_WAIT(1) : RM_BANK_WAIT(0)) |
  1049. RM_RW_WAIT(1), RCMCONFIG);
  1050. he_writel(he_dev,
  1051. (he_is622(he_dev) ? TM_BANK_WAIT(2) : TM_BANK_WAIT(1)) |
  1052. TM_RW_WAIT(1), TCMCONFIG);
  1053. he_writel(he_dev, he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD, LB_CONFIG);
  1054. he_writel(he_dev,
  1055. (he_is622(he_dev) ? UT_RD_DELAY(8) : UT_RD_DELAY(0)) |
  1056. (he_is622(he_dev) ? RC_UT_MODE(0) : RC_UT_MODE(1)) |
  1057. RX_VALVP(he_dev->vpibits) |
  1058. RX_VALVC(he_dev->vcibits), RC_CONFIG);
  1059. he_writel(he_dev, DRF_THRESH(0x20) |
  1060. (he_is622(he_dev) ? TX_UT_MODE(0) : TX_UT_MODE(1)) |
  1061. TX_VCI_MASK(he_dev->vcibits) |
  1062. LBFREE_CNT(he_dev->tx_numbuffs), TX_CONFIG);
  1063. he_writel(he_dev, 0x0, TXAAL5_PROTO);
  1064. he_writel(he_dev, PHY_INT_ENB |
  1065. (he_is622(he_dev) ? PTMR_PRE(67 - 1) : PTMR_PRE(50 - 1)),
  1066. RH_CONFIG);
  1067. /* 5.1.3 initialize connection memory */
  1068. for (i = 0; i < TCM_MEM_SIZE; ++i)
  1069. he_writel_tcm(he_dev, 0, i);
  1070. for (i = 0; i < RCM_MEM_SIZE; ++i)
  1071. he_writel_rcm(he_dev, 0, i);
  1072. /*
  1073. * transmit connection memory map
  1074. *
  1075. * tx memory
  1076. * 0x0 ___________________
  1077. * | |
  1078. * | |
  1079. * | TSRa |
  1080. * | |
  1081. * | |
  1082. * 0x8000|___________________|
  1083. * | |
  1084. * | TSRb |
  1085. * 0xc000|___________________|
  1086. * | |
  1087. * | TSRc |
  1088. * 0xe000|___________________|
  1089. * | TSRd |
  1090. * 0xf000|___________________|
  1091. * | tmABR |
  1092. * 0x10000|___________________|
  1093. * | |
  1094. * | tmTPD |
  1095. * |___________________|
  1096. * | |
  1097. * ....
  1098. * 0x1ffff|___________________|
  1099. *
  1100. *
  1101. */
  1102. he_writel(he_dev, CONFIG_TSRB, TSRB_BA);
  1103. he_writel(he_dev, CONFIG_TSRC, TSRC_BA);
  1104. he_writel(he_dev, CONFIG_TSRD, TSRD_BA);
  1105. he_writel(he_dev, CONFIG_TMABR, TMABR_BA);
  1106. he_writel(he_dev, CONFIG_TPDBA, TPD_BA);
  1107. /*
  1108. * receive connection memory map
  1109. *
  1110. * 0x0 ___________________
  1111. * | |
  1112. * | |
  1113. * | RSRa |
  1114. * | |
  1115. * | |
  1116. * 0x8000|___________________|
  1117. * | |
  1118. * | rx0/1 |
  1119. * | LBM | link lists of local
  1120. * | tx | buffer memory
  1121. * | |
  1122. * 0xd000|___________________|
  1123. * | |
  1124. * | rmABR |
  1125. * 0xe000|___________________|
  1126. * | |
  1127. * | RSRb |
  1128. * |___________________|
  1129. * | |
  1130. * ....
  1131. * 0xffff|___________________|
  1132. */
  1133. he_writel(he_dev, 0x08000, RCMLBM_BA);
  1134. he_writel(he_dev, 0x0e000, RCMRSRB_BA);
  1135. he_writel(he_dev, 0x0d800, RCMABR_BA);
  1136. /* 5.1.4 initialize local buffer free pools linked lists */
  1137. he_init_rx_lbfp0(he_dev);
  1138. he_init_rx_lbfp1(he_dev);
  1139. he_writel(he_dev, 0x0, RLBC_H);
  1140. he_writel(he_dev, 0x0, RLBC_T);
  1141. he_writel(he_dev, 0x0, RLBC_H2);
  1142. he_writel(he_dev, 512, RXTHRSH); /* 10% of r0+r1 buffers */
  1143. he_writel(he_dev, 256, LITHRSH); /* 5% of r0+r1 buffers */
  1144. he_init_tx_lbfp(he_dev);
  1145. he_writel(he_dev, he_is622(he_dev) ? 0x104780 : 0x800, UBUFF_BA);
  1146. /* 5.1.5 initialize intermediate receive queues */
  1147. if (he_is622(he_dev)) {
  1148. he_writel(he_dev, 0x000f, G0_INMQ_S);
  1149. he_writel(he_dev, 0x200f, G0_INMQ_L);
  1150. he_writel(he_dev, 0x001f, G1_INMQ_S);
  1151. he_writel(he_dev, 0x201f, G1_INMQ_L);
  1152. he_writel(he_dev, 0x002f, G2_INMQ_S);
  1153. he_writel(he_dev, 0x202f, G2_INMQ_L);
  1154. he_writel(he_dev, 0x003f, G3_INMQ_S);
  1155. he_writel(he_dev, 0x203f, G3_INMQ_L);
  1156. he_writel(he_dev, 0x004f, G4_INMQ_S);
  1157. he_writel(he_dev, 0x204f, G4_INMQ_L);
  1158. he_writel(he_dev, 0x005f, G5_INMQ_S);
  1159. he_writel(he_dev, 0x205f, G5_INMQ_L);
  1160. he_writel(he_dev, 0x006f, G6_INMQ_S);
  1161. he_writel(he_dev, 0x206f, G6_INMQ_L);
  1162. he_writel(he_dev, 0x007f, G7_INMQ_S);
  1163. he_writel(he_dev, 0x207f, G7_INMQ_L);
  1164. } else {
  1165. he_writel(he_dev, 0x0000, G0_INMQ_S);
  1166. he_writel(he_dev, 0x0008, G0_INMQ_L);
  1167. he_writel(he_dev, 0x0001, G1_INMQ_S);
  1168. he_writel(he_dev, 0x0009, G1_INMQ_L);
  1169. he_writel(he_dev, 0x0002, G2_INMQ_S);
  1170. he_writel(he_dev, 0x000a, G2_INMQ_L);
  1171. he_writel(he_dev, 0x0003, G3_INMQ_S);
  1172. he_writel(he_dev, 0x000b, G3_INMQ_L);
  1173. he_writel(he_dev, 0x0004, G4_INMQ_S);
  1174. he_writel(he_dev, 0x000c, G4_INMQ_L);
  1175. he_writel(he_dev, 0x0005, G5_INMQ_S);
  1176. he_writel(he_dev, 0x000d, G5_INMQ_L);
  1177. he_writel(he_dev, 0x0006, G6_INMQ_S);
  1178. he_writel(he_dev, 0x000e, G6_INMQ_L);
  1179. he_writel(he_dev, 0x0007, G7_INMQ_S);
  1180. he_writel(he_dev, 0x000f, G7_INMQ_L);
  1181. }
  1182. /* 5.1.6 application tunable parameters */
  1183. he_writel(he_dev, 0x0, MCC);
  1184. he_writel(he_dev, 0x0, OEC);
  1185. he_writel(he_dev, 0x0, DCC);
  1186. he_writel(he_dev, 0x0, CEC);
  1187. /* 5.1.7 cs block initialization */
  1188. he_init_cs_block(he_dev);
  1189. /* 5.1.8 cs block connection memory initialization */
  1190. if (he_init_cs_block_rcm(he_dev) < 0)
  1191. return -ENOMEM;
  1192. /* 5.1.10 initialize host structures */
  1193. he_init_tpdrq(he_dev);
  1194. #ifdef USE_TPD_POOL
  1195. he_dev->tpd_pool = pci_pool_create("tpd", he_dev->pci_dev,
  1196. sizeof(struct he_tpd), TPD_ALIGNMENT, 0);
  1197. if (he_dev->tpd_pool == NULL) {
  1198. hprintk("unable to create tpd pci_pool\n");
  1199. return -ENOMEM;
  1200. }
  1201. INIT_LIST_HEAD(&he_dev->outstanding_tpds);
  1202. #else
  1203. he_dev->tpd_base = (void *) pci_alloc_consistent(he_dev->pci_dev,
  1204. CONFIG_NUMTPDS * sizeof(struct he_tpd), &he_dev->tpd_base_phys);
  1205. if (!he_dev->tpd_base)
  1206. return -ENOMEM;
  1207. for (i = 0; i < CONFIG_NUMTPDS; ++i) {
  1208. he_dev->tpd_base[i].status = (i << TPD_ADDR_SHIFT);
  1209. he_dev->tpd_base[i].inuse = 0;
  1210. }
  1211. he_dev->tpd_head = he_dev->tpd_base;
  1212. he_dev->tpd_end = &he_dev->tpd_base[CONFIG_NUMTPDS - 1];
  1213. #endif
  1214. if (he_init_group(he_dev, 0) != 0)
  1215. return -ENOMEM;
  1216. for (group = 1; group < HE_NUM_GROUPS; ++group) {
  1217. he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32));
  1218. he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32));
  1219. he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32));
  1220. he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
  1221. G0_RBPS_BS + (group * 32));
  1222. he_writel(he_dev, 0x0, G0_RBPL_S + (group * 32));
  1223. he_writel(he_dev, 0x0, G0_RBPL_T + (group * 32));
  1224. he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
  1225. G0_RBPL_QI + (group * 32));
  1226. he_writel(he_dev, 0x0, G0_RBPL_BS + (group * 32));
  1227. he_writel(he_dev, 0x0, G0_RBRQ_ST + (group * 16));
  1228. he_writel(he_dev, 0x0, G0_RBRQ_H + (group * 16));
  1229. he_writel(he_dev, RBRQ_THRESH(0x1) | RBRQ_SIZE(0x0),
  1230. G0_RBRQ_Q + (group * 16));
  1231. he_writel(he_dev, 0x0, G0_RBRQ_I + (group * 16));
  1232. he_writel(he_dev, 0x0, G0_TBRQ_B_T + (group * 16));
  1233. he_writel(he_dev, 0x0, G0_TBRQ_H + (group * 16));
  1234. he_writel(he_dev, TBRQ_THRESH(0x1),
  1235. G0_TBRQ_THRESH + (group * 16));
  1236. he_writel(he_dev, 0x0, G0_TBRQ_S + (group * 16));
  1237. }
  1238. /* host status page */
  1239. he_dev->hsp = pci_alloc_consistent(he_dev->pci_dev,
  1240. sizeof(struct he_hsp), &he_dev->hsp_phys);
  1241. if (he_dev->hsp == NULL) {
  1242. hprintk("failed to allocate host status page\n");
  1243. return -ENOMEM;
  1244. }
  1245. memset(he_dev->hsp, 0, sizeof(struct he_hsp));
  1246. he_writel(he_dev, he_dev->hsp_phys, HSP_BA);
  1247. /* initialize framer */
  1248. #ifdef CONFIG_ATM_HE_USE_SUNI
  1249. suni_init(he_dev->atm_dev);
  1250. if (he_dev->atm_dev->phy && he_dev->atm_dev->phy->start)
  1251. he_dev->atm_dev->phy->start(he_dev->atm_dev);
  1252. #endif /* CONFIG_ATM_HE_USE_SUNI */
  1253. if (sdh) {
  1254. /* this really should be in suni.c but for now... */
  1255. int val;
  1256. val = he_phy_get(he_dev->atm_dev, SUNI_TPOP_APM);
  1257. val = (val & ~SUNI_TPOP_APM_S) | (SUNI_TPOP_S_SDH << SUNI_TPOP_APM_S_SHIFT);
  1258. he_phy_put(he_dev->atm_dev, val, SUNI_TPOP_APM);
  1259. }
  1260. /* 5.1.12 enable transmit and receive */
  1261. reg = he_readl_mbox(he_dev, CS_ERCTL0);
  1262. reg |= TX_ENABLE|ER_ENABLE;
  1263. he_writel_mbox(he_dev, reg, CS_ERCTL0);
  1264. reg = he_readl(he_dev, RC_CONFIG);
  1265. reg |= RX_ENABLE;
  1266. he_writel(he_dev, reg, RC_CONFIG);
  1267. for (i = 0; i < HE_NUM_CS_STPER; ++i) {
  1268. he_dev->cs_stper[i].inuse = 0;
  1269. he_dev->cs_stper[i].pcr = -1;
  1270. }
  1271. he_dev->total_bw = 0;
  1272. /* atm linux initialization */
  1273. he_dev->atm_dev->ci_range.vpi_bits = he_dev->vpibits;
  1274. he_dev->atm_dev->ci_range.vci_bits = he_dev->vcibits;
  1275. he_dev->irq_peak = 0;
  1276. he_dev->rbrq_peak = 0;
  1277. he_dev->rbpl_peak = 0;
  1278. he_dev->tbrq_peak = 0;
  1279. HPRINTK("hell bent for leather!\n");
  1280. return 0;
  1281. }
  1282. static void
  1283. he_stop(struct he_dev *he_dev)
  1284. {
  1285. u16 command;
  1286. u32 gen_cntl_0, reg;
  1287. struct pci_dev *pci_dev;
  1288. pci_dev = he_dev->pci_dev;
  1289. /* disable interrupts */
  1290. if (he_dev->membase) {
  1291. pci_read_config_dword(pci_dev, GEN_CNTL_0, &gen_cntl_0);
  1292. gen_cntl_0 &= ~(INT_PROC_ENBL | INIT_ENB);
  1293. pci_write_config_dword(pci_dev, GEN_CNTL_0, gen_cntl_0);
  1294. #ifdef USE_TASKLET
  1295. tasklet_disable(&he_dev->tasklet);
  1296. #endif
  1297. /* disable recv and transmit */
  1298. reg = he_readl_mbox(he_dev, CS_ERCTL0);
  1299. reg &= ~(TX_ENABLE|ER_ENABLE);
  1300. he_writel_mbox(he_dev, reg, CS_ERCTL0);
  1301. reg = he_readl(he_dev, RC_CONFIG);
  1302. reg &= ~(RX_ENABLE);
  1303. he_writel(he_dev, reg, RC_CONFIG);
  1304. }
  1305. #ifdef CONFIG_ATM_HE_USE_SUNI
  1306. if (he_dev->atm_dev->phy && he_dev->atm_dev->phy->stop)
  1307. he_dev->atm_dev->phy->stop(he_dev->atm_dev);
  1308. #endif /* CONFIG_ATM_HE_USE_SUNI */
  1309. if (he_dev->irq)
  1310. free_irq(he_dev->irq, he_dev);
  1311. if (he_dev->irq_base)
  1312. pci_free_consistent(he_dev->pci_dev, (CONFIG_IRQ_SIZE+1)
  1313. * sizeof(struct he_irq), he_dev->irq_base, he_dev->irq_phys);
  1314. if (he_dev->hsp)
  1315. pci_free_consistent(he_dev->pci_dev, sizeof(struct he_hsp),
  1316. he_dev->hsp, he_dev->hsp_phys);
  1317. if (he_dev->rbpl_base) {
  1318. #ifdef USE_RBPL_POOL
  1319. for (i = 0; i < CONFIG_RBPL_SIZE; ++i) {
  1320. void *cpuaddr = he_dev->rbpl_virt[i].virt;
  1321. dma_addr_t dma_handle = he_dev->rbpl_base[i].phys;
  1322. pci_pool_free(he_dev->rbpl_pool, cpuaddr, dma_handle);
  1323. }
  1324. #else
  1325. pci_free_consistent(he_dev->pci_dev, CONFIG_RBPL_SIZE
  1326. * CONFIG_RBPL_BUFSIZE, he_dev->rbpl_pages, he_dev->rbpl_pages_phys);
  1327. #endif
  1328. pci_free_consistent(he_dev->pci_dev, CONFIG_RBPL_SIZE
  1329. * sizeof(struct he_rbp), he_dev->rbpl_base, he_dev->rbpl_phys);
  1330. }
  1331. #ifdef USE_RBPL_POOL
  1332. if (he_dev->rbpl_pool)
  1333. pci_pool_destroy(he_dev->rbpl_pool);
  1334. #endif
  1335. #ifdef USE_RBPS
  1336. if (he_dev->rbps_base) {
  1337. #ifdef USE_RBPS_POOL
  1338. for (i = 0; i < CONFIG_RBPS_SIZE; ++i) {
  1339. void *cpuaddr = he_dev->rbps_virt[i].virt;
  1340. dma_addr_t dma_handle = he_dev->rbps_base[i].phys;
  1341. pci_pool_free(he_dev->rbps_pool, cpuaddr, dma_handle);
  1342. }
  1343. #else
  1344. pci_free_consistent(he_dev->pci_dev, CONFIG_RBPS_SIZE
  1345. * CONFIG_RBPS_BUFSIZE, he_dev->rbps_pages, he_dev->rbps_pages_phys);
  1346. #endif
  1347. pci_free_consistent(he_dev->pci_dev, CONFIG_RBPS_SIZE
  1348. * sizeof(struct he_rbp), he_dev->rbps_base, he_dev->rbps_phys);
  1349. }
  1350. #ifdef USE_RBPS_POOL
  1351. if (he_dev->rbps_pool)
  1352. pci_pool_destroy(he_dev->rbps_pool);
  1353. #endif
  1354. #endif /* USE_RBPS */
  1355. if (he_dev->rbrq_base)
  1356. pci_free_consistent(he_dev->pci_dev, CONFIG_RBRQ_SIZE * sizeof(struct he_rbrq),
  1357. he_dev->rbrq_base, he_dev->rbrq_phys);
  1358. if (he_dev->tbrq_base)
  1359. pci_free_consistent(he_dev->pci_dev, CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq),
  1360. he_dev->tbrq_base, he_dev->tbrq_phys);
  1361. if (he_dev->tpdrq_base)
  1362. pci_free_consistent(he_dev->pci_dev, CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq),
  1363. he_dev->tpdrq_base, he_dev->tpdrq_phys);
  1364. #ifdef USE_TPD_POOL
  1365. if (he_dev->tpd_pool)
  1366. pci_pool_destroy(he_dev->tpd_pool);
  1367. #else
  1368. if (he_dev->tpd_base)
  1369. pci_free_consistent(he_dev->pci_dev, CONFIG_NUMTPDS * sizeof(struct he_tpd),
  1370. he_dev->tpd_base, he_dev->tpd_base_phys);
  1371. #endif
  1372. if (he_dev->pci_dev) {
  1373. pci_read_config_word(he_dev->pci_dev, PCI_COMMAND, &command);
  1374. command &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  1375. pci_write_config_word(he_dev->pci_dev, PCI_COMMAND, command);
  1376. }
  1377. if (he_dev->membase)
  1378. iounmap(he_dev->membase);
  1379. }
  1380. static struct he_tpd *
  1381. __alloc_tpd(struct he_dev *he_dev)
  1382. {
  1383. #ifdef USE_TPD_POOL
  1384. struct he_tpd *tpd;
  1385. dma_addr_t dma_handle;
  1386. tpd = pci_pool_alloc(he_dev->tpd_pool, SLAB_ATOMIC|SLAB_DMA, &dma_handle);
  1387. if (tpd == NULL)
  1388. return NULL;
  1389. tpd->status = TPD_ADDR(dma_handle);
  1390. tpd->reserved = 0;
  1391. tpd->iovec[0].addr = 0; tpd->iovec[0].len = 0;
  1392. tpd->iovec[1].addr = 0; tpd->iovec[1].len = 0;
  1393. tpd->iovec[2].addr = 0; tpd->iovec[2].len = 0;
  1394. return tpd;
  1395. #else
  1396. int i;
  1397. for (i = 0; i < CONFIG_NUMTPDS; ++i) {
  1398. ++he_dev->tpd_head;
  1399. if (he_dev->tpd_head > he_dev->tpd_end) {
  1400. he_dev->tpd_head = he_dev->tpd_base;
  1401. }
  1402. if (!he_dev->tpd_head->inuse) {
  1403. he_dev->tpd_head->inuse = 1;
  1404. he_dev->tpd_head->status &= TPD_MASK;
  1405. he_dev->tpd_head->iovec[0].addr = 0; he_dev->tpd_head->iovec[0].len = 0;
  1406. he_dev->tpd_head->iovec[1].addr = 0; he_dev->tpd_head->iovec[1].len = 0;
  1407. he_dev->tpd_head->iovec[2].addr = 0; he_dev->tpd_head->iovec[2].len = 0;
  1408. return he_dev->tpd_head;
  1409. }
  1410. }
  1411. hprintk("out of tpds -- increase CONFIG_NUMTPDS (%d)\n", CONFIG_NUMTPDS);
  1412. return NULL;
  1413. #endif
  1414. }
  1415. #define AAL5_LEN(buf,len) \
  1416. ((((unsigned char *)(buf))[(len)-6] << 8) | \
  1417. (((unsigned char *)(buf))[(len)-5]))
  1418. /* 2.10.1.2 receive
  1419. *
  1420. * aal5 packets can optionally return the tcp checksum in the lower
  1421. * 16 bits of the crc (RSR0_TCP_CKSUM)
  1422. */
  1423. #define TCP_CKSUM(buf,len) \
  1424. ((((unsigned char *)(buf))[(len)-2] << 8) | \
  1425. (((unsigned char *)(buf))[(len-1)]))
  1426. static int
  1427. he_service_rbrq(struct he_dev *he_dev, int group)
  1428. {
  1429. struct he_rbrq *rbrq_tail = (struct he_rbrq *)
  1430. ((unsigned long)he_dev->rbrq_base |
  1431. he_dev->hsp->group[group].rbrq_tail);
  1432. struct he_rbp *rbp = NULL;
  1433. unsigned cid, lastcid = -1;
  1434. unsigned buf_len = 0;
  1435. struct sk_buff *skb;
  1436. struct atm_vcc *vcc = NULL;
  1437. struct he_vcc *he_vcc;
  1438. struct he_iovec *iov;
  1439. int pdus_assembled = 0;
  1440. int updated = 0;
  1441. read_lock(&vcc_sklist_lock);
  1442. while (he_dev->rbrq_head != rbrq_tail) {
  1443. ++updated;
  1444. HPRINTK("%p rbrq%d 0x%x len=%d cid=0x%x %s%s%s%s%s%s\n",
  1445. he_dev->rbrq_head, group,
  1446. RBRQ_ADDR(he_dev->rbrq_head),
  1447. RBRQ_BUFLEN(he_dev->rbrq_head),
  1448. RBRQ_CID(he_dev->rbrq_head),
  1449. RBRQ_CRC_ERR(he_dev->rbrq_head) ? " CRC_ERR" : "",
  1450. RBRQ_LEN_ERR(he_dev->rbrq_head) ? " LEN_ERR" : "",
  1451. RBRQ_END_PDU(he_dev->rbrq_head) ? " END_PDU" : "",
  1452. RBRQ_AAL5_PROT(he_dev->rbrq_head) ? " AAL5_PROT" : "",
  1453. RBRQ_CON_CLOSED(he_dev->rbrq_head) ? " CON_CLOSED" : "",
  1454. RBRQ_HBUF_ERR(he_dev->rbrq_head) ? " HBUF_ERR" : "");
  1455. #ifdef USE_RBPS
  1456. if (RBRQ_ADDR(he_dev->rbrq_head) & RBP_SMALLBUF)
  1457. rbp = &he_dev->rbps_base[RBP_INDEX(RBRQ_ADDR(he_dev->rbrq_head))];
  1458. else
  1459. #endif
  1460. rbp = &he_dev->rbpl_base[RBP_INDEX(RBRQ_ADDR(he_dev->rbrq_head))];
  1461. buf_len = RBRQ_BUFLEN(he_dev->rbrq_head) * 4;
  1462. cid = RBRQ_CID(he_dev->rbrq_head);
  1463. if (cid != lastcid)
  1464. vcc = __find_vcc(he_dev, cid);
  1465. lastcid = cid;
  1466. if (vcc == NULL) {
  1467. hprintk("vcc == NULL (cid 0x%x)\n", cid);
  1468. if (!RBRQ_HBUF_ERR(he_dev->rbrq_head))
  1469. rbp->status &= ~RBP_LOANED;
  1470. goto next_rbrq_entry;
  1471. }
  1472. he_vcc = HE_VCC(vcc);
  1473. if (he_vcc == NULL) {
  1474. hprintk("he_vcc == NULL (cid 0x%x)\n", cid);
  1475. if (!RBRQ_HBUF_ERR(he_dev->rbrq_head))
  1476. rbp->status &= ~RBP_LOANED;
  1477. goto next_rbrq_entry;
  1478. }
  1479. if (RBRQ_HBUF_ERR(he_dev->rbrq_head)) {
  1480. hprintk("HBUF_ERR! (cid 0x%x)\n", cid);
  1481. atomic_inc(&vcc->stats->rx_drop);
  1482. goto return_host_buffers;
  1483. }
  1484. he_vcc->iov_tail->iov_base = RBRQ_ADDR(he_dev->rbrq_head);
  1485. he_vcc->iov_tail->iov_len = buf_len;
  1486. he_vcc->pdu_len += buf_len;
  1487. ++he_vcc->iov_tail;
  1488. if (RBRQ_CON_CLOSED(he_dev->rbrq_head)) {
  1489. lastcid = -1;
  1490. HPRINTK("wake_up rx_waitq (cid 0x%x)\n", cid);
  1491. wake_up(&he_vcc->rx_waitq);
  1492. goto return_host_buffers;
  1493. }
  1494. #ifdef notdef
  1495. if ((he_vcc->iov_tail - he_vcc->iov_head) > HE_MAXIOV) {
  1496. hprintk("iovec full! cid 0x%x\n", cid);
  1497. goto return_host_buffers;
  1498. }
  1499. #endif
  1500. if (!RBRQ_END_PDU(he_dev->rbrq_head))
  1501. goto next_rbrq_entry;
  1502. if (RBRQ_LEN_ERR(he_dev->rbrq_head)
  1503. || RBRQ_CRC_ERR(he_dev->rbrq_head)) {
  1504. HPRINTK("%s%s (%d.%d)\n",
  1505. RBRQ_CRC_ERR(he_dev->rbrq_head)
  1506. ? "CRC_ERR " : "",
  1507. RBRQ_LEN_ERR(he_dev->rbrq_head)
  1508. ? "LEN_ERR" : "",
  1509. vcc->vpi, vcc->vci);
  1510. atomic_inc(&vcc->stats->rx_err);
  1511. goto return_host_buffers;
  1512. }
  1513. skb = atm_alloc_charge(vcc, he_vcc->pdu_len + rx_skb_reserve,
  1514. GFP_ATOMIC);
  1515. if (!skb) {
  1516. HPRINTK("charge failed (%d.%d)\n", vcc->vpi, vcc->vci);
  1517. goto return_host_buffers;
  1518. }
  1519. if (rx_skb_reserve > 0)
  1520. skb_reserve(skb, rx_skb_reserve);
  1521. __net_timestamp(skb);
  1522. for (iov = he_vcc->iov_head;
  1523. iov < he_vcc->iov_tail; ++iov) {
  1524. #ifdef USE_RBPS
  1525. if (iov->iov_base & RBP_SMALLBUF)
  1526. memcpy(skb_put(skb, iov->iov_len),
  1527. he_dev->rbps_virt[RBP_INDEX(iov->iov_base)].virt, iov->iov_len);
  1528. else
  1529. #endif
  1530. memcpy(skb_put(skb, iov->iov_len),
  1531. he_dev->rbpl_virt[RBP_INDEX(iov->iov_base)].virt, iov->iov_len);
  1532. }
  1533. switch (vcc->qos.aal) {
  1534. case ATM_AAL0:
  1535. /* 2.10.1.5 raw cell receive */
  1536. skb->len = ATM_AAL0_SDU;
  1537. skb->tail = skb->data + skb->len;
  1538. break;
  1539. case ATM_AAL5:
  1540. /* 2.10.1.2 aal5 receive */
  1541. skb->len = AAL5_LEN(skb->data, he_vcc->pdu_len);
  1542. skb->tail = skb->data + skb->len;
  1543. #ifdef USE_CHECKSUM_HW
  1544. if (vcc->vpi == 0 && vcc->vci >= ATM_NOT_RSV_VCI) {
  1545. skb->ip_summed = CHECKSUM_HW;
  1546. skb->csum = TCP_CKSUM(skb->data,
  1547. he_vcc->pdu_len);
  1548. }
  1549. #endif
  1550. break;
  1551. }
  1552. #ifdef should_never_happen
  1553. if (skb->len > vcc->qos.rxtp.max_sdu)
  1554. hprintk("pdu_len (%d) > vcc->qos.rxtp.max_sdu (%d)! cid 0x%x\n", skb->len, vcc->qos.rxtp.max_sdu, cid);
  1555. #endif
  1556. #ifdef notdef
  1557. ATM_SKB(skb)->vcc = vcc;
  1558. #endif
  1559. vcc->push(vcc, skb);
  1560. atomic_inc(&vcc->stats->rx);
  1561. return_host_buffers:
  1562. ++pdus_assembled;
  1563. for (iov = he_vcc->iov_head;
  1564. iov < he_vcc->iov_tail; ++iov) {
  1565. #ifdef USE_RBPS
  1566. if (iov->iov_base & RBP_SMALLBUF)
  1567. rbp = &he_dev->rbps_base[RBP_INDEX(iov->iov_base)];
  1568. else
  1569. #endif
  1570. rbp = &he_dev->rbpl_base[RBP_INDEX(iov->iov_base)];
  1571. rbp->status &= ~RBP_LOANED;
  1572. }
  1573. he_vcc->iov_tail = he_vcc->iov_head;
  1574. he_vcc->pdu_len = 0;
  1575. next_rbrq_entry:
  1576. he_dev->rbrq_head = (struct he_rbrq *)
  1577. ((unsigned long) he_dev->rbrq_base |
  1578. RBRQ_MASK(++he_dev->rbrq_head));
  1579. }
  1580. read_unlock(&vcc_sklist_lock);
  1581. if (updated) {
  1582. if (updated > he_dev->rbrq_peak)
  1583. he_dev->rbrq_peak = updated;
  1584. he_writel(he_dev, RBRQ_MASK(he_dev->rbrq_head),
  1585. G0_RBRQ_H + (group * 16));
  1586. }
  1587. return pdus_assembled;
  1588. }
  1589. static void
  1590. he_service_tbrq(struct he_dev *he_dev, int group)
  1591. {
  1592. struct he_tbrq *tbrq_tail = (struct he_tbrq *)
  1593. ((unsigned long)he_dev->tbrq_base |
  1594. he_dev->hsp->group[group].tbrq_tail);
  1595. struct he_tpd *tpd;
  1596. int slot, updated = 0;
  1597. #ifdef USE_TPD_POOL
  1598. struct he_tpd *__tpd;
  1599. #endif
  1600. /* 2.1.6 transmit buffer return queue */
  1601. while (he_dev->tbrq_head != tbrq_tail) {
  1602. ++updated;
  1603. HPRINTK("tbrq%d 0x%x%s%s\n",
  1604. group,
  1605. TBRQ_TPD(he_dev->tbrq_head),
  1606. TBRQ_EOS(he_dev->tbrq_head) ? " EOS" : "",
  1607. TBRQ_MULTIPLE(he_dev->tbrq_head) ? " MULTIPLE" : "");
  1608. #ifdef USE_TPD_POOL
  1609. tpd = NULL;
  1610. list_for_each_entry(__tpd, &he_dev->outstanding_tpds, entry) {
  1611. if (TPD_ADDR(__tpd->status) == TBRQ_TPD(he_dev->tbrq_head)) {
  1612. tpd = __tpd;
  1613. list_del(&__tpd->entry);
  1614. break;
  1615. }
  1616. }
  1617. if (tpd == NULL) {
  1618. hprintk("unable to locate tpd for dma buffer %x\n",
  1619. TBRQ_TPD(he_dev->tbrq_head));
  1620. goto next_tbrq_entry;
  1621. }
  1622. #else
  1623. tpd = &he_dev->tpd_base[ TPD_INDEX(TBRQ_TPD(he_dev->tbrq_head)) ];
  1624. #endif
  1625. if (TBRQ_EOS(he_dev->tbrq_head)) {
  1626. HPRINTK("wake_up(tx_waitq) cid 0x%x\n",
  1627. he_mkcid(he_dev, tpd->vcc->vpi, tpd->vcc->vci));
  1628. if (tpd->vcc)
  1629. wake_up(&HE_VCC(tpd->vcc)->tx_waitq);
  1630. goto next_tbrq_entry;
  1631. }
  1632. for (slot = 0; slot < TPD_MAXIOV; ++slot) {
  1633. if (tpd->iovec[slot].addr)
  1634. pci_unmap_single(he_dev->pci_dev,
  1635. tpd->iovec[slot].addr,
  1636. tpd->iovec[slot].len & TPD_LEN_MASK,
  1637. PCI_DMA_TODEVICE);
  1638. if (tpd->iovec[slot].len & TPD_LST)
  1639. break;
  1640. }
  1641. if (tpd->skb) { /* && !TBRQ_MULTIPLE(he_dev->tbrq_head) */
  1642. if (tpd->vcc && tpd->vcc->pop)
  1643. tpd->vcc->pop(tpd->vcc, tpd->skb);
  1644. else
  1645. dev_kfree_skb_any(tpd->skb);
  1646. }
  1647. next_tbrq_entry:
  1648. #ifdef USE_TPD_POOL
  1649. if (tpd)
  1650. pci_pool_free(he_dev->tpd_pool, tpd, TPD_ADDR(tpd->status));
  1651. #else
  1652. tpd->inuse = 0;
  1653. #endif
  1654. he_dev->tbrq_head = (struct he_tbrq *)
  1655. ((unsigned long) he_dev->tbrq_base |
  1656. TBRQ_MASK(++he_dev->tbrq_head));
  1657. }
  1658. if (updated) {
  1659. if (updated > he_dev->tbrq_peak)
  1660. he_dev->tbrq_peak = updated;
  1661. he_writel(he_dev, TBRQ_MASK(he_dev->tbrq_head),
  1662. G0_TBRQ_H + (group * 16));
  1663. }
  1664. }
  1665. static void
  1666. he_service_rbpl(struct he_dev *he_dev, int group)
  1667. {
  1668. struct he_rbp *newtail;
  1669. struct he_rbp *rbpl_head;
  1670. int moved = 0;
  1671. rbpl_head = (struct he_rbp *) ((unsigned long)he_dev->rbpl_base |
  1672. RBPL_MASK(he_readl(he_dev, G0_RBPL_S)));
  1673. for (;;) {
  1674. newtail = (struct he_rbp *) ((unsigned long)he_dev->rbpl_base |
  1675. RBPL_MASK(he_dev->rbpl_tail+1));
  1676. /* table 3.42 -- rbpl_tail should never be set to rbpl_head */
  1677. if ((newtail == rbpl_head) || (newtail->status & RBP_LOANED))
  1678. break;
  1679. newtail->status |= RBP_LOANED;
  1680. he_dev->rbpl_tail = newtail;
  1681. ++moved;
  1682. }
  1683. if (moved)
  1684. he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail), G0_RBPL_T);
  1685. }
  1686. #ifdef USE_RBPS
  1687. static void
  1688. he_service_rbps(struct he_dev *he_dev, int group)
  1689. {
  1690. struct he_rbp *newtail;
  1691. struct he_rbp *rbps_head;
  1692. int moved = 0;
  1693. rbps_head = (struct he_rbp *) ((unsigned long)he_dev->rbps_base |
  1694. RBPS_MASK(he_readl(he_dev, G0_RBPS_S)));
  1695. for (;;) {
  1696. newtail = (struct he_rbp *) ((unsigned long)he_dev->rbps_base |
  1697. RBPS_MASK(he_dev->rbps_tail+1));
  1698. /* table 3.42 -- rbps_tail should never be set to rbps_head */
  1699. if ((newtail == rbps_head) || (newtail->status & RBP_LOANED))
  1700. break;
  1701. newtail->status |= RBP_LOANED;
  1702. he_dev->rbps_tail = newtail;
  1703. ++moved;
  1704. }
  1705. if (moved)
  1706. he_writel(he_dev, RBPS_MASK(he_dev->rbps_tail), G0_RBPS_T);
  1707. }
  1708. #endif /* USE_RBPS */
  1709. static void
  1710. he_tasklet(unsigned long data)
  1711. {
  1712. unsigned long flags;
  1713. struct he_dev *he_dev = (struct he_dev *) data;
  1714. int group, type;
  1715. int updated = 0;
  1716. HPRINTK("tasklet (0x%lx)\n", data);
  1717. #ifdef USE_TASKLET
  1718. spin_lock_irqsave(&he_dev->global_lock, flags);
  1719. #endif
  1720. while (he_dev->irq_head != he_dev->irq_tail) {
  1721. ++updated;
  1722. type = ITYPE_TYPE(he_dev->irq_head->isw);
  1723. group = ITYPE_GROUP(he_dev->irq_head->isw);
  1724. switch (type) {
  1725. case ITYPE_RBRQ_THRESH:
  1726. HPRINTK("rbrq%d threshold\n", group);
  1727. /* fall through */
  1728. case ITYPE_RBRQ_TIMER:
  1729. if (he_service_rbrq(he_dev, group)) {
  1730. he_service_rbpl(he_dev, group);
  1731. #ifdef USE_RBPS
  1732. he_service_rbps(he_dev, group);
  1733. #endif /* USE_RBPS */
  1734. }
  1735. break;
  1736. case ITYPE_TBRQ_THRESH:
  1737. HPRINTK("tbrq%d threshold\n", group);
  1738. /* fall through */
  1739. case ITYPE_TPD_COMPLETE:
  1740. he_service_tbrq(he_dev, group);
  1741. break;
  1742. case ITYPE_RBPL_THRESH:
  1743. he_service_rbpl(he_dev, group);
  1744. break;
  1745. case ITYPE_RBPS_THRESH:
  1746. #ifdef USE_RBPS
  1747. he_service_rbps(he_dev, group);
  1748. #endif /* USE_RBPS */
  1749. break;
  1750. case ITYPE_PHY:
  1751. HPRINTK("phy interrupt\n");
  1752. #ifdef CONFIG_ATM_HE_USE_SUNI
  1753. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  1754. if (he_dev->atm_dev->phy && he_dev->atm_dev->phy->interrupt)
  1755. he_dev->atm_dev->phy->interrupt(he_dev->atm_dev);
  1756. spin_lock_irqsave(&he_dev->global_lock, flags);
  1757. #endif
  1758. break;
  1759. case ITYPE_OTHER:
  1760. switch (type|group) {
  1761. case ITYPE_PARITY:
  1762. hprintk("parity error\n");
  1763. break;
  1764. case ITYPE_ABORT:
  1765. hprintk("abort 0x%x\n", he_readl(he_dev, ABORT_ADDR));
  1766. break;
  1767. }
  1768. break;
  1769. case ITYPE_TYPE(ITYPE_INVALID):
  1770. /* see 8.1.1 -- check all queues */
  1771. HPRINTK("isw not updated 0x%x\n", he_dev->irq_head->isw);
  1772. he_service_rbrq(he_dev, 0);
  1773. he_service_rbpl(he_dev, 0);
  1774. #ifdef USE_RBPS
  1775. he_service_rbps(he_dev, 0);
  1776. #endif /* USE_RBPS */
  1777. he_service_tbrq(he_dev, 0);
  1778. break;
  1779. default:
  1780. hprintk("bad isw 0x%x?\n", he_dev->irq_head->isw);
  1781. }
  1782. he_dev->irq_head->isw = ITYPE_INVALID;
  1783. he_dev->irq_head = (struct he_irq *) NEXT_ENTRY(he_dev->irq_base, he_dev->irq_head, IRQ_MASK);
  1784. }
  1785. if (updated) {
  1786. if (updated > he_dev->irq_peak)
  1787. he_dev->irq_peak = updated;
  1788. he_writel(he_dev,
  1789. IRQ_SIZE(CONFIG_IRQ_SIZE) |
  1790. IRQ_THRESH(CONFIG_IRQ_THRESH) |
  1791. IRQ_TAIL(he_dev->irq_tail), IRQ0_HEAD);
  1792. (void) he_readl(he_dev, INT_FIFO); /* 8.1.2 controller errata; flush posted writes */
  1793. }
  1794. #ifdef USE_TASKLET
  1795. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  1796. #endif
  1797. }
  1798. static irqreturn_t
  1799. he_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
  1800. {
  1801. unsigned long flags;
  1802. struct he_dev *he_dev = (struct he_dev * )dev_id;
  1803. int handled = 0;
  1804. if (he_dev == NULL)
  1805. return IRQ_NONE;
  1806. spin_lock_irqsave(&he_dev->global_lock, flags);
  1807. he_dev->irq_tail = (struct he_irq *) (((unsigned long)he_dev->irq_base) |
  1808. (*he_dev->irq_tailoffset << 2));
  1809. if (he_dev->irq_tail == he_dev->irq_head) {
  1810. HPRINTK("tailoffset not updated?\n");
  1811. he_dev->irq_tail = (struct he_irq *) ((unsigned long)he_dev->irq_base |
  1812. ((he_readl(he_dev, IRQ0_BASE) & IRQ_MASK) << 2));
  1813. (void) he_readl(he_dev, INT_FIFO); /* 8.1.2 controller errata */
  1814. }
  1815. #ifdef DEBUG
  1816. if (he_dev->irq_head == he_dev->irq_tail /* && !IRQ_PENDING */)
  1817. hprintk("spurious (or shared) interrupt?\n");
  1818. #endif
  1819. if (he_dev->irq_head != he_dev->irq_tail) {
  1820. handled = 1;
  1821. #ifdef USE_TASKLET
  1822. tasklet_schedule(&he_dev->tasklet);
  1823. #else
  1824. he_tasklet((unsigned long) he_dev);
  1825. #endif
  1826. he_writel(he_dev, INT_CLEAR_A, INT_FIFO); /* clear interrupt */
  1827. (void) he_readl(he_dev, INT_FIFO); /* flush posted writes */
  1828. }
  1829. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  1830. return IRQ_RETVAL(handled);
  1831. }
  1832. static __inline__ void
  1833. __enqueue_tpd(struct he_dev *he_dev, struct he_tpd *tpd, unsigned cid)
  1834. {
  1835. struct he_tpdrq *new_tail;
  1836. HPRINTK("tpdrq %p cid 0x%x -> tpdrq_tail %p\n",
  1837. tpd, cid, he_dev->tpdrq_tail);
  1838. /* new_tail = he_dev->tpdrq_tail; */
  1839. new_tail = (struct he_tpdrq *) ((unsigned long) he_dev->tpdrq_base |
  1840. TPDRQ_MASK(he_dev->tpdrq_tail+1));
  1841. /*
  1842. * check to see if we are about to set the tail == head
  1843. * if true, update the head pointer from the adapter
  1844. * to see if this is really the case (reading the queue
  1845. * head for every enqueue would be unnecessarily slow)
  1846. */
  1847. if (new_tail == he_dev->tpdrq_head) {
  1848. he_dev->tpdrq_head = (struct he_tpdrq *)
  1849. (((unsigned long)he_dev->tpdrq_base) |
  1850. TPDRQ_MASK(he_readl(he_dev, TPDRQ_B_H)));
  1851. if (new_tail == he_dev->tpdrq_head) {
  1852. hprintk("tpdrq full (cid 0x%x)\n", cid);
  1853. /*
  1854. * FIXME
  1855. * push tpd onto a transmit backlog queue
  1856. * after service_tbrq, service the backlog
  1857. * for now, we just drop the pdu
  1858. */
  1859. if (tpd->skb) {
  1860. if (tpd->vcc->pop)
  1861. tpd->vcc->pop(tpd->vcc, tpd->skb);
  1862. else
  1863. dev_kfree_skb_any(tpd->skb);
  1864. atomic_inc(&tpd->vcc->stats->tx_err);
  1865. }
  1866. #ifdef USE_TPD_POOL
  1867. pci_pool_free(he_dev->tpd_pool, tpd, TPD_ADDR(tpd->status));
  1868. #else
  1869. tpd->inuse = 0;
  1870. #endif
  1871. return;
  1872. }
  1873. }
  1874. /* 2.1.5 transmit packet descriptor ready queue */
  1875. #ifdef USE_TPD_POOL
  1876. list_add_tail(&tpd->entry, &he_dev->outstanding_tpds);
  1877. he_dev->tpdrq_tail->tpd = TPD_ADDR(tpd->status);
  1878. #else
  1879. he_dev->tpdrq_tail->tpd = he_dev->tpd_base_phys +
  1880. (TPD_INDEX(tpd->status) * sizeof(struct he_tpd));
  1881. #endif
  1882. he_dev->tpdrq_tail->cid = cid;
  1883. wmb();
  1884. he_dev->tpdrq_tail = new_tail;
  1885. he_writel(he_dev, TPDRQ_MASK(he_dev->tpdrq_tail), TPDRQ_T);
  1886. (void) he_readl(he_dev, TPDRQ_T); /* flush posted writes */
  1887. }
  1888. static int
  1889. he_open(struct atm_vcc *vcc)
  1890. {
  1891. unsigned long flags;
  1892. struct he_dev *he_dev = HE_DEV(vcc->dev);
  1893. struct he_vcc *he_vcc;
  1894. int err = 0;
  1895. unsigned cid, rsr0, rsr1, rsr4, tsr0, tsr0_aal, tsr4, period, reg, clock;
  1896. short vpi = vcc->vpi;
  1897. int vci = vcc->vci;
  1898. if (vci == ATM_VCI_UNSPEC || vpi == ATM_VPI_UNSPEC)
  1899. return 0;
  1900. HPRINTK("open vcc %p %d.%d\n", vcc, vpi, vci);
  1901. set_bit(ATM_VF_ADDR, &vcc->flags);
  1902. cid = he_mkcid(he_dev, vpi, vci);
  1903. he_vcc = (struct he_vcc *) kmalloc(sizeof(struct he_vcc), GFP_ATOMIC);
  1904. if (he_vcc == NULL) {
  1905. hprintk("unable to allocate he_vcc during open\n");
  1906. return -ENOMEM;
  1907. }
  1908. he_vcc->iov_tail = he_vcc->iov_head;
  1909. he_vcc->pdu_len = 0;
  1910. he_vcc->rc_index = -1;
  1911. init_waitqueue_head(&he_vcc->rx_waitq);
  1912. init_waitqueue_head(&he_vcc->tx_waitq);
  1913. vcc->dev_data = he_vcc;
  1914. if (vcc->qos.txtp.traffic_class != ATM_NONE) {
  1915. int pcr_goal;
  1916. pcr_goal = atm_pcr_goal(&vcc->qos.txtp);
  1917. if (pcr_goal == 0)
  1918. pcr_goal = he_dev->atm_dev->link_rate;
  1919. if (pcr_goal < 0) /* means round down, technically */
  1920. pcr_goal = -pcr_goal;
  1921. HPRINTK("open tx cid 0x%x pcr_goal %d\n", cid, pcr_goal);
  1922. switch (vcc->qos.aal) {
  1923. case ATM_AAL5:
  1924. tsr0_aal = TSR0_AAL5;
  1925. tsr4 = TSR4_AAL5;
  1926. break;
  1927. case ATM_AAL0:
  1928. tsr0_aal = TSR0_AAL0_SDU;
  1929. tsr4 = TSR4_AAL0_SDU;
  1930. break;
  1931. default:
  1932. err = -EINVAL;
  1933. goto open_failed;
  1934. }
  1935. spin_lock_irqsave(&he_dev->global_lock, flags);
  1936. tsr0 = he_readl_tsr0(he_dev, cid);
  1937. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  1938. if (TSR0_CONN_STATE(tsr0) != 0) {
  1939. hprintk("cid 0x%x not idle (tsr0 = 0x%x)\n", cid, tsr0);
  1940. err = -EBUSY;
  1941. goto open_failed;
  1942. }
  1943. switch (vcc->qos.txtp.traffic_class) {
  1944. case ATM_UBR:
  1945. /* 2.3.3.1 open connection ubr */
  1946. tsr0 = TSR0_UBR | TSR0_GROUP(0) | tsr0_aal |
  1947. TSR0_USE_WMIN | TSR0_UPDATE_GER;
  1948. break;
  1949. case ATM_CBR:
  1950. /* 2.3.3.2 open connection cbr */
  1951. /* 8.2.3 cbr scheduler wrap problem -- limit to 90% total link rate */
  1952. if ((he_dev->total_bw + pcr_goal)
  1953. > (he_dev->atm_dev->link_rate * 9 / 10))
  1954. {
  1955. err = -EBUSY;
  1956. goto open_failed;
  1957. }
  1958. spin_lock_irqsave(&he_dev->global_lock, flags); /* also protects he_dev->cs_stper[] */
  1959. /* find an unused cs_stper register */
  1960. for (reg = 0; reg < HE_NUM_CS_STPER; ++reg)
  1961. if (he_dev->cs_stper[reg].inuse == 0 ||
  1962. he_dev->cs_stper[reg].pcr == pcr_goal)
  1963. break;
  1964. if (reg == HE_NUM_CS_STPER) {
  1965. err = -EBUSY;
  1966. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  1967. goto open_failed;
  1968. }
  1969. he_dev->total_bw += pcr_goal;
  1970. he_vcc->rc_index = reg;
  1971. ++he_dev->cs_stper[reg].inuse;
  1972. he_dev->cs_stper[reg].pcr = pcr_goal;
  1973. clock = he_is622(he_dev) ? 66667000 : 50000000;
  1974. period = clock / pcr_goal;
  1975. HPRINTK("rc_index = %d period = %d\n",
  1976. reg, period);
  1977. he_writel_mbox(he_dev, rate_to_atmf(period/2),
  1978. CS_STPER0 + reg);
  1979. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  1980. tsr0 = TSR0_CBR | TSR0_GROUP(0) | tsr0_aal |
  1981. TSR0_RC_INDEX(reg);
  1982. break;
  1983. default:
  1984. err = -EINVAL;
  1985. goto open_failed;
  1986. }
  1987. spin_lock_irqsave(&he_dev->global_lock, flags);
  1988. he_writel_tsr0(he_dev, tsr0, cid);
  1989. he_writel_tsr4(he_dev, tsr4 | 1, cid);
  1990. he_writel_tsr1(he_dev, TSR1_MCR(rate_to_atmf(0)) |
  1991. TSR1_PCR(rate_to_atmf(pcr_goal)), cid);
  1992. he_writel_tsr2(he_dev, TSR2_ACR(rate_to_atmf(pcr_goal)), cid);
  1993. he_writel_tsr9(he_dev, TSR9_OPEN_CONN, cid);
  1994. he_writel_tsr3(he_dev, 0x0, cid);
  1995. he_writel_tsr5(he_dev, 0x0, cid);
  1996. he_writel_tsr6(he_dev, 0x0, cid);
  1997. he_writel_tsr7(he_dev, 0x0, cid);
  1998. he_writel_tsr8(he_dev, 0x0, cid);
  1999. he_writel_tsr10(he_dev, 0x0, cid);
  2000. he_writel_tsr11(he_dev, 0x0, cid);
  2001. he_writel_tsr12(he_dev, 0x0, cid);
  2002. he_writel_tsr13(he_dev, 0x0, cid);
  2003. he_writel_tsr14(he_dev, 0x0, cid);
  2004. (void) he_readl_tsr0(he_dev, cid); /* flush posted writes */
  2005. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  2006. }
  2007. if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
  2008. unsigned aal;
  2009. HPRINTK("open rx cid 0x%x (rx_waitq %p)\n", cid,
  2010. &HE_VCC(vcc)->rx_waitq);
  2011. switch (vcc->qos.aal) {
  2012. case ATM_AAL5:
  2013. aal = RSR0_AAL5;
  2014. break;
  2015. case ATM_AAL0:
  2016. aal = RSR0_RAWCELL;
  2017. break;
  2018. default:
  2019. err = -EINVAL;
  2020. goto open_failed;
  2021. }
  2022. spin_lock_irqsave(&he_dev->global_lock, flags);
  2023. rsr0 = he_readl_rsr0(he_dev, cid);
  2024. if (rsr0 & RSR0_OPEN_CONN) {
  2025. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  2026. hprintk("cid 0x%x not idle (rsr0 = 0x%x)\n", cid, rsr0);
  2027. err = -EBUSY;
  2028. goto open_failed;
  2029. }
  2030. #ifdef USE_RBPS
  2031. rsr1 = RSR1_GROUP(0);
  2032. rsr4 = RSR4_GROUP(0);
  2033. #else /* !USE_RBPS */
  2034. rsr1 = RSR1_GROUP(0)|RSR1_RBPL_ONLY;
  2035. rsr4 = RSR4_GROUP(0)|RSR4_RBPL_ONLY;
  2036. #endif /* USE_RBPS */
  2037. rsr0 = vcc->qos.rxtp.traffic_class == ATM_UBR ?
  2038. (RSR0_EPD_ENABLE|RSR0_PPD_ENABLE) : 0;
  2039. #ifdef USE_CHECKSUM_HW
  2040. if (vpi == 0 && vci >= ATM_NOT_RSV_VCI)
  2041. rsr0 |= RSR0_TCP_CKSUM;
  2042. #endif
  2043. he_writel_rsr4(he_dev, rsr4, cid);
  2044. he_writel_rsr1(he_dev, rsr1, cid);
  2045. /* 5.1.11 last parameter initialized should be
  2046. the open/closed indication in rsr0 */
  2047. he_writel_rsr0(he_dev,
  2048. rsr0 | RSR0_START_PDU | RSR0_OPEN_CONN | aal, cid);
  2049. (void) he_readl_rsr0(he_dev, cid); /* flush posted writes */
  2050. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  2051. }
  2052. open_failed:
  2053. if (err) {
  2054. kfree(he_vcc);
  2055. clear_bit(ATM_VF_ADDR, &vcc->flags);
  2056. }
  2057. else
  2058. set_bit(ATM_VF_READY, &vcc->flags);
  2059. return err;
  2060. }
  2061. static void
  2062. he_close(struct atm_vcc *vcc)
  2063. {
  2064. unsigned long flags;
  2065. DECLARE_WAITQUEUE(wait, current);
  2066. struct he_dev *he_dev = HE_DEV(vcc->dev);
  2067. struct he_tpd *tpd;
  2068. unsigned cid;
  2069. struct he_vcc *he_vcc = HE_VCC(vcc);
  2070. #define MAX_RETRY 30
  2071. int retry = 0, sleep = 1, tx_inuse;
  2072. HPRINTK("close vcc %p %d.%d\n", vcc, vcc->vpi, vcc->vci);
  2073. clear_bit(ATM_VF_READY, &vcc->flags);
  2074. cid = he_mkcid(he_dev, vcc->vpi, vcc->vci);
  2075. if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
  2076. int timeout;
  2077. HPRINTK("close rx cid 0x%x\n", cid);
  2078. /* 2.7.2.2 close receive operation */
  2079. /* wait for previous close (if any) to finish */
  2080. spin_lock_irqsave(&he_dev->global_lock, flags);
  2081. while (he_readl(he_dev, RCC_STAT) & RCC_BUSY) {
  2082. HPRINTK("close cid 0x%x RCC_BUSY\n", cid);
  2083. udelay(250);
  2084. }
  2085. set_current_state(TASK_UNINTERRUPTIBLE);
  2086. add_wait_queue(&he_vcc->rx_waitq, &wait);
  2087. he_writel_rsr0(he_dev, RSR0_CLOSE_CONN, cid);
  2088. (void) he_readl_rsr0(he_dev, cid); /* flush posted writes */
  2089. he_writel_mbox(he_dev, cid, RXCON_CLOSE);
  2090. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  2091. timeout = schedule_timeout(30*HZ);
  2092. remove_wait_queue(&he_vcc->rx_waitq, &wait);
  2093. set_current_state(TASK_RUNNING);
  2094. if (timeout == 0)
  2095. hprintk("close rx timeout cid 0x%x\n", cid);
  2096. HPRINTK("close rx cid 0x%x complete\n", cid);
  2097. }
  2098. if (vcc->qos.txtp.traffic_class != ATM_NONE) {
  2099. volatile unsigned tsr4, tsr0;
  2100. int timeout;
  2101. HPRINTK("close tx cid 0x%x\n", cid);
  2102. /* 2.1.2
  2103. *
  2104. * ... the host must first stop queueing packets to the TPDRQ
  2105. * on the connection to be closed, then wait for all outstanding
  2106. * packets to be transmitted and their buffers returned to the
  2107. * TBRQ. When the last packet on the connection arrives in the
  2108. * TBRQ, the host issues the close command to the adapter.
  2109. */
  2110. while (((tx_inuse = atomic_read(&sk_atm(vcc)->sk_wmem_alloc)) > 0) &&
  2111. (retry < MAX_RETRY)) {
  2112. msleep(sleep);
  2113. if (sleep < 250)
  2114. sleep = sleep * 2;
  2115. ++retry;
  2116. }
  2117. if (tx_inuse)
  2118. hprintk("close tx cid 0x%x tx_inuse = %d\n", cid, tx_inuse);
  2119. /* 2.3.1.1 generic close operations with flush */
  2120. spin_lock_irqsave(&he_dev->global_lock, flags);
  2121. he_writel_tsr4_upper(he_dev, TSR4_FLUSH_CONN, cid);
  2122. /* also clears TSR4_SESSION_ENDED */
  2123. switch (vcc->qos.txtp.traffic_class) {
  2124. case ATM_UBR:
  2125. he_writel_tsr1(he_dev,
  2126. TSR1_MCR(rate_to_atmf(200000))
  2127. | TSR1_PCR(0), cid);
  2128. break;
  2129. case ATM_CBR:
  2130. he_writel_tsr14_upper(he_dev, TSR14_DELETE, cid);
  2131. break;
  2132. }
  2133. (void) he_readl_tsr4(he_dev, cid); /* flush posted writes */
  2134. tpd = __alloc_tpd(he_dev);
  2135. if (tpd == NULL) {
  2136. hprintk("close tx he_alloc_tpd failed cid 0x%x\n", cid);
  2137. goto close_tx_incomplete;
  2138. }
  2139. tpd->status |= TPD_EOS | TPD_INT;
  2140. tpd->skb = NULL;
  2141. tpd->vcc = vcc;
  2142. wmb();
  2143. set_current_state(TASK_UNINTERRUPTIBLE);
  2144. add_wait_queue(&he_vcc->tx_waitq, &wait);
  2145. __enqueue_tpd(he_dev, tpd, cid);
  2146. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  2147. timeout = schedule_timeout(30*HZ);
  2148. remove_wait_queue(&he_vcc->tx_waitq, &wait);
  2149. set_current_state(TASK_RUNNING);
  2150. spin_lock_irqsave(&he_dev->global_lock, flags);
  2151. if (timeout == 0) {
  2152. hprintk("close tx timeout cid 0x%x\n", cid);
  2153. goto close_tx_incomplete;
  2154. }
  2155. while (!((tsr4 = he_readl_tsr4(he_dev, cid)) & TSR4_SESSION_ENDED)) {
  2156. HPRINTK("close tx cid 0x%x !TSR4_SESSION_ENDED (tsr4 = 0x%x)\n", cid, tsr4);
  2157. udelay(250);
  2158. }
  2159. while (TSR0_CONN_STATE(tsr0 = he_readl_tsr0(he_dev, cid)) != 0) {
  2160. HPRINTK("close tx cid 0x%x TSR0_CONN_STATE != 0 (tsr0 = 0x%x)\n", cid, tsr0);
  2161. udelay(250);
  2162. }
  2163. close_tx_incomplete:
  2164. if (vcc->qos.txtp.traffic_class == ATM_CBR) {
  2165. int reg = he_vcc->rc_index;
  2166. HPRINTK("cs_stper reg = %d\n", reg);
  2167. if (he_dev->cs_stper[reg].inuse == 0)
  2168. hprintk("cs_stper[%d].inuse = 0!\n", reg);
  2169. else
  2170. --he_dev->cs_stper[reg].inuse;
  2171. he_dev->total_bw -= he_dev->cs_stper[reg].pcr;
  2172. }
  2173. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  2174. HPRINTK("close tx cid 0x%x complete\n", cid);
  2175. }
  2176. kfree(he_vcc);
  2177. clear_bit(ATM_VF_ADDR, &vcc->flags);
  2178. }
  2179. static int
  2180. he_send(struct atm_vcc *vcc, struct sk_buff *skb)
  2181. {
  2182. unsigned long flags;
  2183. struct he_dev *he_dev = HE_DEV(vcc->dev);
  2184. unsigned cid = he_mkcid(he_dev, vcc->vpi, vcc->vci);
  2185. struct he_tpd *tpd;
  2186. #ifdef USE_SCATTERGATHER
  2187. int i, slot = 0;
  2188. #endif
  2189. #define HE_TPD_BUFSIZE 0xffff
  2190. HPRINTK("send %d.%d\n", vcc->vpi, vcc->vci);
  2191. if ((skb->len > HE_TPD_BUFSIZE) ||
  2192. ((vcc->qos.aal == ATM_AAL0) && (skb->len != ATM_AAL0_SDU))) {
  2193. hprintk("buffer too large (or small) -- %d bytes\n", skb->len );
  2194. if (vcc->pop)
  2195. vcc->pop(vcc, skb);
  2196. else
  2197. dev_kfree_skb_any(skb);
  2198. atomic_inc(&vcc->stats->tx_err);
  2199. return -EINVAL;
  2200. }
  2201. #ifndef USE_SCATTERGATHER
  2202. if (skb_shinfo(skb)->nr_frags) {
  2203. hprintk("no scatter/gather support\n");
  2204. if (vcc->pop)
  2205. vcc->pop(vcc, skb);
  2206. else
  2207. dev_kfree_skb_any(skb);
  2208. atomic_inc(&vcc->stats->tx_err);
  2209. return -EINVAL;
  2210. }
  2211. #endif
  2212. spin_lock_irqsave(&he_dev->global_lock, flags);
  2213. tpd = __alloc_tpd(he_dev);
  2214. if (tpd == NULL) {
  2215. if (vcc->pop)
  2216. vcc->pop(vcc, skb);
  2217. else
  2218. dev_kfree_skb_any(skb);
  2219. atomic_inc(&vcc->stats->tx_err);
  2220. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  2221. return -ENOMEM;
  2222. }
  2223. if (vcc->qos.aal == ATM_AAL5)
  2224. tpd->status |= TPD_CELLTYPE(TPD_USERCELL);
  2225. else {
  2226. char *pti_clp = (void *) (skb->data + 3);
  2227. int clp, pti;
  2228. pti = (*pti_clp & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT;
  2229. clp = (*pti_clp & ATM_HDR_CLP);
  2230. tpd->status |= TPD_CELLTYPE(pti);
  2231. if (clp)
  2232. tpd->status |= TPD_CLP;
  2233. skb_pull(skb, ATM_AAL0_SDU - ATM_CELL_PAYLOAD);
  2234. }
  2235. #ifdef USE_SCATTERGATHER
  2236. tpd->iovec[slot].addr = pci_map_single(he_dev->pci_dev, skb->data,
  2237. skb->len - skb->data_len, PCI_DMA_TODEVICE);
  2238. tpd->iovec[slot].len = skb->len - skb->data_len;
  2239. ++slot;
  2240. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  2241. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  2242. if (slot == TPD_MAXIOV) { /* queue tpd; start new tpd */
  2243. tpd->vcc = vcc;
  2244. tpd->skb = NULL; /* not the last fragment
  2245. so dont ->push() yet */
  2246. wmb();
  2247. __enqueue_tpd(he_dev, tpd, cid);
  2248. tpd = __alloc_tpd(he_dev);
  2249. if (tpd == NULL) {
  2250. if (vcc->pop)
  2251. vcc->pop(vcc, skb);
  2252. else
  2253. dev_kfree_skb_any(skb);
  2254. atomic_inc(&vcc->stats->tx_err);
  2255. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  2256. return -ENOMEM;
  2257. }
  2258. tpd->status |= TPD_USERCELL;
  2259. slot = 0;
  2260. }
  2261. tpd->iovec[slot].addr = pci_map_single(he_dev->pci_dev,
  2262. (void *) page_address(frag->page) + frag->page_offset,
  2263. frag->size, PCI_DMA_TODEVICE);
  2264. tpd->iovec[slot].len = frag->size;
  2265. ++slot;
  2266. }
  2267. tpd->iovec[slot - 1].len |= TPD_LST;
  2268. #else
  2269. tpd->address0 = pci_map_single(he_dev->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
  2270. tpd->length0 = skb->len | TPD_LST;
  2271. #endif
  2272. tpd->status |= TPD_INT;
  2273. tpd->vcc = vcc;
  2274. tpd->skb = skb;
  2275. wmb();
  2276. ATM_SKB(skb)->vcc = vcc;
  2277. __enqueue_tpd(he_dev, tpd, cid);
  2278. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  2279. atomic_inc(&vcc->stats->tx);
  2280. return 0;
  2281. }
  2282. static int
  2283. he_ioctl(struct atm_dev *atm_dev, unsigned int cmd, void __user *arg)
  2284. {
  2285. unsigned long flags;
  2286. struct he_dev *he_dev = HE_DEV(atm_dev);
  2287. struct he_ioctl_reg reg;
  2288. int err = 0;
  2289. switch (cmd) {
  2290. case HE_GET_REG:
  2291. if (!capable(CAP_NET_ADMIN))
  2292. return -EPERM;
  2293. if (copy_from_user(&reg, arg,
  2294. sizeof(struct he_ioctl_reg)))
  2295. return -EFAULT;
  2296. spin_lock_irqsave(&he_dev->global_lock, flags);
  2297. switch (reg.type) {
  2298. case HE_REGTYPE_PCI:
  2299. reg.val = he_readl(he_dev, reg.addr);
  2300. break;
  2301. case HE_REGTYPE_RCM:
  2302. reg.val =
  2303. he_readl_rcm(he_dev, reg.addr);
  2304. break;
  2305. case HE_REGTYPE_TCM:
  2306. reg.val =
  2307. he_readl_tcm(he_dev, reg.addr);
  2308. break;
  2309. case HE_REGTYPE_MBOX:
  2310. reg.val =
  2311. he_readl_mbox(he_dev, reg.addr);
  2312. break;
  2313. default:
  2314. err = -EINVAL;
  2315. break;
  2316. }
  2317. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  2318. if (err == 0)
  2319. if (copy_to_user(arg, &reg,
  2320. sizeof(struct he_ioctl_reg)))
  2321. return -EFAULT;
  2322. break;
  2323. default:
  2324. #ifdef CONFIG_ATM_HE_USE_SUNI
  2325. if (atm_dev->phy && atm_dev->phy->ioctl)
  2326. err = atm_dev->phy->ioctl(atm_dev, cmd, arg);
  2327. #else /* CONFIG_ATM_HE_USE_SUNI */
  2328. err = -EINVAL;
  2329. #endif /* CONFIG_ATM_HE_USE_SUNI */
  2330. break;
  2331. }
  2332. return err;
  2333. }
  2334. static void
  2335. he_phy_put(struct atm_dev *atm_dev, unsigned char val, unsigned long addr)
  2336. {
  2337. unsigned long flags;
  2338. struct he_dev *he_dev = HE_DEV(atm_dev);
  2339. HPRINTK("phy_put(val 0x%x, addr 0x%lx)\n", val, addr);
  2340. spin_lock_irqsave(&he_dev->global_lock, flags);
  2341. he_writel(he_dev, val, FRAMER + (addr*4));
  2342. (void) he_readl(he_dev, FRAMER + (addr*4)); /* flush posted writes */
  2343. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  2344. }
  2345. static unsigned char
  2346. he_phy_get(struct atm_dev *atm_dev, unsigned long addr)
  2347. {
  2348. unsigned long flags;
  2349. struct he_dev *he_dev = HE_DEV(atm_dev);
  2350. unsigned reg;
  2351. spin_lock_irqsave(&he_dev->global_lock, flags);
  2352. reg = he_readl(he_dev, FRAMER + (addr*4));
  2353. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  2354. HPRINTK("phy_get(addr 0x%lx) =0x%x\n", addr, reg);
  2355. return reg;
  2356. }
  2357. static int
  2358. he_proc_read(struct atm_dev *dev, loff_t *pos, char *page)
  2359. {
  2360. unsigned long flags;
  2361. struct he_dev *he_dev = HE_DEV(dev);
  2362. int left, i;
  2363. #ifdef notdef
  2364. struct he_rbrq *rbrq_tail;
  2365. struct he_tpdrq *tpdrq_head;
  2366. int rbpl_head, rbpl_tail;
  2367. #endif
  2368. static long mcc = 0, oec = 0, dcc = 0, cec = 0;
  2369. left = *pos;
  2370. if (!left--)
  2371. return sprintf(page, "%s\n", version);
  2372. if (!left--)
  2373. return sprintf(page, "%s%s\n\n",
  2374. he_dev->prod_id, he_dev->media & 0x40 ? "SM" : "MM");
  2375. if (!left--)
  2376. return sprintf(page, "Mismatched Cells VPI/VCI Not Open Dropped Cells RCM Dropped Cells\n");
  2377. spin_lock_irqsave(&he_dev->global_lock, flags);
  2378. mcc += he_readl(he_dev, MCC);
  2379. oec += he_readl(he_dev, OEC);
  2380. dcc += he_readl(he_dev, DCC);
  2381. cec += he_readl(he_dev, CEC);
  2382. spin_unlock_irqrestore(&he_dev->global_lock, flags);
  2383. if (!left--)
  2384. return sprintf(page, "%16ld %16ld %13ld %17ld\n\n",
  2385. mcc, oec, dcc, cec);
  2386. if (!left--)
  2387. return sprintf(page, "irq_size = %d inuse = ? peak = %d\n",
  2388. CONFIG_IRQ_SIZE, he_dev->irq_peak);
  2389. if (!left--)
  2390. return sprintf(page, "tpdrq_size = %d inuse = ?\n",
  2391. CONFIG_TPDRQ_SIZE);
  2392. if (!left--)
  2393. return sprintf(page, "rbrq_size = %d inuse = ? peak = %d\n",
  2394. CONFIG_RBRQ_SIZE, he_dev->rbrq_peak);
  2395. if (!left--)
  2396. return sprintf(page, "tbrq_size = %d peak = %d\n",
  2397. CONFIG_TBRQ_SIZE, he_dev->tbrq_peak);
  2398. #ifdef notdef
  2399. rbpl_head = RBPL_MASK(he_readl(he_dev, G0_RBPL_S));
  2400. rbpl_tail = RBPL_MASK(he_readl(he_dev, G0_RBPL_T));
  2401. inuse = rbpl_head - rbpl_tail;
  2402. if (inuse < 0)
  2403. inuse += CONFIG_RBPL_SIZE * sizeof(struct he_rbp);
  2404. inuse /= sizeof(struct he_rbp);
  2405. if (!left--)
  2406. return sprintf(page, "rbpl_size = %d inuse = %d\n\n",
  2407. CONFIG_RBPL_SIZE, inuse);
  2408. #endif
  2409. if (!left--)
  2410. return sprintf(page, "rate controller periods (cbr)\n pcr #vc\n");
  2411. for (i = 0; i < HE_NUM_CS_STPER; ++i)
  2412. if (!left--)
  2413. return sprintf(page, "cs_stper%-2d %8ld %3d\n", i,
  2414. he_dev->cs_stper[i].pcr,
  2415. he_dev->cs_stper[i].inuse);
  2416. if (!left--)
  2417. return sprintf(page, "total bw (cbr): %d (limit %d)\n",
  2418. he_dev->total_bw, he_dev->atm_dev->link_rate * 10 / 9);
  2419. return 0;
  2420. }
  2421. /* eeprom routines -- see 4.7 */
  2422. u8
  2423. read_prom_byte(struct he_dev *he_dev, int addr)
  2424. {
  2425. u32 val = 0, tmp_read = 0;
  2426. int i, j = 0;
  2427. u8 byte_read = 0;
  2428. val = readl(he_dev->membase + HOST_CNTL);
  2429. val &= 0xFFFFE0FF;
  2430. /* Turn on write enable */
  2431. val |= 0x800;
  2432. he_writel(he_dev, val, HOST_CNTL);
  2433. /* Send READ instruction */
  2434. for (i = 0; i < sizeof(readtab)/sizeof(readtab[0]); i++) {
  2435. he_writel(he_dev, val | readtab[i], HOST_CNTL);
  2436. udelay(EEPROM_DELAY);
  2437. }
  2438. /* Next, we need to send the byte address to read from */
  2439. for (i = 7; i >= 0; i--) {
  2440. he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL);
  2441. udelay(EEPROM_DELAY);
  2442. he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL);
  2443. udelay(EEPROM_DELAY);
  2444. }
  2445. j = 0;
  2446. val &= 0xFFFFF7FF; /* Turn off write enable */
  2447. he_writel(he_dev, val, HOST_CNTL);
  2448. /* Now, we can read data from the EEPROM by clocking it in */
  2449. for (i = 7; i >= 0; i--) {
  2450. he_writel(he_dev, val | clocktab[j++], HOST_CNTL);
  2451. udelay(EEPROM_DELAY);
  2452. tmp_read = he_readl(he_dev, HOST_CNTL);
  2453. byte_read |= (unsigned char)
  2454. ((tmp_read & ID_DOUT) >> ID_DOFFSET << i);
  2455. he_writel(he_dev, val | clocktab[j++], HOST_CNTL);
  2456. udelay(EEPROM_DELAY);
  2457. }
  2458. he_writel(he_dev, val | ID_CS, HOST_CNTL);
  2459. udelay(EEPROM_DELAY);
  2460. return byte_read;
  2461. }
  2462. MODULE_LICENSE("GPL");
  2463. MODULE_AUTHOR("chas williams <chas@cmf.nrl.navy.mil>");
  2464. MODULE_DESCRIPTION("ForeRunnerHE ATM Adapter driver");
  2465. module_param(disable64, bool, 0);
  2466. MODULE_PARM_DESC(disable64, "disable 64-bit pci bus transfers");
  2467. module_param(nvpibits, short, 0);
  2468. MODULE_PARM_DESC(nvpibits, "numbers of bits for vpi (default 0)");
  2469. module_param(nvcibits, short, 0);
  2470. MODULE_PARM_DESC(nvcibits, "numbers of bits for vci (default 12)");
  2471. module_param(rx_skb_reserve, short, 0);
  2472. MODULE_PARM_DESC(rx_skb_reserve, "padding for receive skb (default 16)");
  2473. module_param(irq_coalesce, bool, 0);
  2474. MODULE_PARM_DESC(irq_coalesce, "use interrupt coalescing (default 1)");
  2475. module_param(sdh, bool, 0);
  2476. MODULE_PARM_DESC(sdh, "use SDH framing (default 0)");
  2477. static struct pci_device_id he_pci_tbl[] = {
  2478. { PCI_VENDOR_ID_FORE, PCI_DEVICE_ID_FORE_HE, PCI_ANY_ID, PCI_ANY_ID,
  2479. 0, 0, 0 },
  2480. { 0, }
  2481. };
  2482. MODULE_DEVICE_TABLE(pci, he_pci_tbl);
  2483. static struct pci_driver he_driver = {
  2484. .name = "he",
  2485. .probe = he_init_one,
  2486. .remove = __devexit_p(he_remove_one),
  2487. .id_table = he_pci_tbl,
  2488. };
  2489. static int __init he_init(void)
  2490. {
  2491. return pci_register_driver(&he_driver);
  2492. }
  2493. static void __exit he_cleanup(void)
  2494. {
  2495. pci_unregister_driver(&he_driver);
  2496. }
  2497. module_init(he_init);
  2498. module_exit(he_cleanup);