mce_amd.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540
  1. /*
  2. * (c) 2005 Advanced Micro Devices, Inc.
  3. * Your use of this code is subject to the terms and conditions of the
  4. * GNU general public license version 2. See "COPYING" or
  5. * http://www.gnu.org/licenses/gpl.html
  6. *
  7. * Written by Jacob Shin - AMD, Inc.
  8. *
  9. * Support : jacob.shin@amd.com
  10. *
  11. * MC4_MISC0 DRAM ECC Error Threshold available under AMD K8 Rev F.
  12. * MC4_MISC0 exists per physical processor.
  13. *
  14. */
  15. #include <linux/cpu.h>
  16. #include <linux/errno.h>
  17. #include <linux/init.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/kobject.h>
  20. #include <linux/notifier.h>
  21. #include <linux/sched.h>
  22. #include <linux/smp.h>
  23. #include <linux/sysdev.h>
  24. #include <linux/sysfs.h>
  25. #include <asm/apic.h>
  26. #include <asm/mce.h>
  27. #include <asm/msr.h>
  28. #include <asm/percpu.h>
  29. #include <asm/idle.h>
  30. #define PFX "mce_threshold: "
  31. #define VERSION "version 1.00.9"
  32. #define NR_BANKS 5
  33. #define THRESHOLD_MAX 0xFFF
  34. #define INT_TYPE_APIC 0x00020000
  35. #define MASK_VALID_HI 0x80000000
  36. #define MASK_LVTOFF_HI 0x00F00000
  37. #define MASK_COUNT_EN_HI 0x00080000
  38. #define MASK_INT_TYPE_HI 0x00060000
  39. #define MASK_OVERFLOW_HI 0x00010000
  40. #define MASK_ERR_COUNT_HI 0x00000FFF
  41. #define MASK_OVERFLOW 0x0001000000000000L
  42. struct threshold_bank {
  43. unsigned int cpu;
  44. u8 bank;
  45. u8 interrupt_enable;
  46. u16 threshold_limit;
  47. struct kobject kobj;
  48. };
  49. static struct threshold_bank threshold_defaults = {
  50. .interrupt_enable = 0,
  51. .threshold_limit = THRESHOLD_MAX,
  52. };
  53. #ifdef CONFIG_SMP
  54. static unsigned char shared_bank[NR_BANKS] = {
  55. 0, 0, 0, 0, 1
  56. };
  57. #endif
  58. static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
  59. /*
  60. * CPU Initialization
  61. */
  62. /* must be called with correct cpu affinity */
  63. static void threshold_restart_bank(struct threshold_bank *b,
  64. int reset, u16 old_limit)
  65. {
  66. u32 mci_misc_hi, mci_misc_lo;
  67. rdmsr(MSR_IA32_MC0_MISC + b->bank * 4, mci_misc_lo, mci_misc_hi);
  68. if (b->threshold_limit < (mci_misc_hi & THRESHOLD_MAX))
  69. reset = 1; /* limit cannot be lower than err count */
  70. if (reset) { /* reset err count and overflow bit */
  71. mci_misc_hi =
  72. (mci_misc_hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
  73. (THRESHOLD_MAX - b->threshold_limit);
  74. } else if (old_limit) { /* change limit w/o reset */
  75. int new_count = (mci_misc_hi & THRESHOLD_MAX) +
  76. (old_limit - b->threshold_limit);
  77. mci_misc_hi = (mci_misc_hi & ~MASK_ERR_COUNT_HI) |
  78. (new_count & THRESHOLD_MAX);
  79. }
  80. b->interrupt_enable ?
  81. (mci_misc_hi = (mci_misc_hi & ~MASK_INT_TYPE_HI) | INT_TYPE_APIC) :
  82. (mci_misc_hi &= ~MASK_INT_TYPE_HI);
  83. mci_misc_hi |= MASK_COUNT_EN_HI;
  84. wrmsr(MSR_IA32_MC0_MISC + b->bank * 4, mci_misc_lo, mci_misc_hi);
  85. }
  86. void __cpuinit mce_amd_feature_init(struct cpuinfo_x86 *c)
  87. {
  88. int bank;
  89. u32 mci_misc_lo, mci_misc_hi;
  90. unsigned int cpu = smp_processor_id();
  91. for (bank = 0; bank < NR_BANKS; ++bank) {
  92. rdmsr(MSR_IA32_MC0_MISC + bank * 4, mci_misc_lo, mci_misc_hi);
  93. /* !valid, !counter present, bios locked */
  94. if (!(mci_misc_hi & MASK_VALID_HI) ||
  95. !(mci_misc_hi & MASK_VALID_HI >> 1) ||
  96. (mci_misc_hi & MASK_VALID_HI >> 2))
  97. continue;
  98. per_cpu(bank_map, cpu) |= (1 << bank);
  99. #ifdef CONFIG_SMP
  100. if (shared_bank[bank] && cpu_core_id[cpu])
  101. continue;
  102. #endif
  103. setup_threshold_lvt((mci_misc_hi & MASK_LVTOFF_HI) >> 20);
  104. threshold_defaults.cpu = cpu;
  105. threshold_defaults.bank = bank;
  106. threshold_restart_bank(&threshold_defaults, 0, 0);
  107. }
  108. }
  109. /*
  110. * APIC Interrupt Handler
  111. */
  112. /*
  113. * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
  114. * the interrupt goes off when error_count reaches threshold_limit.
  115. * the handler will simply log mcelog w/ software defined bank number.
  116. */
  117. asmlinkage void mce_threshold_interrupt(void)
  118. {
  119. int bank;
  120. struct mce m;
  121. ack_APIC_irq();
  122. exit_idle();
  123. irq_enter();
  124. memset(&m, 0, sizeof(m));
  125. rdtscll(m.tsc);
  126. m.cpu = smp_processor_id();
  127. /* assume first bank caused it */
  128. for (bank = 0; bank < NR_BANKS; ++bank) {
  129. m.bank = MCE_THRESHOLD_BASE + bank;
  130. rdmsrl(MSR_IA32_MC0_MISC + bank * 4, m.misc);
  131. if (m.misc & MASK_OVERFLOW) {
  132. mce_log(&m);
  133. goto out;
  134. }
  135. }
  136. out:
  137. irq_exit();
  138. }
  139. /*
  140. * Sysfs Interface
  141. */
  142. static struct sysdev_class threshold_sysclass = {
  143. set_kset_name("threshold"),
  144. };
  145. static DEFINE_PER_CPU(struct sys_device, device_threshold);
  146. struct threshold_attr {
  147. struct attribute attr;
  148. ssize_t(*show) (struct threshold_bank *, char *);
  149. ssize_t(*store) (struct threshold_bank *, const char *, size_t count);
  150. };
  151. static DEFINE_PER_CPU(struct threshold_bank *, threshold_banks[NR_BANKS]);
  152. static cpumask_t affinity_set(unsigned int cpu)
  153. {
  154. cpumask_t oldmask = current->cpus_allowed;
  155. cpumask_t newmask = CPU_MASK_NONE;
  156. cpu_set(cpu, newmask);
  157. set_cpus_allowed(current, newmask);
  158. return oldmask;
  159. }
  160. static void affinity_restore(cpumask_t oldmask)
  161. {
  162. set_cpus_allowed(current, oldmask);
  163. }
  164. #define SHOW_FIELDS(name) \
  165. static ssize_t show_ ## name(struct threshold_bank * b, char *buf) \
  166. { \
  167. return sprintf(buf, "%lx\n", (unsigned long) b->name); \
  168. }
  169. SHOW_FIELDS(interrupt_enable)
  170. SHOW_FIELDS(threshold_limit)
  171. static ssize_t store_interrupt_enable(struct threshold_bank *b,
  172. const char *buf, size_t count)
  173. {
  174. char *end;
  175. cpumask_t oldmask;
  176. unsigned long new = simple_strtoul(buf, &end, 0);
  177. if (end == buf)
  178. return -EINVAL;
  179. b->interrupt_enable = !!new;
  180. oldmask = affinity_set(b->cpu);
  181. threshold_restart_bank(b, 0, 0);
  182. affinity_restore(oldmask);
  183. return end - buf;
  184. }
  185. static ssize_t store_threshold_limit(struct threshold_bank *b,
  186. const char *buf, size_t count)
  187. {
  188. char *end;
  189. cpumask_t oldmask;
  190. u16 old;
  191. unsigned long new = simple_strtoul(buf, &end, 0);
  192. if (end == buf)
  193. return -EINVAL;
  194. if (new > THRESHOLD_MAX)
  195. new = THRESHOLD_MAX;
  196. if (new < 1)
  197. new = 1;
  198. old = b->threshold_limit;
  199. b->threshold_limit = new;
  200. oldmask = affinity_set(b->cpu);
  201. threshold_restart_bank(b, 0, old);
  202. affinity_restore(oldmask);
  203. return end - buf;
  204. }
  205. static ssize_t show_error_count(struct threshold_bank *b, char *buf)
  206. {
  207. u32 high, low;
  208. cpumask_t oldmask;
  209. oldmask = affinity_set(b->cpu);
  210. rdmsr(MSR_IA32_MC0_MISC + b->bank * 4, low, high); /* ignore low 32 */
  211. affinity_restore(oldmask);
  212. return sprintf(buf, "%x\n",
  213. (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit));
  214. }
  215. static ssize_t store_error_count(struct threshold_bank *b,
  216. const char *buf, size_t count)
  217. {
  218. cpumask_t oldmask;
  219. oldmask = affinity_set(b->cpu);
  220. threshold_restart_bank(b, 1, 0);
  221. affinity_restore(oldmask);
  222. return 1;
  223. }
  224. #define THRESHOLD_ATTR(_name,_mode,_show,_store) { \
  225. .attr = {.name = __stringify(_name), .mode = _mode }, \
  226. .show = _show, \
  227. .store = _store, \
  228. };
  229. #define ATTR_FIELDS(name) \
  230. static struct threshold_attr name = \
  231. THRESHOLD_ATTR(name, 0644, show_## name, store_## name)
  232. ATTR_FIELDS(interrupt_enable);
  233. ATTR_FIELDS(threshold_limit);
  234. ATTR_FIELDS(error_count);
  235. static struct attribute *default_attrs[] = {
  236. &interrupt_enable.attr,
  237. &threshold_limit.attr,
  238. &error_count.attr,
  239. NULL
  240. };
  241. #define to_bank(k) container_of(k,struct threshold_bank,kobj)
  242. #define to_attr(a) container_of(a,struct threshold_attr,attr)
  243. static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
  244. {
  245. struct threshold_bank *b = to_bank(kobj);
  246. struct threshold_attr *a = to_attr(attr);
  247. ssize_t ret;
  248. ret = a->show ? a->show(b, buf) : -EIO;
  249. return ret;
  250. }
  251. static ssize_t store(struct kobject *kobj, struct attribute *attr,
  252. const char *buf, size_t count)
  253. {
  254. struct threshold_bank *b = to_bank(kobj);
  255. struct threshold_attr *a = to_attr(attr);
  256. ssize_t ret;
  257. ret = a->store ? a->store(b, buf, count) : -EIO;
  258. return ret;
  259. }
  260. static struct sysfs_ops threshold_ops = {
  261. .show = show,
  262. .store = store,
  263. };
  264. static struct kobj_type threshold_ktype = {
  265. .sysfs_ops = &threshold_ops,
  266. .default_attrs = default_attrs,
  267. };
  268. /* symlinks sibling shared banks to first core. first core owns dir/files. */
  269. static __cpuinit int threshold_create_bank(unsigned int cpu, int bank)
  270. {
  271. int err = 0;
  272. struct threshold_bank *b = NULL;
  273. #ifdef CONFIG_SMP
  274. if (cpu_core_id[cpu] && shared_bank[bank]) { /* symlink */
  275. char name[16];
  276. unsigned lcpu = first_cpu(cpu_core_map[cpu]);
  277. if (cpu_core_id[lcpu])
  278. goto out; /* first core not up yet */
  279. b = per_cpu(threshold_banks, lcpu)[bank];
  280. if (!b)
  281. goto out;
  282. sprintf(name, "bank%i", bank);
  283. err = sysfs_create_link(&per_cpu(device_threshold, cpu).kobj,
  284. &b->kobj, name);
  285. if (err)
  286. goto out;
  287. per_cpu(threshold_banks, cpu)[bank] = b;
  288. goto out;
  289. }
  290. #endif
  291. b = kmalloc(sizeof(struct threshold_bank), GFP_KERNEL);
  292. if (!b) {
  293. err = -ENOMEM;
  294. goto out;
  295. }
  296. memset(b, 0, sizeof(struct threshold_bank));
  297. b->cpu = cpu;
  298. b->bank = bank;
  299. b->interrupt_enable = 0;
  300. b->threshold_limit = THRESHOLD_MAX;
  301. kobject_set_name(&b->kobj, "bank%i", bank);
  302. b->kobj.parent = &per_cpu(device_threshold, cpu).kobj;
  303. b->kobj.ktype = &threshold_ktype;
  304. err = kobject_register(&b->kobj);
  305. if (err) {
  306. kfree(b);
  307. goto out;
  308. }
  309. per_cpu(threshold_banks, cpu)[bank] = b;
  310. out:
  311. return err;
  312. }
  313. /* create dir/files for all valid threshold banks */
  314. static __cpuinit int threshold_create_device(unsigned int cpu)
  315. {
  316. int bank;
  317. int err = 0;
  318. per_cpu(device_threshold, cpu).id = cpu;
  319. per_cpu(device_threshold, cpu).cls = &threshold_sysclass;
  320. err = sysdev_register(&per_cpu(device_threshold, cpu));
  321. if (err)
  322. goto out;
  323. for (bank = 0; bank < NR_BANKS; ++bank) {
  324. if (!(per_cpu(bank_map, cpu) & 1 << bank))
  325. continue;
  326. err = threshold_create_bank(cpu, bank);
  327. if (err)
  328. goto out;
  329. }
  330. out:
  331. return err;
  332. }
  333. #ifdef CONFIG_HOTPLUG_CPU
  334. /*
  335. * let's be hotplug friendly.
  336. * in case of multiple core processors, the first core always takes ownership
  337. * of shared sysfs dir/files, and rest of the cores will be symlinked to it.
  338. */
  339. /* cpu hotplug call removes all symlinks before first core dies */
  340. static __cpuinit void threshold_remove_bank(unsigned int cpu, int bank)
  341. {
  342. struct threshold_bank *b;
  343. char name[16];
  344. b = per_cpu(threshold_banks, cpu)[bank];
  345. if (!b)
  346. return;
  347. if (shared_bank[bank] && atomic_read(&b->kobj.kref.refcount) > 2) {
  348. sprintf(name, "bank%i", bank);
  349. sysfs_remove_link(&per_cpu(device_threshold, cpu).kobj, name);
  350. per_cpu(threshold_banks, cpu)[bank] = NULL;
  351. } else {
  352. kobject_unregister(&b->kobj);
  353. kfree(per_cpu(threshold_banks, cpu)[bank]);
  354. }
  355. }
  356. static __cpuinit void threshold_remove_device(unsigned int cpu)
  357. {
  358. int bank;
  359. for (bank = 0; bank < NR_BANKS; ++bank) {
  360. if (!(per_cpu(bank_map, cpu) & 1 << bank))
  361. continue;
  362. threshold_remove_bank(cpu, bank);
  363. }
  364. sysdev_unregister(&per_cpu(device_threshold, cpu));
  365. }
  366. /* link all existing siblings when first core comes up */
  367. static __cpuinit int threshold_create_symlinks(unsigned int cpu)
  368. {
  369. int bank, err = 0;
  370. unsigned int lcpu = 0;
  371. if (cpu_core_id[cpu])
  372. return 0;
  373. for_each_cpu_mask(lcpu, cpu_core_map[cpu]) {
  374. if (lcpu == cpu)
  375. continue;
  376. for (bank = 0; bank < NR_BANKS; ++bank) {
  377. if (!(per_cpu(bank_map, cpu) & 1 << bank))
  378. continue;
  379. if (!shared_bank[bank])
  380. continue;
  381. err = threshold_create_bank(lcpu, bank);
  382. }
  383. }
  384. return err;
  385. }
  386. /* remove all symlinks before first core dies. */
  387. static __cpuinit void threshold_remove_symlinks(unsigned int cpu)
  388. {
  389. int bank;
  390. unsigned int lcpu = 0;
  391. if (cpu_core_id[cpu])
  392. return;
  393. for_each_cpu_mask(lcpu, cpu_core_map[cpu]) {
  394. if (lcpu == cpu)
  395. continue;
  396. for (bank = 0; bank < NR_BANKS; ++bank) {
  397. if (!(per_cpu(bank_map, cpu) & 1 << bank))
  398. continue;
  399. if (!shared_bank[bank])
  400. continue;
  401. threshold_remove_bank(lcpu, bank);
  402. }
  403. }
  404. }
  405. #else /* !CONFIG_HOTPLUG_CPU */
  406. static __cpuinit void threshold_create_symlinks(unsigned int cpu)
  407. {
  408. }
  409. static __cpuinit void threshold_remove_symlinks(unsigned int cpu)
  410. {
  411. }
  412. static void threshold_remove_device(unsigned int cpu)
  413. {
  414. }
  415. #endif
  416. /* get notified when a cpu comes on/off */
  417. static __cpuinit int threshold_cpu_callback(struct notifier_block *nfb,
  418. unsigned long action, void *hcpu)
  419. {
  420. /* cpu was unsigned int to begin with */
  421. unsigned int cpu = (unsigned long)hcpu;
  422. if (cpu >= NR_CPUS)
  423. goto out;
  424. switch (action) {
  425. case CPU_ONLINE:
  426. threshold_create_device(cpu);
  427. threshold_create_symlinks(cpu);
  428. break;
  429. case CPU_DOWN_PREPARE:
  430. threshold_remove_symlinks(cpu);
  431. break;
  432. case CPU_DOWN_FAILED:
  433. threshold_create_symlinks(cpu);
  434. break;
  435. case CPU_DEAD:
  436. threshold_remove_device(cpu);
  437. break;
  438. default:
  439. break;
  440. }
  441. out:
  442. return NOTIFY_OK;
  443. }
  444. static struct notifier_block threshold_cpu_notifier = {
  445. .notifier_call = threshold_cpu_callback,
  446. };
  447. static __init int threshold_init_device(void)
  448. {
  449. int err;
  450. int lcpu = 0;
  451. err = sysdev_class_register(&threshold_sysclass);
  452. if (err)
  453. goto out;
  454. /* to hit CPUs online before the notifier is up */
  455. for_each_online_cpu(lcpu) {
  456. err = threshold_create_device(lcpu);
  457. if (err)
  458. goto out;
  459. }
  460. register_cpu_notifier(&threshold_cpu_notifier);
  461. out:
  462. return err;
  463. }
  464. device_initcall(threshold_init_device);