reipl64.S 3.2 KB

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  1. /*
  2. * arch/s390/kernel/reipl.S
  3. *
  4. * S390 version
  5. * Copyright (C) 2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
  6. * Author(s): Holger Smolinski (Holger.Smolinski@de.ibm.com)
  7. Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
  8. */
  9. #include <asm/lowcore.h>
  10. .globl do_reipl
  11. do_reipl: basr %r13,0
  12. .Lpg0: lpswe .Lnewpsw-.Lpg0(%r13)
  13. .Lpg1: lctlg %c6,%c6,.Lall-.Lpg0(%r13)
  14. stctg %c0,%c0,.Lctlsave-.Lpg0(%r13)
  15. ni .Lctlsave+4-.Lpg0(%r13),0xef
  16. lctlg %c0,%c0,.Lctlsave-.Lpg0(%r13)
  17. lgr %r1,%r2
  18. mvc __LC_PGM_NEW_PSW(16),.Lpcnew-.Lpg0(%r13)
  19. stsch .Lschib-.Lpg0(%r13)
  20. oi .Lschib+5-.Lpg0(%r13),0x84
  21. .Lecs: xi .Lschib+27-.Lpg0(%r13),0x01
  22. msch .Lschib-.Lpg0(%r13)
  23. lghi %r0,5
  24. .Lssch: ssch .Liplorb-.Lpg0(%r13)
  25. jz .L001
  26. brct %r0,.Lssch
  27. bas %r14,.Ldisab-.Lpg0(%r13)
  28. .L001: mvc __LC_IO_NEW_PSW(16),.Lionew-.Lpg0(%r13)
  29. .Ltpi: lpswe .Lwaitpsw-.Lpg0(%r13)
  30. .Lcont: c %r1,__LC_SUBCHANNEL_ID
  31. jnz .Ltpi
  32. clc __LC_IO_INT_PARM(4),.Liplorb-.Lpg0(%r13)
  33. jnz .Ltpi
  34. tsch .Liplirb-.Lpg0(%r13)
  35. tm .Liplirb+9-.Lpg0(%r13),0xbf
  36. jz .L002
  37. bas %r14,.Ldisab-.Lpg0(%r13)
  38. .L002: tm .Liplirb+8-.Lpg0(%r13),0xf3
  39. jz .L003
  40. bas %r14,.Ldisab-.Lpg0(%r13)
  41. .L003: spx .Lnull-.Lpg0(%r13)
  42. st %r1,__LC_SUBCHANNEL_ID
  43. lhi %r1,0 # mode 0 = esa
  44. slr %r0,%r0 # set cpuid to zero
  45. sigp %r1,%r0,0x12 # switch to esa mode
  46. lpsw 0
  47. .Ldisab: sll %r14,1
  48. srl %r14,1 # need to kill hi bit to avoid specification exceptions.
  49. st %r14,.Ldispsw+12-.Lpg0(%r13)
  50. lpswe .Ldispsw-.Lpg0(%r13)
  51. .align 8
  52. .Lall: .quad 0x00000000ff000000
  53. .Lctlsave: .quad 0x0000000000000000
  54. .Lnull: .long 0x0000000000000000
  55. .align 16
  56. /*
  57. * These addresses have to be 31 bit otherwise
  58. * the sigp will throw a specifcation exception
  59. * when switching to ESA mode as bit 31 be set
  60. * in the ESA psw.
  61. * Bit 31 of the addresses has to be 0 for the
  62. * 31bit lpswe instruction a fact they appear to have
  63. * ommited from the pop.
  64. */
  65. .Lnewpsw: .quad 0x0000000080000000
  66. .quad .Lpg1
  67. .Lpcnew: .quad 0x0000000080000000
  68. .quad .Lecs
  69. .Lionew: .quad 0x0000000080000000
  70. .quad .Lcont
  71. .Lwaitpsw: .quad 0x0202000080000000
  72. .quad .Ltpi
  73. .Ldispsw: .quad 0x0002000080000000
  74. .quad 0x0000000000000000
  75. .Liplccws: .long 0x02000000,0x60000018
  76. .long 0x08000008,0x20000001
  77. .Liplorb: .long 0x0049504c,0x0040ff80
  78. .long 0x00000000+.Liplccws
  79. .Lschib: .long 0x00000000,0x00000000
  80. .long 0x00000000,0x00000000
  81. .long 0x00000000,0x00000000
  82. .long 0x00000000,0x00000000
  83. .long 0x00000000,0x00000000
  84. .long 0x00000000,0x00000000
  85. .Liplirb: .long 0x00000000,0x00000000
  86. .long 0x00000000,0x00000000
  87. .long 0x00000000,0x00000000
  88. .long 0x00000000,0x00000000
  89. .long 0x00000000,0x00000000
  90. .long 0x00000000,0x00000000
  91. .long 0x00000000,0x00000000
  92. .long 0x00000000,0x00000000