stx_gp3.c 8.2 KB

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  1. /*
  2. * STx GP3 board specific routines
  3. *
  4. * Dan Malek <dan@embeddededge.com>
  5. * Copyright 2004 Embedded Edge, LLC
  6. *
  7. * Copied from mpc8560_ads.c
  8. * Copyright 2002, 2003 Motorola Inc.
  9. *
  10. * Ported to 2.6, Matt Porter <mporter@kernel.crashing.org>
  11. * Copyright 2004-2005 MontaVista Software, Inc.
  12. *
  13. * This program is free software; you can redistribute it and/or modify it
  14. * under the terms of the GNU General Public License as published by the
  15. * Free Software Foundation; either version 2 of the License, or (at your
  16. * option) any later version.
  17. */
  18. #include <linux/config.h>
  19. #include <linux/stddef.h>
  20. #include <linux/kernel.h>
  21. #include <linux/init.h>
  22. #include <linux/errno.h>
  23. #include <linux/reboot.h>
  24. #include <linux/pci.h>
  25. #include <linux/kdev_t.h>
  26. #include <linux/major.h>
  27. #include <linux/blkdev.h>
  28. #include <linux/console.h>
  29. #include <linux/delay.h>
  30. #include <linux/root_dev.h>
  31. #include <linux/seq_file.h>
  32. #include <linux/serial.h>
  33. #include <linux/initrd.h>
  34. #include <linux/module.h>
  35. #include <linux/fsl_devices.h>
  36. #include <linux/interrupt.h>
  37. #include <linux/rio.h>
  38. #include <asm/system.h>
  39. #include <asm/pgtable.h>
  40. #include <asm/page.h>
  41. #include <asm/atomic.h>
  42. #include <asm/time.h>
  43. #include <asm/io.h>
  44. #include <asm/machdep.h>
  45. #include <asm/open_pic.h>
  46. #include <asm/bootinfo.h>
  47. #include <asm/pci-bridge.h>
  48. #include <asm/mpc85xx.h>
  49. #include <asm/irq.h>
  50. #include <asm/immap_85xx.h>
  51. #include <asm/cpm2.h>
  52. #include <asm/mpc85xx.h>
  53. #include <asm/ppc_sys.h>
  54. #include <syslib/cpm2_pic.h>
  55. #include <syslib/ppc85xx_common.h>
  56. #include <syslib/ppc85xx_rio.h>
  57. unsigned char __res[sizeof(bd_t)];
  58. #ifndef CONFIG_PCI
  59. unsigned long isa_io_base = 0;
  60. unsigned long isa_mem_base = 0;
  61. unsigned long pci_dram_offset = 0;
  62. #endif
  63. /* Internal interrupts are all Level Sensitive, and Positive Polarity */
  64. static u8 gp3_openpic_initsenses[] __initdata = {
  65. MPC85XX_INTERNAL_IRQ_SENSES,
  66. 0x0, /* External 0: */
  67. #if defined(CONFIG_PCI)
  68. (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI slot 0 */
  69. (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI slot 1 */
  70. (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI slot 2 */
  71. (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 4: PCI slot 3 */
  72. #else
  73. 0x0, /* External 1: */
  74. 0x0, /* External 2: */
  75. 0x0, /* External 3: */
  76. 0x0, /* External 4: */
  77. #endif
  78. 0x0, /* External 5: */
  79. 0x0, /* External 6: */
  80. 0x0, /* External 7: */
  81. 0x0, /* External 8: */
  82. 0x0, /* External 9: */
  83. 0x0, /* External 10: */
  84. 0x0, /* External 11: */
  85. };
  86. /*
  87. * Setup the architecture
  88. */
  89. static void __init
  90. gp3_setup_arch(void)
  91. {
  92. bd_t *binfo = (bd_t *) __res;
  93. unsigned int freq;
  94. struct gianfar_platform_data *pdata;
  95. struct gianfar_mdio_data *mdata;
  96. cpm2_reset();
  97. /* get the core frequency */
  98. freq = binfo->bi_intfreq;
  99. if (ppc_md.progress)
  100. ppc_md.progress("gp3_setup_arch()", 0);
  101. /* Set loops_per_jiffy to a half-way reasonable value,
  102. for use until calibrate_delay gets called. */
  103. loops_per_jiffy = freq / HZ;
  104. #ifdef CONFIG_PCI
  105. /* setup PCI host bridges */
  106. mpc85xx_setup_hose();
  107. #endif
  108. /* setup the board related info for the MDIO bus */
  109. mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
  110. mdata->irq[2] = MPC85xx_IRQ_EXT5;
  111. mdata->irq[4] = MPC85xx_IRQ_EXT5;
  112. mdata->irq[31] = -1;
  113. /* setup the board related information for the enet controllers */
  114. pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
  115. if (pdata) {
  116. /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
  117. pdata->bus_id = 0;
  118. pdata->phy_id = 2;
  119. memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
  120. }
  121. pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
  122. if (pdata) {
  123. /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
  124. pdata->bus_id = 0;
  125. pdata->phy_id = 4;
  126. memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
  127. }
  128. #ifdef CONFIG_BLK_DEV_INITRD
  129. if (initrd_start)
  130. ROOT_DEV = Root_RAM0;
  131. else
  132. #endif
  133. #ifdef CONFIG_ROOT_NFS
  134. ROOT_DEV = Root_NFS;
  135. #else
  136. ROOT_DEV = Root_HDA1;
  137. #endif
  138. printk ("bi_immr_base = %8.8lx\n", binfo->bi_immr_base);
  139. }
  140. static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
  141. {
  142. while ((irq = cpm2_get_irq(regs)) >= 0)
  143. __do_IRQ(irq, regs);
  144. return IRQ_HANDLED;
  145. }
  146. static struct irqaction cpm2_irqaction = {
  147. .handler = cpm2_cascade,
  148. .flags = SA_INTERRUPT,
  149. .mask = CPU_MASK_NONE,
  150. .name = "cpm2_cascade",
  151. };
  152. static void __init
  153. gp3_init_IRQ(void)
  154. {
  155. bd_t *binfo = (bd_t *) __res;
  156. /*
  157. * Setup OpenPIC
  158. */
  159. /* Determine the Physical Address of the OpenPIC regs */
  160. phys_addr_t OpenPIC_PAddr =
  161. binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
  162. OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
  163. OpenPIC_InitSenses = gp3_openpic_initsenses;
  164. OpenPIC_NumInitSenses = sizeof (gp3_openpic_initsenses);
  165. /* Skip reserved space and internal sources */
  166. openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
  167. /* Map PIC IRQs 0-11 */
  168. openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
  169. /*
  170. * Let openpic interrupts starting from an offset, to
  171. * leave space for cascading interrupts underneath.
  172. */
  173. openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
  174. /* Setup CPM2 PIC */
  175. cpm2_init_IRQ();
  176. setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
  177. return;
  178. }
  179. static int
  180. gp3_show_cpuinfo(struct seq_file *m)
  181. {
  182. uint pvid, svid, phid1;
  183. bd_t *binfo = (bd_t *) __res;
  184. uint memsize;
  185. unsigned int freq;
  186. extern unsigned long total_memory; /* in mm/init */
  187. /* get the core frequency */
  188. freq = binfo->bi_intfreq;
  189. pvid = mfspr(SPRN_PVR);
  190. svid = mfspr(SPRN_SVR);
  191. memsize = total_memory;
  192. seq_printf(m, "Vendor\t\t: RPC Electronics STx \n");
  193. seq_printf(m, "Machine\t\t: GP3 - MPC%s\n", cur_ppc_sys_spec->ppc_sys_name);
  194. seq_printf(m, "bus freq\t: %u.%.6u MHz\n", freq / 1000000,
  195. freq % 1000000);
  196. seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
  197. seq_printf(m, "SVR\t\t: 0x%x\n", svid);
  198. /* Display cpu Pll setting */
  199. phid1 = mfspr(SPRN_HID1);
  200. seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
  201. /* Display the amount of memory */
  202. seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
  203. return 0;
  204. }
  205. #ifdef CONFIG_PCI
  206. int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel,
  207. unsigned char pin)
  208. {
  209. static char pci_irq_table[][4] =
  210. /*
  211. * PCI IDSEL/INTPIN->INTLINE
  212. * A B C D
  213. */
  214. {
  215. {PIRQA, PIRQB, PIRQC, PIRQD},
  216. {PIRQD, PIRQA, PIRQB, PIRQC},
  217. {PIRQC, PIRQD, PIRQA, PIRQB},
  218. {PIRQB, PIRQC, PIRQD, PIRQA},
  219. };
  220. const long min_idsel = 12, max_idsel = 15, irqs_per_slot = 4;
  221. return PCI_IRQ_TABLE_LOOKUP;
  222. }
  223. int mpc85xx_exclude_device(u_char bus, u_char devfn)
  224. {
  225. if (bus == 0 && PCI_SLOT(devfn) == 0)
  226. return PCIBIOS_DEVICE_NOT_FOUND;
  227. else
  228. return PCIBIOS_SUCCESSFUL;
  229. }
  230. #endif /* CONFIG_PCI */
  231. #ifdef CONFIG_RAPIDIO
  232. void
  233. platform_rio_init(void)
  234. {
  235. /*
  236. * The STx firmware configures the RapidIO Local Access Window
  237. * at 0xc0000000 with a size of 512MB.
  238. */
  239. mpc85xx_rio_setup(0xc0000000, 0x20000000);
  240. }
  241. #endif /* CONFIG_RAPIDIO */
  242. void __init
  243. platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
  244. unsigned long r6, unsigned long r7)
  245. {
  246. /* parse_bootinfo must always be called first */
  247. parse_bootinfo(find_bootinfo());
  248. /*
  249. * If we were passed in a board information, copy it into the
  250. * residual data area.
  251. */
  252. if (r3) {
  253. memcpy((void *) __res, (void *) (r3 + KERNELBASE),
  254. sizeof (bd_t));
  255. }
  256. #if defined(CONFIG_BLK_DEV_INITRD)
  257. /*
  258. * If the init RAM disk has been configured in, and there's a valid
  259. * starting address for it, set it up.
  260. */
  261. if (r4) {
  262. initrd_start = r4 + KERNELBASE;
  263. initrd_end = r5 + KERNELBASE;
  264. }
  265. #endif /* CONFIG_BLK_DEV_INITRD */
  266. /* Copy the kernel command line arguments to a safe place. */
  267. if (r6) {
  268. *(char *) (r7 + KERNELBASE) = 0;
  269. strcpy(cmd_line, (char *) (r6 + KERNELBASE));
  270. }
  271. identify_ppc_sys_by_id(mfspr(SPRN_SVR));
  272. /* setup the PowerPC module struct */
  273. ppc_md.setup_arch = gp3_setup_arch;
  274. ppc_md.show_cpuinfo = gp3_show_cpuinfo;
  275. ppc_md.init_IRQ = gp3_init_IRQ;
  276. ppc_md.get_irq = openpic_get_irq;
  277. ppc_md.restart = mpc85xx_restart;
  278. ppc_md.power_off = mpc85xx_power_off;
  279. ppc_md.halt = mpc85xx_halt;
  280. ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
  281. ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
  282. if (ppc_md.progress)
  283. ppc_md.progress("platform_init(): exit", 0);
  284. return;
  285. }