mpc85xx_cds_common.c 16 KB

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  1. /*
  2. * MPC85xx CDS board specific routines
  3. *
  4. * Maintainer: Kumar Gala <galak@kernel.crashing.org>
  5. *
  6. * Copyright 2004 Freescale Semiconductor, Inc
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #include <linux/config.h>
  14. #include <linux/stddef.h>
  15. #include <linux/kernel.h>
  16. #include <linux/init.h>
  17. #include <linux/errno.h>
  18. #include <linux/reboot.h>
  19. #include <linux/pci.h>
  20. #include <linux/kdev_t.h>
  21. #include <linux/major.h>
  22. #include <linux/console.h>
  23. #include <linux/delay.h>
  24. #include <linux/seq_file.h>
  25. #include <linux/serial.h>
  26. #include <linux/module.h>
  27. #include <linux/root_dev.h>
  28. #include <linux/initrd.h>
  29. #include <linux/tty.h>
  30. #include <linux/serial_core.h>
  31. #include <linux/fsl_devices.h>
  32. #include <asm/system.h>
  33. #include <asm/pgtable.h>
  34. #include <asm/page.h>
  35. #include <asm/atomic.h>
  36. #include <asm/time.h>
  37. #include <asm/todc.h>
  38. #include <asm/io.h>
  39. #include <asm/machdep.h>
  40. #include <asm/open_pic.h>
  41. #include <asm/i8259.h>
  42. #include <asm/bootinfo.h>
  43. #include <asm/pci-bridge.h>
  44. #include <asm/mpc85xx.h>
  45. #include <asm/irq.h>
  46. #include <asm/immap_85xx.h>
  47. #include <asm/cpm2.h>
  48. #include <asm/ppc_sys.h>
  49. #include <asm/kgdb.h>
  50. #include <mm/mmu_decl.h>
  51. #include <syslib/cpm2_pic.h>
  52. #include <syslib/ppc85xx_common.h>
  53. #include <syslib/ppc85xx_setup.h>
  54. #ifndef CONFIG_PCI
  55. unsigned long isa_io_base = 0;
  56. unsigned long isa_mem_base = 0;
  57. #endif
  58. extern unsigned long total_memory; /* in mm/init */
  59. unsigned char __res[sizeof (bd_t)];
  60. static int cds_pci_slot = 2;
  61. static volatile u8 * cadmus;
  62. /* Internal interrupts are all Level Sensitive, and Positive Polarity */
  63. static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
  64. MPC85XX_INTERNAL_IRQ_SENSES,
  65. #if defined(CONFIG_PCI)
  66. (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */
  67. (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */
  68. (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI1 slot */
  69. (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI1 slot */
  70. #else
  71. 0x0, /* External 0: */
  72. 0x0, /* External 1: */
  73. 0x0, /* External 2: */
  74. 0x0, /* External 3: */
  75. #endif
  76. 0x0, /* External 4: */
  77. (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
  78. 0x0, /* External 6: */
  79. 0x0, /* External 7: */
  80. 0x0, /* External 8: */
  81. 0x0, /* External 9: */
  82. 0x0, /* External 10: */
  83. #if defined(CONFIG_85xx_PCI2) && defined(CONFIG_PCI)
  84. (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 11: PCI2 slot 0 */
  85. #else
  86. 0x0, /* External 11: */
  87. #endif
  88. };
  89. /* ************************************************************************ */
  90. int
  91. mpc85xx_cds_show_cpuinfo(struct seq_file *m)
  92. {
  93. uint pvid, svid, phid1;
  94. uint memsize = total_memory;
  95. bd_t *binfo = (bd_t *) __res;
  96. unsigned int freq;
  97. /* get the core frequency */
  98. freq = binfo->bi_intfreq;
  99. pvid = mfspr(SPRN_PVR);
  100. svid = mfspr(SPRN_SVR);
  101. seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
  102. seq_printf(m, "Machine\t\t: CDS - MPC%s (%x)\n", cur_ppc_sys_spec->ppc_sys_name, cadmus[CM_VER]);
  103. seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
  104. seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
  105. seq_printf(m, "SVR\t\t: 0x%x\n", svid);
  106. /* Display cpu Pll setting */
  107. phid1 = mfspr(SPRN_HID1);
  108. seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
  109. /* Display the amount of memory */
  110. seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
  111. return 0;
  112. }
  113. #ifdef CONFIG_CPM2
  114. static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
  115. {
  116. while((irq = cpm2_get_irq(regs)) >= 0)
  117. __do_IRQ(irq, regs);
  118. return IRQ_HANDLED;
  119. }
  120. static struct irqaction cpm2_irqaction = {
  121. .handler = cpm2_cascade,
  122. .flags = SA_INTERRUPT,
  123. .mask = CPU_MASK_NONE,
  124. .name = "cpm2_cascade",
  125. };
  126. #endif /* CONFIG_CPM2 */
  127. void __init
  128. mpc85xx_cds_init_IRQ(void)
  129. {
  130. bd_t *binfo = (bd_t *) __res;
  131. int i;
  132. /* Determine the Physical Address of the OpenPIC regs */
  133. phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
  134. OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
  135. OpenPIC_InitSenses = mpc85xx_cds_openpic_initsenses;
  136. OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses);
  137. /* Skip reserved space and internal sources */
  138. #ifdef CONFIG_MPC8548
  139. openpic_set_sources(0, 48, OpenPIC_Addr + 0x10200);
  140. #else
  141. openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
  142. #endif
  143. /* Map PIC IRQs 0-11 */
  144. openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
  145. /* we let openpic interrupts starting from an offset, to
  146. * leave space for cascading interrupts underneath.
  147. */
  148. openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
  149. #ifdef CONFIG_PCI
  150. openpic_hookup_cascade(PIRQ0A, "82c59 cascade", i8259_irq);
  151. i8259_init(0, 0);
  152. #endif
  153. #ifdef CONFIG_CPM2
  154. /* Setup CPM2 PIC */
  155. cpm2_init_IRQ();
  156. setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
  157. #endif
  158. return;
  159. }
  160. #ifdef CONFIG_PCI
  161. /*
  162. * interrupt routing
  163. */
  164. int
  165. mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  166. {
  167. struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
  168. if (!hose->index)
  169. {
  170. /* Handle PCI1 interrupts */
  171. char pci_irq_table[][4] =
  172. /*
  173. * PCI IDSEL/INTPIN->INTLINE
  174. * A B C D
  175. */
  176. /* Note IRQ assignment for slots is based on which slot the elysium is
  177. * in -- in this setup elysium is in slot #2 (this PIRQA as first
  178. * interrupt on slot */
  179. {
  180. { 0, 1, 2, 3 }, /* 16 - PMC */
  181. { 0, 1, 2, 3 }, /* 17 P2P (Tsi320) */
  182. { 0, 1, 2, 3 }, /* 18 - Slot 1 */
  183. { 1, 2, 3, 0 }, /* 19 - Slot 2 */
  184. { 2, 3, 0, 1 }, /* 20 - Slot 3 */
  185. { 3, 0, 1, 2 }, /* 21 - Slot 4 */
  186. };
  187. const long min_idsel = 16, max_idsel = 21, irqs_per_slot = 4;
  188. int i, j;
  189. for (i = 0; i < 6; i++)
  190. for (j = 0; j < 4; j++)
  191. pci_irq_table[i][j] =
  192. ((pci_irq_table[i][j] + 5 -
  193. cds_pci_slot) & 0x3) + PIRQ0A;
  194. return PCI_IRQ_TABLE_LOOKUP;
  195. } else {
  196. /* Handle PCI2 interrupts (if we have one) */
  197. char pci_irq_table[][4] =
  198. {
  199. /*
  200. * We only have one slot and one interrupt
  201. * going to PIRQA - PIRQD */
  202. { PIRQ1A, PIRQ1A, PIRQ1A, PIRQ1A }, /* 21 - slot 0 */
  203. };
  204. const long min_idsel = 21, max_idsel = 21, irqs_per_slot = 4;
  205. return PCI_IRQ_TABLE_LOOKUP;
  206. }
  207. }
  208. #define ARCADIA_HOST_BRIDGE_IDSEL 17
  209. #define ARCADIA_2ND_BRIDGE_IDSEL 3
  210. extern int mpc85xx_pci1_last_busno;
  211. int
  212. mpc85xx_exclude_device(u_char bus, u_char devfn)
  213. {
  214. if (bus == 0 && PCI_SLOT(devfn) == 0)
  215. return PCIBIOS_DEVICE_NOT_FOUND;
  216. #ifdef CONFIG_85xx_PCI2
  217. if (mpc85xx_pci1_last_busno)
  218. if (bus == (mpc85xx_pci1_last_busno + 1) && PCI_SLOT(devfn) == 0)
  219. return PCIBIOS_DEVICE_NOT_FOUND;
  220. #endif
  221. /* We explicitly do not go past the Tundra 320 Bridge */
  222. if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
  223. return PCIBIOS_DEVICE_NOT_FOUND;
  224. if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
  225. return PCIBIOS_DEVICE_NOT_FOUND;
  226. else
  227. return PCIBIOS_SUCCESSFUL;
  228. }
  229. void __init
  230. mpc85xx_cds_enable_via(struct pci_controller *hose)
  231. {
  232. u32 pci_class;
  233. u16 vid, did;
  234. early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
  235. if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
  236. return;
  237. /* Configure P2P so that we can reach bus 1 */
  238. early_write_config_byte(hose, 0, 0x88, PCI_PRIMARY_BUS, 0);
  239. early_write_config_byte(hose, 0, 0x88, PCI_SECONDARY_BUS, 1);
  240. early_write_config_byte(hose, 0, 0x88, PCI_SUBORDINATE_BUS, 0xff);
  241. early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
  242. early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
  243. if ((vid != PCI_VENDOR_ID_VIA) ||
  244. (did != PCI_DEVICE_ID_VIA_82C686))
  245. return;
  246. /* Enable USB and IDE functions */
  247. early_write_config_byte(hose, 1, 0x10, 0x48, 0x08);
  248. }
  249. void __init
  250. mpc85xx_cds_fixup_via(struct pci_controller *hose)
  251. {
  252. u32 pci_class;
  253. u16 vid, did;
  254. early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
  255. if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
  256. return;
  257. /*
  258. * Force the backplane P2P bridge to have a window
  259. * open from 0x00000000-0x00001fff in PCI I/O space.
  260. * This allows legacy I/O (i8259, etc) on the VIA
  261. * southbridge to be accessed.
  262. */
  263. early_write_config_byte(hose, 0, 0x88, PCI_IO_BASE, 0x00);
  264. early_write_config_word(hose, 0, 0x88, PCI_IO_BASE_UPPER16, 0x0000);
  265. early_write_config_byte(hose, 0, 0x88, PCI_IO_LIMIT, 0x10);
  266. early_write_config_word(hose, 0, 0x88, PCI_IO_LIMIT_UPPER16, 0x0000);
  267. early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
  268. early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
  269. if ((vid != PCI_VENDOR_ID_VIA) ||
  270. (did != PCI_DEVICE_ID_VIA_82C686))
  271. return;
  272. /*
  273. * Since the P2P window was forced to cover the fixed
  274. * legacy I/O addresses, it is necessary to manually
  275. * place the base addresses for the IDE and USB functions
  276. * within this window.
  277. */
  278. /* Function 1, IDE */
  279. early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_0, 0x1ff8);
  280. early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_1, 0x1ff4);
  281. early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_2, 0x1fe8);
  282. early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_3, 0x1fe4);
  283. early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_4, 0x1fd0);
  284. /* Function 2, USB ports 0-1 */
  285. early_write_config_dword(hose, 1, 0x12, PCI_BASE_ADDRESS_4, 0x1fa0);
  286. /* Function 3, USB ports 2-3 */
  287. early_write_config_dword(hose, 1, 0x13, PCI_BASE_ADDRESS_4, 0x1f80);
  288. /* Function 5, Power Management */
  289. early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_0, 0x1e00);
  290. early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_1, 0x1dfc);
  291. early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_2, 0x1df8);
  292. /* Function 6, AC97 Interface */
  293. early_write_config_dword(hose, 1, 0x16, PCI_BASE_ADDRESS_0, 0x1c00);
  294. }
  295. void __init
  296. mpc85xx_cds_pcibios_fixup(void)
  297. {
  298. struct pci_dev *dev;
  299. u_char c;
  300. if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
  301. PCI_DEVICE_ID_VIA_82C586_1, NULL))) {
  302. /*
  303. * U-Boot does not set the enable bits
  304. * for the IDE device. Force them on here.
  305. */
  306. pci_read_config_byte(dev, 0x40, &c);
  307. c |= 0x03; /* IDE: Chip Enable Bits */
  308. pci_write_config_byte(dev, 0x40, c);
  309. /*
  310. * Since only primary interface works, force the
  311. * IDE function to standard primary IDE interrupt
  312. * w/ 8259 offset
  313. */
  314. dev->irq = 14;
  315. pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
  316. pci_dev_put(dev);
  317. }
  318. /*
  319. * Force legacy USB interrupt routing
  320. */
  321. if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
  322. PCI_DEVICE_ID_VIA_82C586_2, NULL))) {
  323. dev->irq = 10;
  324. pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10);
  325. pci_dev_put(dev);
  326. }
  327. if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
  328. PCI_DEVICE_ID_VIA_82C586_2, dev))) {
  329. dev->irq = 11;
  330. pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
  331. pci_dev_put(dev);
  332. }
  333. }
  334. #endif /* CONFIG_PCI */
  335. TODC_ALLOC();
  336. /* ************************************************************************
  337. *
  338. * Setup the architecture
  339. *
  340. */
  341. static void __init
  342. mpc85xx_cds_setup_arch(void)
  343. {
  344. bd_t *binfo = (bd_t *) __res;
  345. unsigned int freq;
  346. struct gianfar_platform_data *pdata;
  347. struct gianfar_mdio_data *mdata;
  348. /* get the core frequency */
  349. freq = binfo->bi_intfreq;
  350. printk("mpc85xx_cds_setup_arch\n");
  351. #ifdef CONFIG_CPM2
  352. cpm2_reset();
  353. #endif
  354. cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
  355. cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
  356. printk("CDS Version = %x in PCI slot %d\n", cadmus[CM_VER], cds_pci_slot);
  357. /* Setup TODC access */
  358. TODC_INIT(TODC_TYPE_DS1743,
  359. 0,
  360. 0,
  361. ioremap(CDS_RTC_ADDR, CDS_RTC_SIZE),
  362. 8);
  363. /* Set loops_per_jiffy to a half-way reasonable value,
  364. for use until calibrate_delay gets called. */
  365. loops_per_jiffy = freq / HZ;
  366. #ifdef CONFIG_PCI
  367. /* VIA IDE configuration */
  368. ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup;
  369. /* setup PCI host bridges */
  370. mpc85xx_setup_hose();
  371. #endif
  372. #ifdef CONFIG_SERIAL_8250
  373. mpc85xx_early_serial_map();
  374. #endif
  375. #ifdef CONFIG_SERIAL_TEXT_DEBUG
  376. /* Invalidate the entry we stole earlier the serial ports
  377. * should be properly mapped */
  378. invalidate_tlbcam_entry(num_tlbcam_entries - 1);
  379. #endif
  380. /* setup the board related info for the MDIO bus */
  381. mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
  382. mdata->irq[0] = MPC85xx_IRQ_EXT5;
  383. mdata->irq[1] = MPC85xx_IRQ_EXT5;
  384. mdata->irq[2] = -1;
  385. mdata->irq[3] = -1;
  386. mdata->irq[31] = -1;
  387. /* setup the board related information for the enet controllers */
  388. pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
  389. if (pdata) {
  390. pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
  391. pdata->bus_id = 0;
  392. pdata->phy_id = 0;
  393. memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
  394. }
  395. pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
  396. if (pdata) {
  397. pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
  398. pdata->bus_id = 0;
  399. pdata->phy_id = 1;
  400. memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
  401. }
  402. pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC1);
  403. if (pdata) {
  404. pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
  405. pdata->bus_id = 0;
  406. pdata->phy_id = 0;
  407. memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
  408. }
  409. pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC2);
  410. if (pdata) {
  411. pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
  412. pdata->bus_id = 0;
  413. pdata->phy_id = 1;
  414. memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
  415. }
  416. ppc_sys_device_remove(MPC85xx_eTSEC3);
  417. ppc_sys_device_remove(MPC85xx_eTSEC4);
  418. #ifdef CONFIG_BLK_DEV_INITRD
  419. if (initrd_start)
  420. ROOT_DEV = Root_RAM0;
  421. else
  422. #endif
  423. #ifdef CONFIG_ROOT_NFS
  424. ROOT_DEV = Root_NFS;
  425. #else
  426. ROOT_DEV = Root_HDA1;
  427. #endif
  428. }
  429. /* ************************************************************************ */
  430. void __init
  431. platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
  432. unsigned long r6, unsigned long r7)
  433. {
  434. /* parse_bootinfo must always be called first */
  435. parse_bootinfo(find_bootinfo());
  436. /*
  437. * If we were passed in a board information, copy it into the
  438. * residual data area.
  439. */
  440. if (r3) {
  441. memcpy((void *) __res, (void *) (r3 + KERNELBASE),
  442. sizeof (bd_t));
  443. }
  444. #ifdef CONFIG_SERIAL_TEXT_DEBUG
  445. {
  446. bd_t *binfo = (bd_t *) __res;
  447. struct uart_port p;
  448. /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
  449. settlbcam(num_tlbcam_entries - 1, binfo->bi_immr_base,
  450. binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
  451. memset(&p, 0, sizeof (p));
  452. p.iotype = UPIO_MEM;
  453. p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
  454. p.uartclk = binfo->bi_busfreq;
  455. gen550_init(0, &p);
  456. memset(&p, 0, sizeof (p));
  457. p.iotype = UPIO_MEM;
  458. p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
  459. p.uartclk = binfo->bi_busfreq;
  460. gen550_init(1, &p);
  461. }
  462. #endif
  463. #if defined(CONFIG_BLK_DEV_INITRD)
  464. /*
  465. * If the init RAM disk has been configured in, and there's a valid
  466. * starting address for it, set it up.
  467. */
  468. if (r4) {
  469. initrd_start = r4 + KERNELBASE;
  470. initrd_end = r5 + KERNELBASE;
  471. }
  472. #endif /* CONFIG_BLK_DEV_INITRD */
  473. /* Copy the kernel command line arguments to a safe place. */
  474. if (r6) {
  475. *(char *) (r7 + KERNELBASE) = 0;
  476. strcpy(cmd_line, (char *) (r6 + KERNELBASE));
  477. }
  478. identify_ppc_sys_by_id(mfspr(SPRN_SVR));
  479. /* setup the PowerPC module struct */
  480. ppc_md.setup_arch = mpc85xx_cds_setup_arch;
  481. ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo;
  482. ppc_md.init_IRQ = mpc85xx_cds_init_IRQ;
  483. ppc_md.get_irq = openpic_get_irq;
  484. ppc_md.restart = mpc85xx_restart;
  485. ppc_md.power_off = mpc85xx_power_off;
  486. ppc_md.halt = mpc85xx_halt;
  487. ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
  488. ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
  489. ppc_md.time_init = todc_time_init;
  490. ppc_md.set_rtc_time = todc_set_rtc_time;
  491. ppc_md.get_rtc_time = todc_get_rtc_time;
  492. ppc_md.nvram_read_val = todc_direct_read_val;
  493. ppc_md.nvram_write_val = todc_direct_write_val;
  494. #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
  495. ppc_md.progress = gen550_progress;
  496. #endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
  497. #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
  498. ppc_md.early_serial_map = mpc85xx_early_serial_map;
  499. #endif /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
  500. if (ppc_md.progress)
  501. ppc_md.progress("mpc85xx_cds_init(): exit", 0);
  502. return;
  503. }