mpc85xx_ads_common.c 5.3 KB

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  1. /*
  2. * MPC85xx ADS board common routines
  3. *
  4. * Maintainer: Kumar Gala <galak@kernel.crashing.org>
  5. *
  6. * Copyright 2004 Freescale Semiconductor Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #include <linux/config.h>
  14. #include <linux/stddef.h>
  15. #include <linux/kernel.h>
  16. #include <linux/init.h>
  17. #include <linux/errno.h>
  18. #include <linux/reboot.h>
  19. #include <linux/pci.h>
  20. #include <linux/kdev_t.h>
  21. #include <linux/major.h>
  22. #include <linux/console.h>
  23. #include <linux/delay.h>
  24. #include <linux/seq_file.h>
  25. #include <linux/serial.h>
  26. #include <linux/module.h>
  27. #include <asm/system.h>
  28. #include <asm/pgtable.h>
  29. #include <asm/page.h>
  30. #include <asm/atomic.h>
  31. #include <asm/time.h>
  32. #include <asm/io.h>
  33. #include <asm/machdep.h>
  34. #include <asm/open_pic.h>
  35. #include <asm/bootinfo.h>
  36. #include <asm/pci-bridge.h>
  37. #include <asm/mpc85xx.h>
  38. #include <asm/irq.h>
  39. #include <asm/immap_85xx.h>
  40. #include <asm/ppc_sys.h>
  41. #include <mm/mmu_decl.h>
  42. #include <syslib/ppc85xx_rio.h>
  43. #include <platforms/85xx/mpc85xx_ads_common.h>
  44. #ifndef CONFIG_PCI
  45. unsigned long isa_io_base = 0;
  46. unsigned long isa_mem_base = 0;
  47. #endif
  48. extern unsigned long total_memory; /* in mm/init */
  49. unsigned char __res[sizeof (bd_t)];
  50. /* Internal interrupts are all Level Sensitive, and Positive Polarity */
  51. static u_char mpc85xx_ads_openpic_initsenses[] __initdata = {
  52. MPC85XX_INTERNAL_IRQ_SENSES,
  53. 0x0, /* External 0: */
  54. #if defined(CONFIG_PCI)
  55. (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI slot 0 */
  56. (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI slot 1 */
  57. (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI slot 2 */
  58. (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 4: PCI slot 3 */
  59. #else
  60. 0x0, /* External 1: */
  61. 0x0, /* External 2: */
  62. 0x0, /* External 3: */
  63. 0x0, /* External 4: */
  64. #endif
  65. (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
  66. 0x0, /* External 6: */
  67. (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 7: PHY */
  68. 0x0, /* External 8: */
  69. 0x0, /* External 9: */
  70. 0x0, /* External 10: */
  71. 0x0, /* External 11: */
  72. };
  73. /* ************************************************************************ */
  74. int
  75. mpc85xx_ads_show_cpuinfo(struct seq_file *m)
  76. {
  77. uint pvid, svid, phid1;
  78. uint memsize = total_memory;
  79. bd_t *binfo = (bd_t *) __res;
  80. unsigned int freq;
  81. /* get the core frequency */
  82. freq = binfo->bi_intfreq;
  83. pvid = mfspr(SPRN_PVR);
  84. svid = mfspr(SPRN_SVR);
  85. seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
  86. seq_printf(m, "Machine\t\t: mpc%sads\n", cur_ppc_sys_spec->ppc_sys_name);
  87. seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
  88. seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
  89. seq_printf(m, "SVR\t\t: 0x%x\n", svid);
  90. /* Display cpu Pll setting */
  91. phid1 = mfspr(SPRN_HID1);
  92. seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
  93. /* Display the amount of memory */
  94. seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
  95. return 0;
  96. }
  97. void __init
  98. mpc85xx_ads_init_IRQ(void)
  99. {
  100. bd_t *binfo = (bd_t *) __res;
  101. /* Determine the Physical Address of the OpenPIC regs */
  102. phys_addr_t OpenPIC_PAddr =
  103. binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
  104. OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
  105. OpenPIC_InitSenses = mpc85xx_ads_openpic_initsenses;
  106. OpenPIC_NumInitSenses = sizeof (mpc85xx_ads_openpic_initsenses);
  107. /* Skip reserved space and internal sources */
  108. openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
  109. /* Map PIC IRQs 0-11 */
  110. openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
  111. /* we let openpic interrupts starting from an offset, to
  112. * leave space for cascading interrupts underneath.
  113. */
  114. openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
  115. return;
  116. }
  117. #ifdef CONFIG_PCI
  118. /*
  119. * interrupt routing
  120. */
  121. int
  122. mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  123. {
  124. static char pci_irq_table[][4] =
  125. /*
  126. * This is little evil, but works around the fact
  127. * that revA boards have IDSEL starting at 18
  128. * and others boards (older) start at 12
  129. *
  130. * PCI IDSEL/INTPIN->INTLINE
  131. * A B C D
  132. */
  133. {
  134. {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 2 */
  135. {PIRQD, PIRQA, PIRQB, PIRQC},
  136. {PIRQC, PIRQD, PIRQA, PIRQB},
  137. {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 5 */
  138. {0, 0, 0, 0}, /* -- */
  139. {0, 0, 0, 0}, /* -- */
  140. {0, 0, 0, 0}, /* -- */
  141. {0, 0, 0, 0}, /* -- */
  142. {0, 0, 0, 0}, /* -- */
  143. {0, 0, 0, 0}, /* -- */
  144. {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 12 */
  145. {PIRQD, PIRQA, PIRQB, PIRQC},
  146. {PIRQC, PIRQD, PIRQA, PIRQB},
  147. {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 15 */
  148. {0, 0, 0, 0}, /* -- */
  149. {0, 0, 0, 0}, /* -- */
  150. {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 18 */
  151. {PIRQD, PIRQA, PIRQB, PIRQC},
  152. {PIRQC, PIRQD, PIRQA, PIRQB},
  153. {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 21 */
  154. };
  155. const long min_idsel = 2, max_idsel = 21, irqs_per_slot = 4;
  156. return PCI_IRQ_TABLE_LOOKUP;
  157. }
  158. int
  159. mpc85xx_exclude_device(u_char bus, u_char devfn)
  160. {
  161. if (bus == 0 && PCI_SLOT(devfn) == 0)
  162. return PCIBIOS_DEVICE_NOT_FOUND;
  163. else
  164. return PCIBIOS_SUCCESSFUL;
  165. }
  166. #endif /* CONFIG_PCI */
  167. #ifdef CONFIG_RAPIDIO
  168. void platform_rio_init(void)
  169. {
  170. /* 512MB RIO LAW at 0xc0000000 */
  171. mpc85xx_rio_setup(0xc0000000, 0x20000000);
  172. }
  173. #endif /* CONFIG_RAPIDIO */