head.S 3.3 KB

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  1. /*
  2. * Initial board bringup code for many different boards.
  3. *
  4. * Author: Tom Rini
  5. * trini@mvista.com
  6. * Derived from arch/ppc/boot/prep/head.S (Cort Dougan, many others).
  7. *
  8. * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
  9. * the terms of the GNU General Public License version 2. This program
  10. * is licensed "as is" without any warranty of any kind, whether express
  11. * or implied.
  12. */
  13. #include <linux/config.h>
  14. #include <asm/reg.h>
  15. #include <asm/cache.h>
  16. #include <asm/ppc_asm.h>
  17. .text
  18. /*
  19. * Begin at some arbitrary location in RAM or Flash
  20. * Initialize core registers
  21. * Configure memory controller (Not executing from RAM)
  22. * Move the boot code to the link address (8M)
  23. * Setup C stack
  24. * Initialize UART
  25. * Decompress the kernel to 0x0
  26. * Jump to the kernel entry
  27. *
  28. */
  29. .globl start
  30. start:
  31. bl start_
  32. #ifdef CONFIG_IBM_OPENBIOS
  33. /* The IBM "Tree" bootrom knows that the address of the bootrom
  34. * read only structure is 4 bytes after _start.
  35. */
  36. .long 0x62726f6d # structure ID - "brom"
  37. .long 0x5f726f00 # - "_ro\0"
  38. .long 1 # structure version
  39. .long bootrom_cmdline # address of *bootrom_cmdline
  40. #endif
  41. start_:
  42. #ifdef CONFIG_FORCE
  43. /* We have some really bad firmware. We must disable the L1
  44. * icache/dcache now or the board won't boot.
  45. */
  46. li r4,0x0000
  47. isync
  48. mtspr SPRN_HID0,r4
  49. sync
  50. isync
  51. #endif
  52. #if defined(CONFIG_MBX) || defined(CONFIG_RPX8260) || defined(CONFIG_PPC_PREP)
  53. mr r29,r3 /* On the MBX860, r3 is the board info pointer.
  54. * On the RPXSUPER, r3 points to the NVRAM
  55. * configuration keys.
  56. * On PReP, r3 is the pointer to the residual data.
  57. */
  58. #endif
  59. #if defined(CONFIG_XILINX_VIRTEX_4_FX)
  60. /* PPC errata 213: only for Virtex-4 FX */
  61. mfccr0 0
  62. oris 0,0,0x50000000@h
  63. mtccr0 0
  64. #endif
  65. mflr r3 /* Save our actual starting address. */
  66. /* The following functions we call must not modify r3 or r4.....
  67. */
  68. #ifdef CONFIG_6xx
  69. /* On PReP we must look at the OpenFirmware pointer and sanity
  70. * test it. On other platforms, we disable the MMU right now
  71. * and other bits.
  72. */
  73. #ifdef CONFIG_PPC_PREP
  74. /*
  75. * Save the OF pointer to r25, but only if the entry point is in a sane
  76. * location; if not we store 0. If there is no entry point, or it is
  77. * invalid, we establish the default MSR value immediately. Otherwise,
  78. * we defer doing that, to allow OF functions to be called, until we
  79. * begin uncompressing the kernel.
  80. */
  81. lis r8,0x0fff /* r8 = 0x0fffffff */
  82. ori r8,r8,0xffff
  83. subc r8,r8,r5 /* r8 = (r5 <= r8) ? ~0 : 0 */
  84. subfe r8,r8,r8
  85. nand r8,r8,r8
  86. and. r5,r5,r8 /* r5 will be cleared if (r5 > r8) */
  87. bne+ haveOF
  88. li r8,MSR_IP|MSR_FP /* Not OF: set MSR immediately */
  89. mtmsr r8
  90. isync
  91. haveOF:
  92. mr r25,r5
  93. #else
  94. bl disable_6xx_mmu
  95. #endif
  96. bl disable_6xx_l1cache
  97. CLEAR_CACHES
  98. #endif
  99. #ifdef CONFIG_8xx
  100. mfmsr r8 /* Turn off interrupts */
  101. li r9,0
  102. ori r9,r9,MSR_EE
  103. andc r8,r8,r9
  104. mtmsr r8
  105. /* We do this because some boot roms don't initialize the
  106. * processor correctly. Don't do this if you want to debug
  107. * using a BDM device.
  108. */
  109. li r4,0 /* Zero DER to prevent FRZ */
  110. mtspr SPRN_DER,r4
  111. #endif
  112. #if defined(CONFIG_MBX) || defined(CONFIG_RPX8260) || defined(CONFIG_PPC_PREP)
  113. mr r4,r29 /* put the board info pointer where the relocate
  114. * routine will find it
  115. */
  116. #endif
  117. /* Get the load address.
  118. */
  119. subi r3, r3, 4 /* Get the actual IP, not NIP */
  120. b relocate