eeh.c 29 KB

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  1. /*
  2. * eeh.c
  3. * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/delay.h>
  20. #include <linux/init.h>
  21. #include <linux/list.h>
  22. #include <linux/pci.h>
  23. #include <linux/proc_fs.h>
  24. #include <linux/rbtree.h>
  25. #include <linux/seq_file.h>
  26. #include <linux/spinlock.h>
  27. #include <asm/atomic.h>
  28. #include <asm/eeh.h>
  29. #include <asm/eeh_event.h>
  30. #include <asm/io.h>
  31. #include <asm/machdep.h>
  32. #include <asm/ppc-pci.h>
  33. #include <asm/rtas.h>
  34. #undef DEBUG
  35. /** Overview:
  36. * EEH, or "Extended Error Handling" is a PCI bridge technology for
  37. * dealing with PCI bus errors that can't be dealt with within the
  38. * usual PCI framework, except by check-stopping the CPU. Systems
  39. * that are designed for high-availability/reliability cannot afford
  40. * to crash due to a "mere" PCI error, thus the need for EEH.
  41. * An EEH-capable bridge operates by converting a detected error
  42. * into a "slot freeze", taking the PCI adapter off-line, making
  43. * the slot behave, from the OS'es point of view, as if the slot
  44. * were "empty": all reads return 0xff's and all writes are silently
  45. * ignored. EEH slot isolation events can be triggered by parity
  46. * errors on the address or data busses (e.g. during posted writes),
  47. * which in turn might be caused by low voltage on the bus, dust,
  48. * vibration, humidity, radioactivity or plain-old failed hardware.
  49. *
  50. * Note, however, that one of the leading causes of EEH slot
  51. * freeze events are buggy device drivers, buggy device microcode,
  52. * or buggy device hardware. This is because any attempt by the
  53. * device to bus-master data to a memory address that is not
  54. * assigned to the device will trigger a slot freeze. (The idea
  55. * is to prevent devices-gone-wild from corrupting system memory).
  56. * Buggy hardware/drivers will have a miserable time co-existing
  57. * with EEH.
  58. *
  59. * Ideally, a PCI device driver, when suspecting that an isolation
  60. * event has occured (e.g. by reading 0xff's), will then ask EEH
  61. * whether this is the case, and then take appropriate steps to
  62. * reset the PCI slot, the PCI device, and then resume operations.
  63. * However, until that day, the checking is done here, with the
  64. * eeh_check_failure() routine embedded in the MMIO macros. If
  65. * the slot is found to be isolated, an "EEH Event" is synthesized
  66. * and sent out for processing.
  67. */
  68. /* If a device driver keeps reading an MMIO register in an interrupt
  69. * handler after a slot isolation event has occurred, we assume it
  70. * is broken and panic. This sets the threshold for how many read
  71. * attempts we allow before panicking.
  72. */
  73. #define EEH_MAX_FAILS 100000
  74. /* RTAS tokens */
  75. static int ibm_set_eeh_option;
  76. static int ibm_set_slot_reset;
  77. static int ibm_read_slot_reset_state;
  78. static int ibm_read_slot_reset_state2;
  79. static int ibm_slot_error_detail;
  80. static int ibm_get_config_addr_info;
  81. static int ibm_configure_bridge;
  82. int eeh_subsystem_enabled;
  83. EXPORT_SYMBOL(eeh_subsystem_enabled);
  84. /* Lock to avoid races due to multiple reports of an error */
  85. static DEFINE_SPINLOCK(confirm_error_lock);
  86. /* Buffer for reporting slot-error-detail rtas calls */
  87. static unsigned char slot_errbuf[RTAS_ERROR_LOG_MAX];
  88. static DEFINE_SPINLOCK(slot_errbuf_lock);
  89. static int eeh_error_buf_size;
  90. /* System monitoring statistics */
  91. static unsigned long no_device;
  92. static unsigned long no_dn;
  93. static unsigned long no_cfg_addr;
  94. static unsigned long ignored_check;
  95. static unsigned long total_mmio_ffs;
  96. static unsigned long false_positives;
  97. static unsigned long ignored_failures;
  98. static unsigned long slot_resets;
  99. #define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE)
  100. /* --------------------------------------------------------------- */
  101. /* Below lies the EEH event infrastructure */
  102. void eeh_slot_error_detail (struct pci_dn *pdn, int severity)
  103. {
  104. int config_addr;
  105. unsigned long flags;
  106. int rc;
  107. /* Log the error with the rtas logger */
  108. spin_lock_irqsave(&slot_errbuf_lock, flags);
  109. memset(slot_errbuf, 0, eeh_error_buf_size);
  110. /* Use PE configuration address, if present */
  111. config_addr = pdn->eeh_config_addr;
  112. if (pdn->eeh_pe_config_addr)
  113. config_addr = pdn->eeh_pe_config_addr;
  114. rc = rtas_call(ibm_slot_error_detail,
  115. 8, 1, NULL, config_addr,
  116. BUID_HI(pdn->phb->buid),
  117. BUID_LO(pdn->phb->buid), NULL, 0,
  118. virt_to_phys(slot_errbuf),
  119. eeh_error_buf_size,
  120. severity);
  121. if (rc == 0)
  122. log_error(slot_errbuf, ERR_TYPE_RTAS_LOG, 0);
  123. spin_unlock_irqrestore(&slot_errbuf_lock, flags);
  124. }
  125. /**
  126. * read_slot_reset_state - Read the reset state of a device node's slot
  127. * @dn: device node to read
  128. * @rets: array to return results in
  129. */
  130. static int read_slot_reset_state(struct pci_dn *pdn, int rets[])
  131. {
  132. int token, outputs;
  133. int config_addr;
  134. if (ibm_read_slot_reset_state2 != RTAS_UNKNOWN_SERVICE) {
  135. token = ibm_read_slot_reset_state2;
  136. outputs = 4;
  137. } else {
  138. token = ibm_read_slot_reset_state;
  139. rets[2] = 0; /* fake PE Unavailable info */
  140. outputs = 3;
  141. }
  142. /* Use PE configuration address, if present */
  143. config_addr = pdn->eeh_config_addr;
  144. if (pdn->eeh_pe_config_addr)
  145. config_addr = pdn->eeh_pe_config_addr;
  146. return rtas_call(token, 3, outputs, rets, config_addr,
  147. BUID_HI(pdn->phb->buid), BUID_LO(pdn->phb->buid));
  148. }
  149. /**
  150. * eeh_token_to_phys - convert EEH address token to phys address
  151. * @token i/o token, should be address in the form 0xA....
  152. */
  153. static inline unsigned long eeh_token_to_phys(unsigned long token)
  154. {
  155. pte_t *ptep;
  156. unsigned long pa;
  157. ptep = find_linux_pte(init_mm.pgd, token);
  158. if (!ptep)
  159. return token;
  160. pa = pte_pfn(*ptep) << PAGE_SHIFT;
  161. return pa | (token & (PAGE_SIZE-1));
  162. }
  163. /**
  164. * Return the "partitionable endpoint" (pe) under which this device lies
  165. */
  166. struct device_node * find_device_pe(struct device_node *dn)
  167. {
  168. while ((dn->parent) && PCI_DN(dn->parent) &&
  169. (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) {
  170. dn = dn->parent;
  171. }
  172. return dn;
  173. }
  174. /** Mark all devices that are peers of this device as failed.
  175. * Mark the device driver too, so that it can see the failure
  176. * immediately; this is critical, since some drivers poll
  177. * status registers in interrupts ... If a driver is polling,
  178. * and the slot is frozen, then the driver can deadlock in
  179. * an interrupt context, which is bad.
  180. */
  181. static void __eeh_mark_slot (struct device_node *dn, int mode_flag)
  182. {
  183. while (dn) {
  184. if (PCI_DN(dn)) {
  185. /* Mark the pci device driver too */
  186. struct pci_dev *dev = PCI_DN(dn)->pcidev;
  187. PCI_DN(dn)->eeh_mode |= mode_flag;
  188. if (dev && dev->driver)
  189. dev->error_state = pci_channel_io_frozen;
  190. if (dn->child)
  191. __eeh_mark_slot (dn->child, mode_flag);
  192. }
  193. dn = dn->sibling;
  194. }
  195. }
  196. void eeh_mark_slot (struct device_node *dn, int mode_flag)
  197. {
  198. dn = find_device_pe (dn);
  199. /* Back up one, since config addrs might be shared */
  200. if (PCI_DN(dn) && PCI_DN(dn)->eeh_pe_config_addr)
  201. dn = dn->parent;
  202. PCI_DN(dn)->eeh_mode |= mode_flag;
  203. __eeh_mark_slot (dn->child, mode_flag);
  204. }
  205. static void __eeh_clear_slot (struct device_node *dn, int mode_flag)
  206. {
  207. while (dn) {
  208. if (PCI_DN(dn)) {
  209. PCI_DN(dn)->eeh_mode &= ~mode_flag;
  210. PCI_DN(dn)->eeh_check_count = 0;
  211. if (dn->child)
  212. __eeh_clear_slot (dn->child, mode_flag);
  213. }
  214. dn = dn->sibling;
  215. }
  216. }
  217. void eeh_clear_slot (struct device_node *dn, int mode_flag)
  218. {
  219. unsigned long flags;
  220. spin_lock_irqsave(&confirm_error_lock, flags);
  221. dn = find_device_pe (dn);
  222. /* Back up one, since config addrs might be shared */
  223. if (PCI_DN(dn) && PCI_DN(dn)->eeh_pe_config_addr)
  224. dn = dn->parent;
  225. PCI_DN(dn)->eeh_mode &= ~mode_flag;
  226. PCI_DN(dn)->eeh_check_count = 0;
  227. __eeh_clear_slot (dn->child, mode_flag);
  228. spin_unlock_irqrestore(&confirm_error_lock, flags);
  229. }
  230. /**
  231. * eeh_dn_check_failure - check if all 1's data is due to EEH slot freeze
  232. * @dn device node
  233. * @dev pci device, if known
  234. *
  235. * Check for an EEH failure for the given device node. Call this
  236. * routine if the result of a read was all 0xff's and you want to
  237. * find out if this is due to an EEH slot freeze. This routine
  238. * will query firmware for the EEH status.
  239. *
  240. * Returns 0 if there has not been an EEH error; otherwise returns
  241. * a non-zero value and queues up a slot isolation event notification.
  242. *
  243. * It is safe to call this routine in an interrupt context.
  244. */
  245. int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
  246. {
  247. int ret;
  248. int rets[3];
  249. unsigned long flags;
  250. struct pci_dn *pdn;
  251. enum pci_channel_state state;
  252. int rc = 0;
  253. total_mmio_ffs++;
  254. if (!eeh_subsystem_enabled)
  255. return 0;
  256. if (!dn) {
  257. no_dn++;
  258. return 0;
  259. }
  260. pdn = PCI_DN(dn);
  261. /* Access to IO BARs might get this far and still not want checking. */
  262. if (!(pdn->eeh_mode & EEH_MODE_SUPPORTED) ||
  263. pdn->eeh_mode & EEH_MODE_NOCHECK) {
  264. ignored_check++;
  265. #ifdef DEBUG
  266. printk ("EEH:ignored check (%x) for %s %s\n",
  267. pdn->eeh_mode, pci_name (dev), dn->full_name);
  268. #endif
  269. return 0;
  270. }
  271. if (!pdn->eeh_config_addr && !pdn->eeh_pe_config_addr) {
  272. no_cfg_addr++;
  273. return 0;
  274. }
  275. /* If we already have a pending isolation event for this
  276. * slot, we know it's bad already, we don't need to check.
  277. * Do this checking under a lock; as multiple PCI devices
  278. * in one slot might report errors simultaneously, and we
  279. * only want one error recovery routine running.
  280. */
  281. spin_lock_irqsave(&confirm_error_lock, flags);
  282. rc = 1;
  283. if (pdn->eeh_mode & EEH_MODE_ISOLATED) {
  284. pdn->eeh_check_count ++;
  285. if (pdn->eeh_check_count >= EEH_MAX_FAILS) {
  286. printk (KERN_ERR "EEH: Device driver ignored %d bad reads, panicing\n",
  287. pdn->eeh_check_count);
  288. dump_stack();
  289. /* re-read the slot reset state */
  290. if (read_slot_reset_state(pdn, rets) != 0)
  291. rets[0] = -1; /* reset state unknown */
  292. /* If we are here, then we hit an infinite loop. Stop. */
  293. panic("EEH: MMIO halt (%d) on device:%s\n", rets[0], pci_name(dev));
  294. }
  295. goto dn_unlock;
  296. }
  297. /*
  298. * Now test for an EEH failure. This is VERY expensive.
  299. * Note that the eeh_config_addr may be a parent device
  300. * in the case of a device behind a bridge, or it may be
  301. * function zero of a multi-function device.
  302. * In any case they must share a common PHB.
  303. */
  304. ret = read_slot_reset_state(pdn, rets);
  305. /* If the call to firmware failed, punt */
  306. if (ret != 0) {
  307. printk(KERN_WARNING "EEH: read_slot_reset_state() failed; rc=%d dn=%s\n",
  308. ret, dn->full_name);
  309. false_positives++;
  310. rc = 0;
  311. goto dn_unlock;
  312. }
  313. /* If EEH is not supported on this device, punt. */
  314. if (rets[1] != 1) {
  315. printk(KERN_WARNING "EEH: event on unsupported device, rc=%d dn=%s\n",
  316. ret, dn->full_name);
  317. false_positives++;
  318. rc = 0;
  319. goto dn_unlock;
  320. }
  321. /* If not the kind of error we know about, punt. */
  322. if (rets[0] != 2 && rets[0] != 4 && rets[0] != 5) {
  323. false_positives++;
  324. rc = 0;
  325. goto dn_unlock;
  326. }
  327. /* Note that config-io to empty slots may fail;
  328. * we recognize empty because they don't have children. */
  329. if ((rets[0] == 5) && (dn->child == NULL)) {
  330. false_positives++;
  331. rc = 0;
  332. goto dn_unlock;
  333. }
  334. slot_resets++;
  335. /* Avoid repeated reports of this failure, including problems
  336. * with other functions on this device, and functions under
  337. * bridges. */
  338. eeh_mark_slot (dn, EEH_MODE_ISOLATED);
  339. spin_unlock_irqrestore(&confirm_error_lock, flags);
  340. state = pci_channel_io_normal;
  341. if ((rets[0] == 2) || (rets[0] == 4))
  342. state = pci_channel_io_frozen;
  343. if (rets[0] == 5)
  344. state = pci_channel_io_perm_failure;
  345. eeh_send_failure_event (dn, dev, state, rets[2]);
  346. /* Most EEH events are due to device driver bugs. Having
  347. * a stack trace will help the device-driver authors figure
  348. * out what happened. So print that out. */
  349. if (rets[0] != 5) dump_stack();
  350. return 1;
  351. dn_unlock:
  352. spin_unlock_irqrestore(&confirm_error_lock, flags);
  353. return rc;
  354. }
  355. EXPORT_SYMBOL_GPL(eeh_dn_check_failure);
  356. /**
  357. * eeh_check_failure - check if all 1's data is due to EEH slot freeze
  358. * @token i/o token, should be address in the form 0xA....
  359. * @val value, should be all 1's (XXX why do we need this arg??)
  360. *
  361. * Check for an EEH failure at the given token address. Call this
  362. * routine if the result of a read was all 0xff's and you want to
  363. * find out if this is due to an EEH slot freeze event. This routine
  364. * will query firmware for the EEH status.
  365. *
  366. * Note this routine is safe to call in an interrupt context.
  367. */
  368. unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
  369. {
  370. unsigned long addr;
  371. struct pci_dev *dev;
  372. struct device_node *dn;
  373. /* Finding the phys addr + pci device; this is pretty quick. */
  374. addr = eeh_token_to_phys((unsigned long __force) token);
  375. dev = pci_get_device_by_addr(addr);
  376. if (!dev) {
  377. no_device++;
  378. return val;
  379. }
  380. dn = pci_device_to_OF_node(dev);
  381. eeh_dn_check_failure (dn, dev);
  382. pci_dev_put(dev);
  383. return val;
  384. }
  385. EXPORT_SYMBOL(eeh_check_failure);
  386. /* ------------------------------------------------------------- */
  387. /* The code below deals with error recovery */
  388. /** Return negative value if a permanent error, else return
  389. * a number of milliseconds to wait until the PCI slot is
  390. * ready to be used.
  391. */
  392. static int
  393. eeh_slot_availability(struct pci_dn *pdn)
  394. {
  395. int rc;
  396. int rets[3];
  397. rc = read_slot_reset_state(pdn, rets);
  398. if (rc) return rc;
  399. if (rets[1] == 0) return -1; /* EEH is not supported */
  400. if (rets[0] == 0) return 0; /* Oll Korrect */
  401. if (rets[0] == 5) {
  402. if (rets[2] == 0) return -1; /* permanently unavailable */
  403. return rets[2]; /* number of millisecs to wait */
  404. }
  405. if (rets[0] == 1)
  406. return 250;
  407. printk (KERN_ERR "EEH: Slot unavailable: rc=%d, rets=%d %d %d\n",
  408. rc, rets[0], rets[1], rets[2]);
  409. return -1;
  410. }
  411. /** rtas_pci_slot_reset raises/lowers the pci #RST line
  412. * state: 1/0 to raise/lower the #RST
  413. *
  414. * Clear the EEH-frozen condition on a slot. This routine
  415. * asserts the PCI #RST line if the 'state' argument is '1',
  416. * and drops the #RST line if 'state is '0'. This routine is
  417. * safe to call in an interrupt context.
  418. *
  419. */
  420. static void
  421. rtas_pci_slot_reset(struct pci_dn *pdn, int state)
  422. {
  423. int config_addr;
  424. int rc;
  425. BUG_ON (pdn==NULL);
  426. if (!pdn->phb) {
  427. printk (KERN_WARNING "EEH: in slot reset, device node %s has no phb\n",
  428. pdn->node->full_name);
  429. return;
  430. }
  431. /* Use PE configuration address, if present */
  432. config_addr = pdn->eeh_config_addr;
  433. if (pdn->eeh_pe_config_addr)
  434. config_addr = pdn->eeh_pe_config_addr;
  435. rc = rtas_call(ibm_set_slot_reset,4,1, NULL,
  436. config_addr,
  437. BUID_HI(pdn->phb->buid),
  438. BUID_LO(pdn->phb->buid),
  439. state);
  440. if (rc) {
  441. printk (KERN_WARNING "EEH: Unable to reset the failed slot, (%d) #RST=%d dn=%s\n",
  442. rc, state, pdn->node->full_name);
  443. return;
  444. }
  445. }
  446. /** rtas_set_slot_reset -- assert the pci #RST line for 1/4 second
  447. * dn -- device node to be reset.
  448. *
  449. * Return 0 if success, else a non-zero value.
  450. */
  451. int
  452. rtas_set_slot_reset(struct pci_dn *pdn)
  453. {
  454. int i, rc;
  455. rtas_pci_slot_reset (pdn, 1);
  456. /* The PCI bus requires that the reset be held high for at least
  457. * a 100 milliseconds. We wait a bit longer 'just in case'. */
  458. #define PCI_BUS_RST_HOLD_TIME_MSEC 250
  459. msleep (PCI_BUS_RST_HOLD_TIME_MSEC);
  460. /* We might get hit with another EEH freeze as soon as the
  461. * pci slot reset line is dropped. Make sure we don't miss
  462. * these, and clear the flag now. */
  463. eeh_clear_slot (pdn->node, EEH_MODE_ISOLATED);
  464. rtas_pci_slot_reset (pdn, 0);
  465. /* After a PCI slot has been reset, the PCI Express spec requires
  466. * a 1.5 second idle time for the bus to stabilize, before starting
  467. * up traffic. */
  468. #define PCI_BUS_SETTLE_TIME_MSEC 1800
  469. msleep (PCI_BUS_SETTLE_TIME_MSEC);
  470. /* Now double check with the firmware to make sure the device is
  471. * ready to be used; if not, wait for recovery. */
  472. for (i=0; i<10; i++) {
  473. rc = eeh_slot_availability (pdn);
  474. if (rc < 0)
  475. printk (KERN_ERR "EEH: failed (%d) to reset slot %s\n", rc, pdn->node->full_name);
  476. if (rc == 0)
  477. return 0;
  478. if (rc < 0)
  479. return -1;
  480. msleep (rc+100);
  481. }
  482. rc = eeh_slot_availability (pdn);
  483. if (rc)
  484. printk (KERN_ERR "EEH: timeout resetting slot %s\n", pdn->node->full_name);
  485. return rc;
  486. }
  487. /* ------------------------------------------------------- */
  488. /** Save and restore of PCI BARs
  489. *
  490. * Although firmware will set up BARs during boot, it doesn't
  491. * set up device BAR's after a device reset, although it will,
  492. * if requested, set up bridge configuration. Thus, we need to
  493. * configure the PCI devices ourselves.
  494. */
  495. /**
  496. * __restore_bars - Restore the Base Address Registers
  497. * Loads the PCI configuration space base address registers,
  498. * the expansion ROM base address, the latency timer, and etc.
  499. * from the saved values in the device node.
  500. */
  501. static inline void __restore_bars (struct pci_dn *pdn)
  502. {
  503. int i;
  504. if (NULL==pdn->phb) return;
  505. for (i=4; i<10; i++) {
  506. rtas_write_config(pdn, i*4, 4, pdn->config_space[i]);
  507. }
  508. /* 12 == Expansion ROM Address */
  509. rtas_write_config(pdn, 12*4, 4, pdn->config_space[12]);
  510. #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
  511. #define SAVED_BYTE(OFF) (((u8 *)(pdn->config_space))[BYTE_SWAP(OFF)])
  512. rtas_write_config (pdn, PCI_CACHE_LINE_SIZE, 1,
  513. SAVED_BYTE(PCI_CACHE_LINE_SIZE));
  514. rtas_write_config (pdn, PCI_LATENCY_TIMER, 1,
  515. SAVED_BYTE(PCI_LATENCY_TIMER));
  516. /* max latency, min grant, interrupt pin and line */
  517. rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]);
  518. }
  519. /**
  520. * eeh_restore_bars - restore the PCI config space info
  521. *
  522. * This routine performs a recursive walk to the children
  523. * of this device as well.
  524. */
  525. void eeh_restore_bars(struct pci_dn *pdn)
  526. {
  527. struct device_node *dn;
  528. if (!pdn)
  529. return;
  530. if ((pdn->eeh_mode & EEH_MODE_SUPPORTED) && !IS_BRIDGE(pdn->class_code))
  531. __restore_bars (pdn);
  532. dn = pdn->node->child;
  533. while (dn) {
  534. eeh_restore_bars (PCI_DN(dn));
  535. dn = dn->sibling;
  536. }
  537. }
  538. /**
  539. * eeh_save_bars - save device bars
  540. *
  541. * Save the values of the device bars. Unlike the restore
  542. * routine, this routine is *not* recursive. This is because
  543. * PCI devices are added individuallly; but, for the restore,
  544. * an entire slot is reset at a time.
  545. */
  546. static void eeh_save_bars(struct pci_dn *pdn)
  547. {
  548. int i;
  549. if (!pdn )
  550. return;
  551. for (i = 0; i < 16; i++)
  552. rtas_read_config(pdn, i * 4, 4, &pdn->config_space[i]);
  553. }
  554. void
  555. rtas_configure_bridge(struct pci_dn *pdn)
  556. {
  557. int config_addr;
  558. int rc;
  559. /* Use PE configuration address, if present */
  560. config_addr = pdn->eeh_config_addr;
  561. if (pdn->eeh_pe_config_addr)
  562. config_addr = pdn->eeh_pe_config_addr;
  563. rc = rtas_call(ibm_configure_bridge,3,1, NULL,
  564. config_addr,
  565. BUID_HI(pdn->phb->buid),
  566. BUID_LO(pdn->phb->buid));
  567. if (rc) {
  568. printk (KERN_WARNING "EEH: Unable to configure device bridge (%d) for %s\n",
  569. rc, pdn->node->full_name);
  570. }
  571. }
  572. /* ------------------------------------------------------------- */
  573. /* The code below deals with enabling EEH for devices during the
  574. * early boot sequence. EEH must be enabled before any PCI probing
  575. * can be done.
  576. */
  577. #define EEH_ENABLE 1
  578. struct eeh_early_enable_info {
  579. unsigned int buid_hi;
  580. unsigned int buid_lo;
  581. };
  582. /* Enable eeh for the given device node. */
  583. static void *early_enable_eeh(struct device_node *dn, void *data)
  584. {
  585. struct eeh_early_enable_info *info = data;
  586. int ret;
  587. char *status = get_property(dn, "status", NULL);
  588. u32 *class_code = (u32 *)get_property(dn, "class-code", NULL);
  589. u32 *vendor_id = (u32 *)get_property(dn, "vendor-id", NULL);
  590. u32 *device_id = (u32 *)get_property(dn, "device-id", NULL);
  591. u32 *regs;
  592. int enable;
  593. struct pci_dn *pdn = PCI_DN(dn);
  594. pdn->class_code = 0;
  595. pdn->eeh_mode = 0;
  596. pdn->eeh_check_count = 0;
  597. pdn->eeh_freeze_count = 0;
  598. if (status && strcmp(status, "ok") != 0)
  599. return NULL; /* ignore devices with bad status */
  600. /* Ignore bad nodes. */
  601. if (!class_code || !vendor_id || !device_id)
  602. return NULL;
  603. /* There is nothing to check on PCI to ISA bridges */
  604. if (dn->type && !strcmp(dn->type, "isa")) {
  605. pdn->eeh_mode |= EEH_MODE_NOCHECK;
  606. return NULL;
  607. }
  608. pdn->class_code = *class_code;
  609. /*
  610. * Now decide if we are going to "Disable" EEH checking
  611. * for this device. We still run with the EEH hardware active,
  612. * but we won't be checking for ff's. This means a driver
  613. * could return bad data (very bad!), an interrupt handler could
  614. * hang waiting on status bits that won't change, etc.
  615. * But there are a few cases like display devices that make sense.
  616. */
  617. enable = 1; /* i.e. we will do checking */
  618. #if 0
  619. if ((*class_code >> 16) == PCI_BASE_CLASS_DISPLAY)
  620. enable = 0;
  621. #endif
  622. if (!enable)
  623. pdn->eeh_mode |= EEH_MODE_NOCHECK;
  624. /* Ok... see if this device supports EEH. Some do, some don't,
  625. * and the only way to find out is to check each and every one. */
  626. regs = (u32 *)get_property(dn, "reg", NULL);
  627. if (regs) {
  628. /* First register entry is addr (00BBSS00) */
  629. /* Try to enable eeh */
  630. ret = rtas_call(ibm_set_eeh_option, 4, 1, NULL,
  631. regs[0], info->buid_hi, info->buid_lo,
  632. EEH_ENABLE);
  633. if (ret == 0) {
  634. eeh_subsystem_enabled = 1;
  635. pdn->eeh_mode |= EEH_MODE_SUPPORTED;
  636. pdn->eeh_config_addr = regs[0];
  637. /* If the newer, better, ibm,get-config-addr-info is supported,
  638. * then use that instead. */
  639. pdn->eeh_pe_config_addr = 0;
  640. if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) {
  641. unsigned int rets[2];
  642. ret = rtas_call (ibm_get_config_addr_info, 4, 2, rets,
  643. pdn->eeh_config_addr,
  644. info->buid_hi, info->buid_lo,
  645. 0);
  646. if (ret == 0)
  647. pdn->eeh_pe_config_addr = rets[0];
  648. }
  649. #ifdef DEBUG
  650. printk(KERN_DEBUG "EEH: %s: eeh enabled, config=%x pe_config=%x\n",
  651. dn->full_name, pdn->eeh_config_addr, pdn->eeh_pe_config_addr);
  652. #endif
  653. } else {
  654. /* This device doesn't support EEH, but it may have an
  655. * EEH parent, in which case we mark it as supported. */
  656. if (dn->parent && PCI_DN(dn->parent)
  657. && (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) {
  658. /* Parent supports EEH. */
  659. pdn->eeh_mode |= EEH_MODE_SUPPORTED;
  660. pdn->eeh_config_addr = PCI_DN(dn->parent)->eeh_config_addr;
  661. return NULL;
  662. }
  663. }
  664. } else {
  665. printk(KERN_WARNING "EEH: %s: unable to get reg property.\n",
  666. dn->full_name);
  667. }
  668. eeh_save_bars(pdn);
  669. return NULL;
  670. }
  671. /*
  672. * Initialize EEH by trying to enable it for all of the adapters in the system.
  673. * As a side effect we can determine here if eeh is supported at all.
  674. * Note that we leave EEH on so failed config cycles won't cause a machine
  675. * check. If a user turns off EEH for a particular adapter they are really
  676. * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't
  677. * grant access to a slot if EEH isn't enabled, and so we always enable
  678. * EEH for all slots/all devices.
  679. *
  680. * The eeh-force-off option disables EEH checking globally, for all slots.
  681. * Even if force-off is set, the EEH hardware is still enabled, so that
  682. * newer systems can boot.
  683. */
  684. void __init eeh_init(void)
  685. {
  686. struct device_node *phb, *np;
  687. struct eeh_early_enable_info info;
  688. spin_lock_init(&confirm_error_lock);
  689. spin_lock_init(&slot_errbuf_lock);
  690. np = of_find_node_by_path("/rtas");
  691. if (np == NULL)
  692. return;
  693. ibm_set_eeh_option = rtas_token("ibm,set-eeh-option");
  694. ibm_set_slot_reset = rtas_token("ibm,set-slot-reset");
  695. ibm_read_slot_reset_state2 = rtas_token("ibm,read-slot-reset-state2");
  696. ibm_read_slot_reset_state = rtas_token("ibm,read-slot-reset-state");
  697. ibm_slot_error_detail = rtas_token("ibm,slot-error-detail");
  698. ibm_get_config_addr_info = rtas_token("ibm,get-config-addr-info");
  699. ibm_configure_bridge = rtas_token ("ibm,configure-bridge");
  700. if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE)
  701. return;
  702. eeh_error_buf_size = rtas_token("rtas-error-log-max");
  703. if (eeh_error_buf_size == RTAS_UNKNOWN_SERVICE) {
  704. eeh_error_buf_size = 1024;
  705. }
  706. if (eeh_error_buf_size > RTAS_ERROR_LOG_MAX) {
  707. printk(KERN_WARNING "EEH: rtas-error-log-max is bigger than allocated "
  708. "buffer ! (%d vs %d)", eeh_error_buf_size, RTAS_ERROR_LOG_MAX);
  709. eeh_error_buf_size = RTAS_ERROR_LOG_MAX;
  710. }
  711. /* Enable EEH for all adapters. Note that eeh requires buid's */
  712. for (phb = of_find_node_by_name(NULL, "pci"); phb;
  713. phb = of_find_node_by_name(phb, "pci")) {
  714. unsigned long buid;
  715. buid = get_phb_buid(phb);
  716. if (buid == 0 || PCI_DN(phb) == NULL)
  717. continue;
  718. info.buid_lo = BUID_LO(buid);
  719. info.buid_hi = BUID_HI(buid);
  720. traverse_pci_devices(phb, early_enable_eeh, &info);
  721. }
  722. if (eeh_subsystem_enabled)
  723. printk(KERN_INFO "EEH: PCI Enhanced I/O Error Handling Enabled\n");
  724. else
  725. printk(KERN_WARNING "EEH: No capable adapters found\n");
  726. }
  727. /**
  728. * eeh_add_device_early - enable EEH for the indicated device_node
  729. * @dn: device node for which to set up EEH
  730. *
  731. * This routine must be used to perform EEH initialization for PCI
  732. * devices that were added after system boot (e.g. hotplug, dlpar).
  733. * This routine must be called before any i/o is performed to the
  734. * adapter (inluding any config-space i/o).
  735. * Whether this actually enables EEH or not for this device depends
  736. * on the CEC architecture, type of the device, on earlier boot
  737. * command-line arguments & etc.
  738. */
  739. static void eeh_add_device_early(struct device_node *dn)
  740. {
  741. struct pci_controller *phb;
  742. struct eeh_early_enable_info info;
  743. if (!dn || !PCI_DN(dn))
  744. return;
  745. phb = PCI_DN(dn)->phb;
  746. /* USB Bus children of PCI devices will not have BUID's */
  747. if (NULL == phb || 0 == phb->buid)
  748. return;
  749. info.buid_hi = BUID_HI(phb->buid);
  750. info.buid_lo = BUID_LO(phb->buid);
  751. early_enable_eeh(dn, &info);
  752. }
  753. void eeh_add_device_tree_early(struct device_node *dn)
  754. {
  755. struct device_node *sib;
  756. for (sib = dn->child; sib; sib = sib->sibling)
  757. eeh_add_device_tree_early(sib);
  758. eeh_add_device_early(dn);
  759. }
  760. EXPORT_SYMBOL_GPL(eeh_add_device_tree_early);
  761. /**
  762. * eeh_add_device_late - perform EEH initialization for the indicated pci device
  763. * @dev: pci device for which to set up EEH
  764. *
  765. * This routine must be used to complete EEH initialization for PCI
  766. * devices that were added after system boot (e.g. hotplug, dlpar).
  767. */
  768. static void eeh_add_device_late(struct pci_dev *dev)
  769. {
  770. struct device_node *dn;
  771. struct pci_dn *pdn;
  772. if (!dev || !eeh_subsystem_enabled)
  773. return;
  774. #ifdef DEBUG
  775. printk(KERN_DEBUG "EEH: adding device %s\n", pci_name(dev));
  776. #endif
  777. pci_dev_get (dev);
  778. dn = pci_device_to_OF_node(dev);
  779. pdn = PCI_DN(dn);
  780. pdn->pcidev = dev;
  781. pci_addr_cache_insert_device (dev);
  782. }
  783. void eeh_add_device_tree_late(struct pci_bus *bus)
  784. {
  785. struct pci_dev *dev;
  786. list_for_each_entry(dev, &bus->devices, bus_list) {
  787. eeh_add_device_late(dev);
  788. if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
  789. struct pci_bus *subbus = dev->subordinate;
  790. if (subbus)
  791. eeh_add_device_tree_late(subbus);
  792. }
  793. }
  794. }
  795. EXPORT_SYMBOL_GPL(eeh_add_device_tree_late);
  796. /**
  797. * eeh_remove_device - undo EEH setup for the indicated pci device
  798. * @dev: pci device to be removed
  799. *
  800. * This routine should be called when a device is removed from
  801. * a running system (e.g. by hotplug or dlpar). It unregisters
  802. * the PCI device from the EEH subsystem. I/O errors affecting
  803. * this device will no longer be detected after this call; thus,
  804. * i/o errors affecting this slot may leave this device unusable.
  805. */
  806. static void eeh_remove_device(struct pci_dev *dev)
  807. {
  808. struct device_node *dn;
  809. if (!dev || !eeh_subsystem_enabled)
  810. return;
  811. /* Unregister the device with the EEH/PCI address search system */
  812. #ifdef DEBUG
  813. printk(KERN_DEBUG "EEH: remove device %s\n", pci_name(dev));
  814. #endif
  815. pci_addr_cache_remove_device(dev);
  816. dn = pci_device_to_OF_node(dev);
  817. if (PCI_DN(dn)->pcidev) {
  818. PCI_DN(dn)->pcidev = NULL;
  819. pci_dev_put (dev);
  820. }
  821. }
  822. void eeh_remove_bus_device(struct pci_dev *dev)
  823. {
  824. struct pci_bus *bus = dev->subordinate;
  825. struct pci_dev *child, *tmp;
  826. eeh_remove_device(dev);
  827. if (bus && dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
  828. list_for_each_entry_safe(child, tmp, &bus->devices, bus_list)
  829. eeh_remove_bus_device(child);
  830. }
  831. }
  832. EXPORT_SYMBOL_GPL(eeh_remove_bus_device);
  833. static int proc_eeh_show(struct seq_file *m, void *v)
  834. {
  835. if (0 == eeh_subsystem_enabled) {
  836. seq_printf(m, "EEH Subsystem is globally disabled\n");
  837. seq_printf(m, "eeh_total_mmio_ffs=%ld\n", total_mmio_ffs);
  838. } else {
  839. seq_printf(m, "EEH Subsystem is enabled\n");
  840. seq_printf(m,
  841. "no device=%ld\n"
  842. "no device node=%ld\n"
  843. "no config address=%ld\n"
  844. "check not wanted=%ld\n"
  845. "eeh_total_mmio_ffs=%ld\n"
  846. "eeh_false_positives=%ld\n"
  847. "eeh_ignored_failures=%ld\n"
  848. "eeh_slot_resets=%ld\n",
  849. no_device, no_dn, no_cfg_addr,
  850. ignored_check, total_mmio_ffs,
  851. false_positives, ignored_failures,
  852. slot_resets);
  853. }
  854. return 0;
  855. }
  856. static int proc_eeh_open(struct inode *inode, struct file *file)
  857. {
  858. return single_open(file, proc_eeh_show, NULL);
  859. }
  860. static struct file_operations proc_eeh_operations = {
  861. .open = proc_eeh_open,
  862. .read = seq_read,
  863. .llseek = seq_lseek,
  864. .release = single_release,
  865. };
  866. static int __init eeh_init_proc(void)
  867. {
  868. struct proc_dir_entry *e;
  869. if (machine_is(pseries)) {
  870. e = create_proc_entry("ppc64/eeh", 0, NULL);
  871. if (e)
  872. e->proc_fops = &proc_eeh_operations;
  873. }
  874. return 0;
  875. }
  876. __initcall(eeh_init_proc);