common.c 6.7 KB

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  1. /*
  2. * Low-Level PCI Support for PC
  3. *
  4. * (c) 1999--2000 Martin Mares <mj@ucw.cz>
  5. */
  6. #include <linux/sched.h>
  7. #include <linux/pci.h>
  8. #include <linux/ioport.h>
  9. #include <linux/init.h>
  10. #include <linux/dmi.h>
  11. #include <asm/acpi.h>
  12. #include <asm/segment.h>
  13. #include <asm/io.h>
  14. #include <asm/smp.h>
  15. #include "pci.h"
  16. #ifdef CONFIG_PCI_BIOS
  17. extern void pcibios_sort(void);
  18. #endif
  19. unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2 |
  20. PCI_PROBE_MMCONF;
  21. int pci_routeirq;
  22. int pcibios_last_bus = -1;
  23. unsigned long pirq_table_addr;
  24. struct pci_bus *pci_root_bus;
  25. struct pci_raw_ops *raw_pci_ops;
  26. static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
  27. {
  28. return raw_pci_ops->read(0, bus->number, devfn, where, size, value);
  29. }
  30. static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
  31. {
  32. return raw_pci_ops->write(0, bus->number, devfn, where, size, value);
  33. }
  34. struct pci_ops pci_root_ops = {
  35. .read = pci_read,
  36. .write = pci_write,
  37. };
  38. /*
  39. * legacy, numa, and acpi all want to call pcibios_scan_root
  40. * from their initcalls. This flag prevents that.
  41. */
  42. int pcibios_scanned;
  43. /*
  44. * This interrupt-safe spinlock protects all accesses to PCI
  45. * configuration space.
  46. */
  47. DEFINE_SPINLOCK(pci_config_lock);
  48. /*
  49. * Several buggy motherboards address only 16 devices and mirror
  50. * them to next 16 IDs. We try to detect this `feature' on all
  51. * primary buses (those containing host bridges as they are
  52. * expected to be unique) and remove the ghost devices.
  53. */
  54. static void __devinit pcibios_fixup_ghosts(struct pci_bus *b)
  55. {
  56. struct list_head *ln, *mn;
  57. struct pci_dev *d, *e;
  58. int mirror = PCI_DEVFN(16,0);
  59. int seen_host_bridge = 0;
  60. int i;
  61. DBG("PCI: Scanning for ghost devices on bus %d\n", b->number);
  62. list_for_each(ln, &b->devices) {
  63. d = pci_dev_b(ln);
  64. if ((d->class >> 8) == PCI_CLASS_BRIDGE_HOST)
  65. seen_host_bridge++;
  66. for (mn=ln->next; mn != &b->devices; mn=mn->next) {
  67. e = pci_dev_b(mn);
  68. if (e->devfn != d->devfn + mirror ||
  69. e->vendor != d->vendor ||
  70. e->device != d->device ||
  71. e->class != d->class)
  72. continue;
  73. for(i=0; i<PCI_NUM_RESOURCES; i++)
  74. if (e->resource[i].start != d->resource[i].start ||
  75. e->resource[i].end != d->resource[i].end ||
  76. e->resource[i].flags != d->resource[i].flags)
  77. continue;
  78. break;
  79. }
  80. if (mn == &b->devices)
  81. return;
  82. }
  83. if (!seen_host_bridge)
  84. return;
  85. printk(KERN_WARNING "PCI: Ignoring ghost devices on bus %02x\n", b->number);
  86. ln = &b->devices;
  87. while (ln->next != &b->devices) {
  88. d = pci_dev_b(ln->next);
  89. if (d->devfn >= mirror) {
  90. list_del(&d->global_list);
  91. list_del(&d->bus_list);
  92. kfree(d);
  93. } else
  94. ln = ln->next;
  95. }
  96. }
  97. /*
  98. * Called after each bus is probed, but before its children
  99. * are examined.
  100. */
  101. void __devinit pcibios_fixup_bus(struct pci_bus *b)
  102. {
  103. pcibios_fixup_ghosts(b);
  104. pci_read_bridge_bases(b);
  105. }
  106. /*
  107. * Enable renumbering of PCI bus# ranges to reach all PCI busses (Cardbus)
  108. */
  109. #ifdef __i386__
  110. static int __devinit assign_all_busses(struct dmi_system_id *d)
  111. {
  112. pci_probe |= PCI_ASSIGN_ALL_BUSSES;
  113. printk(KERN_INFO "%s detected: enabling PCI bus# renumbering"
  114. " (pci=assign-busses)\n", d->ident);
  115. return 0;
  116. }
  117. #endif
  118. /*
  119. * Laptops which need pci=assign-busses to see Cardbus cards
  120. */
  121. static struct dmi_system_id __devinitdata pciprobe_dmi_table[] = {
  122. #ifdef __i386__
  123. {
  124. .callback = assign_all_busses,
  125. .ident = "Samsung X20 Laptop",
  126. .matches = {
  127. DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"),
  128. DMI_MATCH(DMI_PRODUCT_NAME, "SX20S"),
  129. },
  130. },
  131. #endif /* __i386__ */
  132. {}
  133. };
  134. struct pci_bus * __devinit pcibios_scan_root(int busnum)
  135. {
  136. struct pci_bus *bus = NULL;
  137. dmi_check_system(pciprobe_dmi_table);
  138. while ((bus = pci_find_next_bus(bus)) != NULL) {
  139. if (bus->number == busnum) {
  140. /* Already scanned */
  141. return bus;
  142. }
  143. }
  144. printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busnum);
  145. return pci_scan_bus_parented(NULL, busnum, &pci_root_ops, NULL);
  146. }
  147. extern u8 pci_cache_line_size;
  148. static int __init pcibios_init(void)
  149. {
  150. struct cpuinfo_x86 *c = &boot_cpu_data;
  151. if (!raw_pci_ops) {
  152. printk(KERN_WARNING "PCI: System does not support PCI\n");
  153. return 0;
  154. }
  155. /*
  156. * Assume PCI cacheline size of 32 bytes for all x86s except K7/K8
  157. * and P4. It's also good for 386/486s (which actually have 16)
  158. * as quite a few PCI devices do not support smaller values.
  159. */
  160. pci_cache_line_size = 32 >> 2;
  161. if (c->x86 >= 6 && c->x86_vendor == X86_VENDOR_AMD)
  162. pci_cache_line_size = 64 >> 2; /* K7 & K8 */
  163. else if (c->x86 > 6 && c->x86_vendor == X86_VENDOR_INTEL)
  164. pci_cache_line_size = 128 >> 2; /* P4 */
  165. pcibios_resource_survey();
  166. #ifdef CONFIG_PCI_BIOS
  167. if ((pci_probe & PCI_BIOS_SORT) && !(pci_probe & PCI_NO_SORT))
  168. pcibios_sort();
  169. #endif
  170. return 0;
  171. }
  172. subsys_initcall(pcibios_init);
  173. char * __devinit pcibios_setup(char *str)
  174. {
  175. if (!strcmp(str, "off")) {
  176. pci_probe = 0;
  177. return NULL;
  178. }
  179. #ifdef CONFIG_PCI_BIOS
  180. else if (!strcmp(str, "bios")) {
  181. pci_probe = PCI_PROBE_BIOS;
  182. return NULL;
  183. } else if (!strcmp(str, "nobios")) {
  184. pci_probe &= ~PCI_PROBE_BIOS;
  185. return NULL;
  186. } else if (!strcmp(str, "nosort")) {
  187. pci_probe |= PCI_NO_SORT;
  188. return NULL;
  189. } else if (!strcmp(str, "biosirq")) {
  190. pci_probe |= PCI_BIOS_IRQ_SCAN;
  191. return NULL;
  192. } else if (!strncmp(str, "pirqaddr=", 9)) {
  193. pirq_table_addr = simple_strtoul(str+9, NULL, 0);
  194. return NULL;
  195. }
  196. #endif
  197. #ifdef CONFIG_PCI_DIRECT
  198. else if (!strcmp(str, "conf1")) {
  199. pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
  200. return NULL;
  201. }
  202. else if (!strcmp(str, "conf2")) {
  203. pci_probe = PCI_PROBE_CONF2 | PCI_NO_CHECKS;
  204. return NULL;
  205. }
  206. #endif
  207. #ifdef CONFIG_PCI_MMCONFIG
  208. else if (!strcmp(str, "nommconf")) {
  209. pci_probe &= ~PCI_PROBE_MMCONF;
  210. return NULL;
  211. }
  212. #endif
  213. else if (!strcmp(str, "noacpi")) {
  214. acpi_noirq_set();
  215. return NULL;
  216. }
  217. #ifndef CONFIG_X86_VISWS
  218. else if (!strcmp(str, "usepirqmask")) {
  219. pci_probe |= PCI_USE_PIRQ_MASK;
  220. return NULL;
  221. } else if (!strncmp(str, "irqmask=", 8)) {
  222. pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
  223. return NULL;
  224. } else if (!strncmp(str, "lastbus=", 8)) {
  225. pcibios_last_bus = simple_strtol(str+8, NULL, 0);
  226. return NULL;
  227. }
  228. #endif
  229. else if (!strcmp(str, "rom")) {
  230. pci_probe |= PCI_ASSIGN_ROMS;
  231. return NULL;
  232. } else if (!strcmp(str, "assign-busses")) {
  233. pci_probe |= PCI_ASSIGN_ALL_BUSSES;
  234. return NULL;
  235. } else if (!strcmp(str, "routeirq")) {
  236. pci_routeirq = 1;
  237. return NULL;
  238. }
  239. return str;
  240. }
  241. unsigned int pcibios_assign_all_busses(void)
  242. {
  243. return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
  244. }
  245. int pcibios_enable_device(struct pci_dev *dev, int mask)
  246. {
  247. int err;
  248. if ((err = pcibios_enable_resources(dev, mask)) < 0)
  249. return err;
  250. return pcibios_enable_irq(dev);
  251. }
  252. void pcibios_disable_device (struct pci_dev *dev)
  253. {
  254. if (pcibios_disable_irq)
  255. pcibios_disable_irq(dev);
  256. }