dram_init.S 3.6 KB

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  1. /* $Id: dram_init.S,v 1.4 2005/04/24 18:48:32 starvik Exp $
  2. *
  3. * DRAM/SDRAM initialization - alter with care
  4. * This file is intended to be included from other assembler files
  5. *
  6. * Note: This file may not modify r8 or r9 because they are used to
  7. * carry information from the decompresser to the kernel
  8. *
  9. * Copyright (C) 2000-2003 Axis Communications AB
  10. *
  11. * Authors: Mikael Starvik (starvik@axis.com)
  12. */
  13. /* Just to be certain the config file is included, we include it here
  14. * explicitely instead of depending on it being included in the file that
  15. * uses this code.
  16. */
  17. #include <linux/config.h>
  18. #include <asm/arch/hwregs/asm/reg_map_asm.h>
  19. #include <asm/arch/hwregs/asm/bif_core_defs_asm.h>
  20. ;; WARNING! The registers r8 and r9 are used as parameters carrying
  21. ;; information from the decompressor (if the kernel was compressed).
  22. ;; They should not be used in the code below.
  23. ; Refer to BIF MDS for a description of SDRAM initialization
  24. ; Bank configuration
  25. move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp0), $r0
  26. move.d CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1
  27. move.d $r1, [$r0]
  28. move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp1), $r0
  29. move.d CONFIG_ETRAX_SDRAM_GRP1_CONFIG, $r1
  30. move.d $r1, [$r0]
  31. ; Calculate value of mrs_data
  32. ; CAS latency = 2 && bus_width = 32 => 0x40
  33. ; CAS latency = 3 && bus_width = 32 => 0x60
  34. ; CAS latency = 2 && bus_width = 16 => 0x20
  35. ; CAS latency = 3 && bus_width = 16 => 0x30
  36. ; Check if value is already supplied in kernel config
  37. move.d CONFIG_ETRAX_SDRAM_COMMAND, $r2
  38. bne _set_timing
  39. nop
  40. move.d 0x40, $r4 ; Assume 32 bits and CAS latency = 2
  41. move.d CONFIG_ETRAX_SDRAM_TIMING, $r1
  42. and.d 0x07, $r1 ; Get CAS latency
  43. cmpq 2, $r1 ; CL = 2 ?
  44. beq _bw_check
  45. nop
  46. move.d 0x60, $r4
  47. _bw_check:
  48. ; Assume that group 0 width is equal to group 1. This assumption
  49. ; is wrong for a group 1 only hardware (such as the grand old
  50. ; StorPoint+).
  51. move.d CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1
  52. and.d 0x200, $r1 ; DRAM width is bit 9
  53. beq _set_timing
  54. lslq 2, $r4 ; mrs_data starts at bit 2
  55. lsrq 1, $r4 ; 16 bits. Shift down value.
  56. ; Set timing parameters (refresh off to avoid Guinness TR 83)
  57. _set_timing:
  58. move.d CONFIG_ETRAX_SDRAM_TIMING, $r1
  59. and.d ~(3 << reg_bif_core_rw_sdram_timing___ref___lsb), $r1
  60. move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0
  61. move.d $r1, [$r0]
  62. ; Issue NOP command
  63. move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cmd), $r5
  64. moveq regk_bif_core_nop, $r1
  65. move.d $r1, [$r5]
  66. ; Wait 200us
  67. move.d 10000, $r2
  68. 1: bne 1b
  69. subq 1, $r2
  70. ; Issue initialization command sequence
  71. move.d _sdram_commands_start, $r2
  72. and.d 0x000fffff, $r2 ; Make sure commands are read from flash
  73. move.d _sdram_commands_end, $r3
  74. and.d 0x000fffff, $r3
  75. 1: clear.d $r6
  76. move.b [$r2+], $r6 ; Load command
  77. or.d $r4, $r6 ; Add calculated mrs
  78. move.d $r6, [$r5] ; Write rw_sdram_cmd
  79. ; Wait 80 ns between each command
  80. move.d 4000, $r7
  81. 2: bne 2b
  82. subq 1, $r7
  83. cmp.d $r2, $r3 ; Last command?
  84. bne 1b
  85. nop
  86. ; Start refresh
  87. move.d CONFIG_ETRAX_SDRAM_TIMING, $r1
  88. move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0
  89. move.d $r1, [$r0]
  90. ; Initialization finished
  91. ba _sdram_commands_end
  92. nop
  93. _sdram_commands_start:
  94. .byte regk_bif_core_pre ; Precharge
  95. .byte regk_bif_core_ref ; refresh
  96. .byte regk_bif_core_ref ; refresh
  97. .byte regk_bif_core_ref ; refresh
  98. .byte regk_bif_core_ref ; refresh
  99. .byte regk_bif_core_ref ; refresh
  100. .byte regk_bif_core_ref ; refresh
  101. .byte regk_bif_core_ref ; refresh
  102. .byte regk_bif_core_ref ; refresh
  103. .byte regk_bif_core_mrs ; mrs
  104. _sdram_commands_end: