pci.c 6.2 KB

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  1. /*
  2. * arch/arm/mach-ixp23xx/pci.c
  3. *
  4. * PCI routines for IXP23XX based systems
  5. *
  6. * Copyright (c) 2005 MontaVista Software, Inc.
  7. *
  8. * based on original code:
  9. *
  10. * Author: Naeem Afzal <naeem.m.afzal@intel.com>
  11. * Copyright 2002-2005 Intel Corp.
  12. *
  13. * This program is free software; you can redistribute it and/or modify it
  14. * under the terms of the GNU General Public License as published by the
  15. * Free Software Foundation; either version 2 of the License, or (at your
  16. * option) any later version.
  17. */
  18. #include <linux/config.h>
  19. #include <linux/sched.h>
  20. #include <linux/kernel.h>
  21. #include <linux/pci.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/mm.h>
  24. #include <linux/init.h>
  25. #include <linux/ioport.h>
  26. #include <linux/slab.h>
  27. #include <linux/delay.h>
  28. #include <asm/io.h>
  29. #include <asm/irq.h>
  30. #include <asm/sizes.h>
  31. #include <asm/system.h>
  32. #include <asm/mach/pci.h>
  33. #include <asm/mach-types.h>
  34. #include <asm/hardware.h>
  35. extern int (*external_fault) (unsigned long, struct pt_regs *);
  36. static int pci_master_aborts = 0;
  37. #ifdef DEBUG
  38. #define DBG(x...) printk(x)
  39. #else
  40. #define DBG(x...)
  41. #endif
  42. int clear_master_aborts(void);
  43. static u32
  44. *ixp23xx_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where)
  45. {
  46. u32 *paddress;
  47. /*
  48. * Must be dword aligned
  49. */
  50. where &= ~3;
  51. /*
  52. * For top bus, generate type 0, else type 1
  53. */
  54. if (!bus_nr) {
  55. if (PCI_SLOT(devfn) >= 8)
  56. return 0;
  57. paddress = (u32 *) (IXP23XX_PCI_CFG0_VIRT
  58. | (1 << (PCI_SLOT(devfn) + 16))
  59. | (PCI_FUNC(devfn) << 8) | where);
  60. } else {
  61. paddress = (u32 *) (IXP23XX_PCI_CFG1_VIRT
  62. | (bus_nr << 16)
  63. | (PCI_SLOT(devfn) << 11)
  64. | (PCI_FUNC(devfn) << 8) | where);
  65. }
  66. return paddress;
  67. }
  68. /*
  69. * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
  70. * 0 and 3 are not valid indexes...
  71. */
  72. static u32 bytemask[] = {
  73. /*0*/ 0,
  74. /*1*/ 0xff,
  75. /*2*/ 0xffff,
  76. /*3*/ 0,
  77. /*4*/ 0xffffffff,
  78. };
  79. static int ixp23xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
  80. int where, int size, u32 *value)
  81. {
  82. u32 n;
  83. u32 *addr;
  84. n = where % 4;
  85. DBG("In config_read(%d) %d from dev %d:%d:%d\n", size, where,
  86. bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
  87. addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
  88. if (!addr)
  89. return PCIBIOS_DEVICE_NOT_FOUND;
  90. pci_master_aborts = 0;
  91. *value = (*addr >> (8*n)) & bytemask[size];
  92. if (pci_master_aborts) {
  93. pci_master_aborts = 0;
  94. *value = 0xffffffff;
  95. return PCIBIOS_DEVICE_NOT_FOUND;
  96. }
  97. return PCIBIOS_SUCCESSFUL;
  98. }
  99. /*
  100. * We don't do error checking on the address for writes.
  101. * It's assumed that the user checked for the device existing first
  102. * by doing a read first.
  103. */
  104. static int ixp23xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
  105. int where, int size, u32 value)
  106. {
  107. u32 mask;
  108. u32 *addr;
  109. u32 temp;
  110. mask = ~(bytemask[size] << ((where % 0x4) * 8));
  111. addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
  112. if (!addr)
  113. return PCIBIOS_DEVICE_NOT_FOUND;
  114. temp = (u32) (value) << ((where % 0x4) * 8);
  115. *addr = (*addr & mask) | temp;
  116. clear_master_aborts();
  117. return PCIBIOS_SUCCESSFUL;
  118. }
  119. struct pci_ops ixp23xx_pci_ops = {
  120. .read = ixp23xx_pci_read_config,
  121. .write = ixp23xx_pci_write_config,
  122. };
  123. struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
  124. {
  125. return pci_scan_bus(sysdata->busnr, &ixp23xx_pci_ops, sysdata);
  126. }
  127. int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
  128. {
  129. volatile unsigned long temp;
  130. unsigned long flags;
  131. pci_master_aborts = 1;
  132. local_irq_save(flags);
  133. temp = *IXP23XX_PCI_CONTROL;
  134. /*
  135. * master abort and cmd tgt err
  136. */
  137. if (temp & ((1 << 8) | (1 << 5)))
  138. *IXP23XX_PCI_CONTROL = temp;
  139. temp = *IXP23XX_PCI_CMDSTAT;
  140. if (temp & (1 << 29))
  141. *IXP23XX_PCI_CMDSTAT = temp;
  142. local_irq_restore(flags);
  143. /*
  144. * If it was an imprecise abort, then we need to correct the
  145. * return address to be _after_ the instruction.
  146. */
  147. if (fsr & (1 << 10))
  148. regs->ARM_pc += 4;
  149. return 0;
  150. }
  151. int clear_master_aborts(void)
  152. {
  153. volatile u32 temp;
  154. temp = *IXP23XX_PCI_CONTROL;
  155. /*
  156. * master abort and cmd tgt err
  157. */
  158. if (temp & ((1 << 8) | (1 << 5)))
  159. *IXP23XX_PCI_CONTROL = temp;
  160. temp = *IXP23XX_PCI_CMDSTAT;
  161. if (temp & (1 << 29))
  162. *IXP23XX_PCI_CMDSTAT = temp;
  163. return 0;
  164. }
  165. static void __init ixp23xx_pci_common_init(void)
  166. {
  167. #ifdef __ARMEB__
  168. *IXP23XX_PCI_CONTROL |= 0x20000; /* set I/O swapping */
  169. #endif
  170. /*
  171. * ADDR_31 needs to be clear for PCI memory access to CPP memory
  172. */
  173. *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_ADDR_31;
  174. *IXP23XX_CPP2XSI_CURR_XFER_REG3 |= IXP23XX_CPP2XSI_PSH_OFF;
  175. /*
  176. * Select correct memory for PCI inbound transactions
  177. */
  178. if (ixp23xx_cpp_boot()) {
  179. *IXP23XX_PCI_CPP_ADDR_BITS &= ~(1 << 1);
  180. } else {
  181. *IXP23XX_PCI_CPP_ADDR_BITS |= (1 << 1);
  182. /*
  183. * Enable coherency on A2 silicon.
  184. */
  185. if (arch_is_coherent())
  186. *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_COH_OFF;
  187. }
  188. }
  189. void __init ixp23xx_pci_preinit(void)
  190. {
  191. ixp23xx_pci_common_init();
  192. hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS,
  193. "PCI config cycle to non-existent device");
  194. *IXP23XX_PCI_ADDR_EXT = 0x0000e000;
  195. }
  196. /*
  197. * Prevent PCI layer from seeing the inbound host-bridge resources
  198. */
  199. static void __devinit pci_fixup_ixp23xx(struct pci_dev *dev)
  200. {
  201. int i;
  202. dev->class &= 0xff;
  203. dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
  204. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  205. dev->resource[i].start = 0;
  206. dev->resource[i].end = 0;
  207. dev->resource[i].flags = 0;
  208. }
  209. }
  210. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9002, pci_fixup_ixp23xx);
  211. /*
  212. * IXP2300 systems often have large resource requirements, so we just
  213. * use our own resource space.
  214. */
  215. static struct resource ixp23xx_pci_mem_space = {
  216. .start = IXP23XX_PCI_MEM_START,
  217. .end = IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE - 1,
  218. .flags = IORESOURCE_MEM,
  219. .name = "PCI Mem Space"
  220. };
  221. static struct resource ixp23xx_pci_io_space = {
  222. .start = 0x00000100,
  223. .end = 0x01ffffff,
  224. .flags = IORESOURCE_IO,
  225. .name = "PCI I/O Space"
  226. };
  227. int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys)
  228. {
  229. if (nr >= 1)
  230. return 0;
  231. sys->resource[0] = &ixp23xx_pci_io_space;
  232. sys->resource[1] = &ixp23xx_pci_mem_space;
  233. sys->resource[2] = NULL;
  234. return 1;
  235. }
  236. void ixp23xx_pci_slave_init(void)
  237. {
  238. ixp23xx_pci_common_init();
  239. }