ixdp2351.c 8.1 KB

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  1. /*
  2. * arch/arm/mach-ixp23xx/ixdp2351.c
  3. *
  4. * IXDP2351 board-specific routines
  5. *
  6. * Author: Deepak Saxena <dsaxena@plexity.net>
  7. *
  8. * Copyright 2005 (c) MontaVista Software, Inc.
  9. *
  10. * Based on 2.4 code Copyright 2004 (c) Intel Corporation
  11. *
  12. * This file is licensed under the terms of the GNU General Public
  13. * License version 2. This program is licensed "as is" without any
  14. * warranty of any kind, whether express or implied.
  15. */
  16. #include <linux/config.h>
  17. #include <linux/kernel.h>
  18. #include <linux/init.h>
  19. #include <linux/spinlock.h>
  20. #include <linux/sched.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/serial.h>
  23. #include <linux/tty.h>
  24. #include <linux/bitops.h>
  25. #include <linux/ioport.h>
  26. #include <linux/serial.h>
  27. #include <linux/serial_8250.h>
  28. #include <linux/serial_core.h>
  29. #include <linux/device.h>
  30. #include <linux/mm.h>
  31. #include <linux/pci.h>
  32. #include <linux/mtd/physmap.h>
  33. #include <asm/types.h>
  34. #include <asm/setup.h>
  35. #include <asm/memory.h>
  36. #include <asm/hardware.h>
  37. #include <asm/mach-types.h>
  38. #include <asm/irq.h>
  39. #include <asm/system.h>
  40. #include <asm/tlbflush.h>
  41. #include <asm/pgtable.h>
  42. #include <asm/mach/map.h>
  43. #include <asm/mach/irq.h>
  44. #include <asm/mach/arch.h>
  45. #include <asm/mach/irq.h>
  46. #include <asm/mach/pci.h>
  47. /*
  48. * IXDP2351 Interrupt Handling
  49. */
  50. static void ixdp2351_inta_mask(unsigned int irq)
  51. {
  52. *IXDP2351_CPLD_INTA_MASK_SET_REG = IXDP2351_INTA_IRQ_MASK(irq);
  53. }
  54. static void ixdp2351_inta_unmask(unsigned int irq)
  55. {
  56. *IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(irq);
  57. }
  58. static void ixdp2351_inta_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
  59. {
  60. u16 ex_interrupt =
  61. *IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID;
  62. int i;
  63. desc->chip->mask(irq);
  64. for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) {
  65. if (ex_interrupt & (1 << i)) {
  66. struct irqdesc *cpld_desc;
  67. int cpld_irq =
  68. IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i);
  69. cpld_desc = irq_desc + cpld_irq;
  70. cpld_desc->handle(cpld_irq, cpld_desc, regs);
  71. }
  72. }
  73. desc->chip->unmask(irq);
  74. }
  75. static struct irqchip ixdp2351_inta_chip = {
  76. .ack = ixdp2351_inta_mask,
  77. .mask = ixdp2351_inta_mask,
  78. .unmask = ixdp2351_inta_unmask
  79. };
  80. static void ixdp2351_intb_mask(unsigned int irq)
  81. {
  82. *IXDP2351_CPLD_INTB_MASK_SET_REG = IXDP2351_INTB_IRQ_MASK(irq);
  83. }
  84. static void ixdp2351_intb_unmask(unsigned int irq)
  85. {
  86. *IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(irq);
  87. }
  88. static void ixdp2351_intb_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
  89. {
  90. u16 ex_interrupt =
  91. *IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID;
  92. int i;
  93. desc->chip->ack(irq);
  94. for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) {
  95. if (ex_interrupt & (1 << i)) {
  96. struct irqdesc *cpld_desc;
  97. int cpld_irq =
  98. IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i);
  99. cpld_desc = irq_desc + cpld_irq;
  100. cpld_desc->handle(cpld_irq, cpld_desc, regs);
  101. }
  102. }
  103. desc->chip->unmask(irq);
  104. }
  105. static struct irqchip ixdp2351_intb_chip = {
  106. .ack = ixdp2351_intb_mask,
  107. .mask = ixdp2351_intb_mask,
  108. .unmask = ixdp2351_intb_unmask
  109. };
  110. void ixdp2351_init_irq(void)
  111. {
  112. int irq;
  113. /* Mask all interrupts from CPLD, disable simulation */
  114. *IXDP2351_CPLD_INTA_MASK_SET_REG = (u16) -1;
  115. *IXDP2351_CPLD_INTB_MASK_SET_REG = (u16) -1;
  116. *IXDP2351_CPLD_INTA_SIM_REG = 0;
  117. *IXDP2351_CPLD_INTB_SIM_REG = 0;
  118. ixp23xx_init_irq();
  119. for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE);
  120. irq <
  121. IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + IXDP2351_INTA_IRQ_NUM);
  122. irq++) {
  123. if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
  124. set_irq_flags(irq, IRQF_VALID);
  125. set_irq_handler(irq, do_level_IRQ);
  126. set_irq_chip(irq, &ixdp2351_inta_chip);
  127. }
  128. }
  129. for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE);
  130. irq <
  131. IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + IXDP2351_INTB_IRQ_NUM);
  132. irq++) {
  133. if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
  134. set_irq_flags(irq, IRQF_VALID);
  135. set_irq_handler(irq, do_level_IRQ);
  136. set_irq_chip(irq, &ixdp2351_intb_chip);
  137. }
  138. }
  139. set_irq_chained_handler(IRQ_IXP23XX_INTA, &ixdp2351_inta_handler);
  140. set_irq_chained_handler(IRQ_IXP23XX_INTB, &ixdp2351_intb_handler);
  141. }
  142. /*
  143. * IXDP2351 PCI
  144. */
  145. /*
  146. * This board does not do normal PCI IRQ routing, or any
  147. * sort of swizzling, so we just need to check where on the
  148. * bus the device is and figure out what CPLD pin it is
  149. * being routed to.
  150. */
  151. #define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
  152. static int __init ixdp2351_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
  153. {
  154. u8 bus = dev->bus->number;
  155. u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
  156. struct pci_bus *tmp_bus = dev->bus;
  157. /* Primary bus, no interrupts here */
  158. if (!bus)
  159. return -1;
  160. /* Lookup first leaf in bus tree */
  161. while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL))
  162. tmp_bus = tmp_bus->parent;
  163. /* Select between known bridges */
  164. switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
  165. /* Device is located after first bridge */
  166. case 0x0008:
  167. if (tmp_bus == dev->bus) {
  168. /* Device is located directy after first bridge */
  169. switch (devpin) {
  170. /* Onboard 82546 */
  171. case DEVPIN(1, 1): /* Onboard 82546 ch 0 */
  172. return IRQ_IXDP2351_INTA_82546;
  173. case DEVPIN(1, 2): /* Onboard 82546 ch 1 */
  174. return IRQ_IXDP2351_INTB_82546;
  175. /* PMC SLOT */
  176. case DEVPIN(0, 1): /* PMCP INTA# */
  177. case DEVPIN(2, 4): /* PMCS INTD# */
  178. return IRQ_IXDP2351_SPCI_PMC_INTA;
  179. case DEVPIN(0, 2): /* PMCP INTB# */
  180. case DEVPIN(2, 1): /* PMCS INTA# */
  181. return IRQ_IXDP2351_SPCI_PMC_INTB;
  182. case DEVPIN(0, 3): /* PMCP INTC# */
  183. case DEVPIN(2, 2): /* PMCS INTB# */
  184. return IRQ_IXDP2351_SPCI_PMC_INTC;
  185. case DEVPIN(0, 4): /* PMCP INTD# */
  186. case DEVPIN(2, 3): /* PMCS INTC# */
  187. return IRQ_IXDP2351_SPCI_PMC_INTD;
  188. }
  189. } else {
  190. /* Device is located indirectly after first bridge */
  191. /* Not supported now */
  192. return -1;
  193. }
  194. break;
  195. case 0x0010:
  196. if (tmp_bus == dev->bus) {
  197. /* Device is located directy after second bridge */
  198. /* Secondary bus of second bridge */
  199. switch (devpin) {
  200. case DEVPIN(0, 1): /* DB#0 */
  201. case DEVPIN(0, 2):
  202. case DEVPIN(0, 3):
  203. case DEVPIN(0, 4):
  204. return IRQ_IXDP2351_SPCI_DB_0;
  205. case DEVPIN(1, 1): /* DB#1 */
  206. case DEVPIN(1, 2):
  207. case DEVPIN(1, 3):
  208. case DEVPIN(1, 4):
  209. return IRQ_IXDP2351_SPCI_DB_1;
  210. case DEVPIN(2, 1): /* FIC1 */
  211. case DEVPIN(2, 2):
  212. case DEVPIN(2, 3):
  213. case DEVPIN(2, 4):
  214. case DEVPIN(3, 1): /* FIC2 */
  215. case DEVPIN(3, 2):
  216. case DEVPIN(3, 3):
  217. case DEVPIN(3, 4):
  218. return IRQ_IXDP2351_SPCI_FIC;
  219. }
  220. } else {
  221. /* Device is located indirectly after second bridge */
  222. /* Not supported now */
  223. return -1;
  224. }
  225. break;
  226. }
  227. return -1;
  228. }
  229. struct hw_pci ixdp2351_pci __initdata = {
  230. .nr_controllers = 1,
  231. .preinit = ixp23xx_pci_preinit,
  232. .setup = ixp23xx_pci_setup,
  233. .scan = ixp23xx_pci_scan_bus,
  234. .map_irq = ixdp2351_map_irq,
  235. };
  236. int __init ixdp2351_pci_init(void)
  237. {
  238. if (machine_is_ixdp2351())
  239. pci_common_init(&ixdp2351_pci);
  240. return 0;
  241. }
  242. subsys_initcall(ixdp2351_pci_init);
  243. /*
  244. * IXDP2351 Static Mapped I/O
  245. */
  246. static struct map_desc ixdp2351_io_desc[] __initdata = {
  247. {
  248. .virtual = IXDP2351_NP_VIRT_BASE,
  249. .pfn = __phys_to_pfn((u64)IXDP2351_NP_PHYS_BASE),
  250. .length = IXDP2351_NP_PHYS_SIZE,
  251. .type = MT_DEVICE
  252. }, {
  253. .virtual = IXDP2351_BB_BASE_VIRT,
  254. .pfn = __phys_to_pfn((u64)IXDP2351_BB_BASE_PHYS),
  255. .length = IXDP2351_BB_SIZE,
  256. .type = MT_DEVICE
  257. }
  258. };
  259. static void __init ixdp2351_map_io(void)
  260. {
  261. ixp23xx_map_io();
  262. iotable_init(ixdp2351_io_desc, ARRAY_SIZE(ixdp2351_io_desc));
  263. }
  264. static void __init ixdp2351_init(void)
  265. {
  266. physmap_configure(0x90000000, 0x04000000, 1, NULL);
  267. /*
  268. * Mark flash as writeable
  269. */
  270. IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
  271. IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
  272. IXP23XX_EXP_CS0[2] |= IXP23XX_FLASH_WRITABLE;
  273. IXP23XX_EXP_CS0[3] |= IXP23XX_FLASH_WRITABLE;
  274. ixp23xx_sys_init();
  275. }
  276. MACHINE_START(IXDP2351, "Intel IXDP2351 Development Platform")
  277. /* Maintainer: MontaVista Software, Inc. */
  278. .phys_io = IXP23XX_PERIPHERAL_PHYS,
  279. .io_pg_offst = ((IXP23XX_PERIPHERAL_VIRT >> 18)) & 0xfffc,
  280. .map_io = ixdp2351_map_io,
  281. .init_irq = ixdp2351_init_irq,
  282. .timer = &ixp23xx_timer,
  283. .boot_params = 0x00000100,
  284. .init_machine = ixdp2351_init,
  285. MACHINE_END