makefiles.txt 38 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156
  1. Linux Kernel Makefiles
  2. This document describes the Linux kernel Makefiles.
  3. === Table of Contents
  4. === 1 Overview
  5. === 2 Who does what
  6. === 3 The kbuild files
  7. --- 3.1 Goal definitions
  8. --- 3.2 Built-in object goals - obj-y
  9. --- 3.3 Loadable module goals - obj-m
  10. --- 3.4 Objects which export symbols
  11. --- 3.5 Library file goals - lib-y
  12. --- 3.6 Descending down in directories
  13. --- 3.7 Compilation flags
  14. --- 3.8 Command line dependency
  15. --- 3.9 Dependency tracking
  16. --- 3.10 Special Rules
  17. --- 3.11 $(CC) support functions
  18. === 4 Host Program support
  19. --- 4.1 Simple Host Program
  20. --- 4.2 Composite Host Programs
  21. --- 4.3 Defining shared libraries
  22. --- 4.4 Using C++ for host programs
  23. --- 4.5 Controlling compiler options for host programs
  24. --- 4.6 When host programs are actually built
  25. --- 4.7 Using hostprogs-$(CONFIG_FOO)
  26. === 5 Kbuild clean infrastructure
  27. === 6 Architecture Makefiles
  28. --- 6.1 Set variables to tweak the build to the architecture
  29. --- 6.2 Add prerequisites to archprepare:
  30. --- 6.3 List directories to visit when descending
  31. --- 6.4 Architecture specific boot images
  32. --- 6.5 Building non-kbuild targets
  33. --- 6.6 Commands useful for building a boot image
  34. --- 6.7 Custom kbuild commands
  35. --- 6.8 Preprocessing linker scripts
  36. === 7 Kbuild Variables
  37. === 8 Makefile language
  38. === 9 Credits
  39. === 10 TODO
  40. === 1 Overview
  41. The Makefiles have five parts:
  42. Makefile the top Makefile.
  43. .config the kernel configuration file.
  44. arch/$(ARCH)/Makefile the arch Makefile.
  45. scripts/Makefile.* common rules etc. for all kbuild Makefiles.
  46. kbuild Makefiles there are about 500 of these.
  47. The top Makefile reads the .config file, which comes from the kernel
  48. configuration process.
  49. The top Makefile is responsible for building two major products: vmlinux
  50. (the resident kernel image) and modules (any module files).
  51. It builds these goals by recursively descending into the subdirectories of
  52. the kernel source tree.
  53. The list of subdirectories which are visited depends upon the kernel
  54. configuration. The top Makefile textually includes an arch Makefile
  55. with the name arch/$(ARCH)/Makefile. The arch Makefile supplies
  56. architecture-specific information to the top Makefile.
  57. Each subdirectory has a kbuild Makefile which carries out the commands
  58. passed down from above. The kbuild Makefile uses information from the
  59. .config file to construct various file lists used by kbuild to build
  60. any built-in or modular targets.
  61. scripts/Makefile.* contains all the definitions/rules etc. that
  62. are used to build the kernel based on the kbuild makefiles.
  63. === 2 Who does what
  64. People have four different relationships with the kernel Makefiles.
  65. *Users* are people who build kernels. These people type commands such as
  66. "make menuconfig" or "make". They usually do not read or edit
  67. any kernel Makefiles (or any other source files).
  68. *Normal developers* are people who work on features such as device
  69. drivers, file systems, and network protocols. These people need to
  70. maintain the kbuild Makefiles for the subsystem that they are
  71. working on. In order to do this effectively, they need some overall
  72. knowledge about the kernel Makefiles, plus detailed knowledge about the
  73. public interface for kbuild.
  74. *Arch developers* are people who work on an entire architecture, such
  75. as sparc or ia64. Arch developers need to know about the arch Makefile
  76. as well as kbuild Makefiles.
  77. *Kbuild developers* are people who work on the kernel build system itself.
  78. These people need to know about all aspects of the kernel Makefiles.
  79. This document is aimed towards normal developers and arch developers.
  80. === 3 The kbuild files
  81. Most Makefiles within the kernel are kbuild Makefiles that use the
  82. kbuild infrastructure. This chapter introduce the syntax used in the
  83. kbuild makefiles.
  84. The preferred name for the kbuild files are 'Makefile' but 'Kbuild' can
  85. be used and if both a 'Makefile' and a 'Kbuild' file exists then the 'Kbuild'
  86. file will be used.
  87. Section 3.1 "Goal definitions" is a quick intro, further chapters provide
  88. more details, with real examples.
  89. --- 3.1 Goal definitions
  90. Goal definitions are the main part (heart) of the kbuild Makefile.
  91. These lines define the files to be built, any special compilation
  92. options, and any subdirectories to be entered recursively.
  93. The most simple kbuild makefile contains one line:
  94. Example:
  95. obj-y += foo.o
  96. This tell kbuild that there is one object in that directory named
  97. foo.o. foo.o will be built from foo.c or foo.S.
  98. If foo.o shall be built as a module, the variable obj-m is used.
  99. Therefore the following pattern is often used:
  100. Example:
  101. obj-$(CONFIG_FOO) += foo.o
  102. $(CONFIG_FOO) evaluates to either y (for built-in) or m (for module).
  103. If CONFIG_FOO is neither y nor m, then the file will not be compiled
  104. nor linked.
  105. --- 3.2 Built-in object goals - obj-y
  106. The kbuild Makefile specifies object files for vmlinux
  107. in the lists $(obj-y). These lists depend on the kernel
  108. configuration.
  109. Kbuild compiles all the $(obj-y) files. It then calls
  110. "$(LD) -r" to merge these files into one built-in.o file.
  111. built-in.o is later linked into vmlinux by the parent Makefile.
  112. The order of files in $(obj-y) is significant. Duplicates in
  113. the lists are allowed: the first instance will be linked into
  114. built-in.o and succeeding instances will be ignored.
  115. Link order is significant, because certain functions
  116. (module_init() / __initcall) will be called during boot in the
  117. order they appear. So keep in mind that changing the link
  118. order may e.g. change the order in which your SCSI
  119. controllers are detected, and thus you disks are renumbered.
  120. Example:
  121. #drivers/isdn/i4l/Makefile
  122. # Makefile for the kernel ISDN subsystem and device drivers.
  123. # Each configuration option enables a list of files.
  124. obj-$(CONFIG_ISDN) += isdn.o
  125. obj-$(CONFIG_ISDN_PPP_BSDCOMP) += isdn_bsdcomp.o
  126. --- 3.3 Loadable module goals - obj-m
  127. $(obj-m) specify object files which are built as loadable
  128. kernel modules.
  129. A module may be built from one source file or several source
  130. files. In the case of one source file, the kbuild makefile
  131. simply adds the file to $(obj-m).
  132. Example:
  133. #drivers/isdn/i4l/Makefile
  134. obj-$(CONFIG_ISDN_PPP_BSDCOMP) += isdn_bsdcomp.o
  135. Note: In this example $(CONFIG_ISDN_PPP_BSDCOMP) evaluates to 'm'
  136. If a kernel module is built from several source files, you specify
  137. that you want to build a module in the same way as above.
  138. Kbuild needs to know which the parts that you want to build your
  139. module from, so you have to tell it by setting an
  140. $(<module_name>-objs) variable.
  141. Example:
  142. #drivers/isdn/i4l/Makefile
  143. obj-$(CONFIG_ISDN) += isdn.o
  144. isdn-objs := isdn_net_lib.o isdn_v110.o isdn_common.o
  145. In this example, the module name will be isdn.o. Kbuild will
  146. compile the objects listed in $(isdn-objs) and then run
  147. "$(LD) -r" on the list of these files to generate isdn.o.
  148. Kbuild recognises objects used for composite objects by the suffix
  149. -objs, and the suffix -y. This allows the Makefiles to use
  150. the value of a CONFIG_ symbol to determine if an object is part
  151. of a composite object.
  152. Example:
  153. #fs/ext2/Makefile
  154. obj-$(CONFIG_EXT2_FS) += ext2.o
  155. ext2-y := balloc.o bitmap.o
  156. ext2-$(CONFIG_EXT2_FS_XATTR) += xattr.o
  157. In this example xattr.o is only part of the composite object
  158. ext2.o, if $(CONFIG_EXT2_FS_XATTR) evaluates to 'y'.
  159. Note: Of course, when you are building objects into the kernel,
  160. the syntax above will also work. So, if you have CONFIG_EXT2_FS=y,
  161. kbuild will build an ext2.o file for you out of the individual
  162. parts and then link this into built-in.o, as you would expect.
  163. --- 3.4 Objects which export symbols
  164. No special notation is required in the makefiles for
  165. modules exporting symbols.
  166. --- 3.5 Library file goals - lib-y
  167. Objects listed with obj-* are used for modules or
  168. combined in a built-in.o for that specific directory.
  169. There is also the possibility to list objects that will
  170. be included in a library, lib.a.
  171. All objects listed with lib-y are combined in a single
  172. library for that directory.
  173. Objects that are listed in obj-y and additional listed in
  174. lib-y will not be included in the library, since they will anyway
  175. be accessible.
  176. For consistency objects listed in lib-m will be included in lib.a.
  177. Note that the same kbuild makefile may list files to be built-in
  178. and to be part of a library. Therefore the same directory
  179. may contain both a built-in.o and a lib.a file.
  180. Example:
  181. #arch/i386/lib/Makefile
  182. lib-y := checksum.o delay.o
  183. This will create a library lib.a based on checksum.o and delay.o.
  184. For kbuild to actually recognize that there is a lib.a being build
  185. the directory shall be listed in libs-y.
  186. See also "6.3 List directories to visit when descending".
  187. Usage of lib-y is normally restricted to lib/ and arch/*/lib.
  188. --- 3.6 Descending down in directories
  189. A Makefile is only responsible for building objects in its own
  190. directory. Files in subdirectories should be taken care of by
  191. Makefiles in these subdirs. The build system will automatically
  192. invoke make recursively in subdirectories, provided you let it know of
  193. them.
  194. To do so obj-y and obj-m are used.
  195. ext2 lives in a separate directory, and the Makefile present in fs/
  196. tells kbuild to descend down using the following assignment.
  197. Example:
  198. #fs/Makefile
  199. obj-$(CONFIG_EXT2_FS) += ext2/
  200. If CONFIG_EXT2_FS is set to either 'y' (built-in) or 'm' (modular)
  201. the corresponding obj- variable will be set, and kbuild will descend
  202. down in the ext2 directory.
  203. Kbuild only uses this information to decide that it needs to visit
  204. the directory, it is the Makefile in the subdirectory that
  205. specifies what is modules and what is built-in.
  206. It is good practice to use a CONFIG_ variable when assigning directory
  207. names. This allows kbuild to totally skip the directory if the
  208. corresponding CONFIG_ option is neither 'y' nor 'm'.
  209. --- 3.7 Compilation flags
  210. EXTRA_CFLAGS, EXTRA_AFLAGS, EXTRA_LDFLAGS, EXTRA_ARFLAGS
  211. All the EXTRA_ variables apply only to the kbuild makefile
  212. where they are assigned. The EXTRA_ variables apply to all
  213. commands executed in the kbuild makefile.
  214. $(EXTRA_CFLAGS) specifies options for compiling C files with
  215. $(CC).
  216. Example:
  217. # drivers/sound/emu10k1/Makefile
  218. EXTRA_CFLAGS += -I$(obj)
  219. ifdef DEBUG
  220. EXTRA_CFLAGS += -DEMU10K1_DEBUG
  221. endif
  222. This variable is necessary because the top Makefile owns the
  223. variable $(CFLAGS) and uses it for compilation flags for the
  224. entire tree.
  225. $(EXTRA_AFLAGS) is a similar string for per-directory options
  226. when compiling assembly language source.
  227. Example:
  228. #arch/x86_64/kernel/Makefile
  229. EXTRA_AFLAGS := -traditional
  230. $(EXTRA_LDFLAGS) and $(EXTRA_ARFLAGS) are similar strings for
  231. per-directory options to $(LD) and $(AR).
  232. Example:
  233. #arch/m68k/fpsp040/Makefile
  234. EXTRA_LDFLAGS := -x
  235. CFLAGS_$@, AFLAGS_$@
  236. CFLAGS_$@ and AFLAGS_$@ only apply to commands in current
  237. kbuild makefile.
  238. $(CFLAGS_$@) specifies per-file options for $(CC). The $@
  239. part has a literal value which specifies the file that it is for.
  240. Example:
  241. # drivers/scsi/Makefile
  242. CFLAGS_aha152x.o = -DAHA152X_STAT -DAUTOCONF
  243. CFLAGS_gdth.o = # -DDEBUG_GDTH=2 -D__SERIAL__ -D__COM2__ \
  244. -DGDTH_STATISTICS
  245. CFLAGS_seagate.o = -DARBITRATE -DPARITY -DSEAGATE_USE_ASM
  246. These three lines specify compilation flags for aha152x.o,
  247. gdth.o, and seagate.o
  248. $(AFLAGS_$@) is a similar feature for source files in assembly
  249. languages.
  250. Example:
  251. # arch/arm/kernel/Makefile
  252. AFLAGS_head-armv.o := -DTEXTADDR=$(TEXTADDR) -traditional
  253. AFLAGS_head-armo.o := -DTEXTADDR=$(TEXTADDR) -traditional
  254. --- 3.9 Dependency tracking
  255. Kbuild tracks dependencies on the following:
  256. 1) All prerequisite files (both *.c and *.h)
  257. 2) CONFIG_ options used in all prerequisite files
  258. 3) Command-line used to compile target
  259. Thus, if you change an option to $(CC) all affected files will
  260. be re-compiled.
  261. --- 3.10 Special Rules
  262. Special rules are used when the kbuild infrastructure does
  263. not provide the required support. A typical example is
  264. header files generated during the build process.
  265. Another example is the architecture specific Makefiles which
  266. needs special rules to prepare boot images etc.
  267. Special rules are written as normal Make rules.
  268. Kbuild is not executing in the directory where the Makefile is
  269. located, so all special rules shall provide a relative
  270. path to prerequisite files and target files.
  271. Two variables are used when defining special rules:
  272. $(src)
  273. $(src) is a relative path which points to the directory
  274. where the Makefile is located. Always use $(src) when
  275. referring to files located in the src tree.
  276. $(obj)
  277. $(obj) is a relative path which points to the directory
  278. where the target is saved. Always use $(obj) when
  279. referring to generated files.
  280. Example:
  281. #drivers/scsi/Makefile
  282. $(obj)/53c8xx_d.h: $(src)/53c7,8xx.scr $(src)/script_asm.pl
  283. $(CPP) -DCHIP=810 - < $< | ... $(src)/script_asm.pl
  284. This is a special rule, following the normal syntax
  285. required by make.
  286. The target file depends on two prerequisite files. References
  287. to the target file are prefixed with $(obj), references
  288. to prerequisites are referenced with $(src) (because they are not
  289. generated files).
  290. --- 3.11 $(CC) support functions
  291. The kernel may be build with several different versions of
  292. $(CC), each supporting a unique set of features and options.
  293. kbuild provide basic support to check for valid options for $(CC).
  294. $(CC) is useally the gcc compiler, but other alternatives are
  295. available.
  296. as-option
  297. as-option is used to check if $(CC) when used to compile
  298. assembler (*.S) files supports the given option. An optional
  299. second option may be specified if first option are not supported.
  300. Example:
  301. #arch/sh/Makefile
  302. cflags-y += $(call as-option,-Wa$(comma)-isa=$(isa-y),)
  303. In the above example cflags-y will be assinged the the option
  304. -Wa$(comma)-isa=$(isa-y) if it is supported by $(CC).
  305. The second argument is optional, and if supplied will be used
  306. if first argument is not supported.
  307. cc-option
  308. cc-option is used to check if $(CC) support a given option, and not
  309. supported to use an optional second option.
  310. Example:
  311. #arch/i386/Makefile
  312. cflags-y += $(call cc-option,-march=pentium-mmx,-march=i586)
  313. In the above example cflags-y will be assigned the option
  314. -march=pentium-mmx if supported by $(CC), otherwise -march-i586.
  315. The second argument to cc-option is optional, and if omitted
  316. cflags-y will be assigned no value if first option is not supported.
  317. cc-option-yn
  318. cc-option-yn is used to check if gcc supports a given option
  319. and return 'y' if supported, otherwise 'n'.
  320. Example:
  321. #arch/ppc/Makefile
  322. biarch := $(call cc-option-yn, -m32)
  323. aflags-$(biarch) += -a32
  324. cflags-$(biarch) += -m32
  325. In the above example $(biarch) is set to y if $(CC) supports the -m32
  326. option. When $(biarch) equals to y the expanded variables $(aflags-y)
  327. and $(cflags-y) will be assigned the values -a32 and -m32.
  328. cc-option-align
  329. gcc version >= 3.0 shifted type of options used to speify
  330. alignment of functions, loops etc. $(cc-option-align) whrn used
  331. as prefix to the align options will select the right prefix:
  332. gcc < 3.00
  333. cc-option-align = -malign
  334. gcc >= 3.00
  335. cc-option-align = -falign
  336. Example:
  337. CFLAGS += $(cc-option-align)-functions=4
  338. In the above example the option -falign-functions=4 is used for
  339. gcc >= 3.00. For gcc < 3.00 -malign-functions=4 is used.
  340. cc-version
  341. cc-version return a numerical version of the $(CC) compiler version.
  342. The format is <major><minor> where both are two digits. So for example
  343. gcc 3.41 would return 0341.
  344. cc-version is useful when a specific $(CC) version is faulty in one
  345. area, for example the -mregparm=3 were broken in some gcc version
  346. even though the option was accepted by gcc.
  347. Example:
  348. #arch/i386/Makefile
  349. cflags-y += $(shell \
  350. if [ $(call cc-version) -ge 0300 ] ; then \
  351. echo "-mregparm=3"; fi ;)
  352. In the above example -mregparm=3 is only used for gcc version greater
  353. than or equal to gcc 3.0.
  354. cc-ifversion
  355. cc-ifversion test the version of $(CC) and equals last argument if
  356. version expression is true.
  357. Example:
  358. #fs/reiserfs/Makefile
  359. EXTRA_CFLAGS := $(call cc-ifversion, -lt, 0402, -O1)
  360. In this example EXTRA_CFLAGS will be assigned the value -O1 if the
  361. $(CC) version is less than 4.2.
  362. cc-ifversion takes all the shell operators:
  363. -eq, -ne, -lt, -le, -gt, and -ge
  364. The third parameter may be a text as in this example, but it may also
  365. be an expanded variable or a macro.
  366. === 4 Host Program support
  367. Kbuild supports building executables on the host for use during the
  368. compilation stage.
  369. Two steps are required in order to use a host executable.
  370. The first step is to tell kbuild that a host program exists. This is
  371. done utilising the variable hostprogs-y.
  372. The second step is to add an explicit dependency to the executable.
  373. This can be done in two ways. Either add the dependency in a rule,
  374. or utilise the variable $(always).
  375. Both possibilities are described in the following.
  376. --- 4.1 Simple Host Program
  377. In some cases there is a need to compile and run a program on the
  378. computer where the build is running.
  379. The following line tells kbuild that the program bin2hex shall be
  380. built on the build host.
  381. Example:
  382. hostprogs-y := bin2hex
  383. Kbuild assumes in the above example that bin2hex is made from a single
  384. c-source file named bin2hex.c located in the same directory as
  385. the Makefile.
  386. --- 4.2 Composite Host Programs
  387. Host programs can be made up based on composite objects.
  388. The syntax used to define composite objects for host programs is
  389. similar to the syntax used for kernel objects.
  390. $(<executeable>-objs) list all objects used to link the final
  391. executable.
  392. Example:
  393. #scripts/lxdialog/Makefile
  394. hostprogs-y := lxdialog
  395. lxdialog-objs := checklist.o lxdialog.o
  396. Objects with extension .o are compiled from the corresponding .c
  397. files. In the above example checklist.c is compiled to checklist.o
  398. and lxdialog.c is compiled to lxdialog.o.
  399. Finally the two .o files are linked to the executable, lxdialog.
  400. Note: The syntax <executable>-y is not permitted for host-programs.
  401. --- 4.3 Defining shared libraries
  402. Objects with extension .so are considered shared libraries, and
  403. will be compiled as position independent objects.
  404. Kbuild provides support for shared libraries, but the usage
  405. shall be restricted.
  406. In the following example the libkconfig.so shared library is used
  407. to link the executable conf.
  408. Example:
  409. #scripts/kconfig/Makefile
  410. hostprogs-y := conf
  411. conf-objs := conf.o libkconfig.so
  412. libkconfig-objs := expr.o type.o
  413. Shared libraries always require a corresponding -objs line, and
  414. in the example above the shared library libkconfig is composed by
  415. the two objects expr.o and type.o.
  416. expr.o and type.o will be built as position independent code and
  417. linked as a shared library libkconfig.so. C++ is not supported for
  418. shared libraries.
  419. --- 4.4 Using C++ for host programs
  420. kbuild offers support for host programs written in C++. This was
  421. introduced solely to support kconfig, and is not recommended
  422. for general use.
  423. Example:
  424. #scripts/kconfig/Makefile
  425. hostprogs-y := qconf
  426. qconf-cxxobjs := qconf.o
  427. In the example above the executable is composed of the C++ file
  428. qconf.cc - identified by $(qconf-cxxobjs).
  429. If qconf is composed by a mixture of .c and .cc files, then an
  430. additional line can be used to identify this.
  431. Example:
  432. #scripts/kconfig/Makefile
  433. hostprogs-y := qconf
  434. qconf-cxxobjs := qconf.o
  435. qconf-objs := check.o
  436. --- 4.5 Controlling compiler options for host programs
  437. When compiling host programs, it is possible to set specific flags.
  438. The programs will always be compiled utilising $(HOSTCC) passed
  439. the options specified in $(HOSTCFLAGS).
  440. To set flags that will take effect for all host programs created
  441. in that Makefile use the variable HOST_EXTRACFLAGS.
  442. Example:
  443. #scripts/lxdialog/Makefile
  444. HOST_EXTRACFLAGS += -I/usr/include/ncurses
  445. To set specific flags for a single file the following construction
  446. is used:
  447. Example:
  448. #arch/ppc64/boot/Makefile
  449. HOSTCFLAGS_piggyback.o := -DKERNELBASE=$(KERNELBASE)
  450. It is also possible to specify additional options to the linker.
  451. Example:
  452. #scripts/kconfig/Makefile
  453. HOSTLOADLIBES_qconf := -L$(QTDIR)/lib
  454. When linking qconf it will be passed the extra option "-L$(QTDIR)/lib".
  455. --- 4.6 When host programs are actually built
  456. Kbuild will only build host-programs when they are referenced
  457. as a prerequisite.
  458. This is possible in two ways:
  459. (1) List the prerequisite explicitly in a special rule.
  460. Example:
  461. #drivers/pci/Makefile
  462. hostprogs-y := gen-devlist
  463. $(obj)/devlist.h: $(src)/pci.ids $(obj)/gen-devlist
  464. ( cd $(obj); ./gen-devlist ) < $<
  465. The target $(obj)/devlist.h will not be built before
  466. $(obj)/gen-devlist is updated. Note that references to
  467. the host programs in special rules must be prefixed with $(obj).
  468. (2) Use $(always)
  469. When there is no suitable special rule, and the host program
  470. shall be built when a makefile is entered, the $(always)
  471. variable shall be used.
  472. Example:
  473. #scripts/lxdialog/Makefile
  474. hostprogs-y := lxdialog
  475. always := $(hostprogs-y)
  476. This will tell kbuild to build lxdialog even if not referenced in
  477. any rule.
  478. --- 4.7 Using hostprogs-$(CONFIG_FOO)
  479. A typcal pattern in a Kbuild file lok like this:
  480. Example:
  481. #scripts/Makefile
  482. hostprogs-$(CONFIG_KALLSYMS) += kallsyms
  483. Kbuild knows about both 'y' for built-in and 'm' for module.
  484. So if a config symbol evaluate to 'm', kbuild will still build
  485. the binary. In other words Kbuild handle hostprogs-m exactly
  486. like hostprogs-y. But only hostprogs-y is recommend used
  487. when no CONFIG symbol are involved.
  488. === 5 Kbuild clean infrastructure
  489. "make clean" deletes most generated files in the src tree where the kernel
  490. is compiled. This includes generated files such as host programs.
  491. Kbuild knows targets listed in $(hostprogs-y), $(hostprogs-m), $(always),
  492. $(extra-y) and $(targets). They are all deleted during "make clean".
  493. Files matching the patterns "*.[oas]", "*.ko", plus some additional files
  494. generated by kbuild are deleted all over the kernel src tree when
  495. "make clean" is executed.
  496. Additional files can be specified in kbuild makefiles by use of $(clean-files).
  497. Example:
  498. #drivers/pci/Makefile
  499. clean-files := devlist.h classlist.h
  500. When executing "make clean", the two files "devlist.h classlist.h" will
  501. be deleted. Kbuild will assume files to be in same relative directory as the
  502. Makefile except if an absolute path is specified (path starting with '/').
  503. To delete a directory hirachy use:
  504. Example:
  505. #scripts/package/Makefile
  506. clean-dirs := $(objtree)/debian/
  507. This will delete the directory debian, including all subdirectories.
  508. Kbuild will assume the directories to be in the same relative path as the
  509. Makefile if no absolute path is specified (path does not start with '/').
  510. Usually kbuild descends down in subdirectories due to "obj-* := dir/",
  511. but in the architecture makefiles where the kbuild infrastructure
  512. is not sufficient this sometimes needs to be explicit.
  513. Example:
  514. #arch/i386/boot/Makefile
  515. subdir- := compressed/
  516. The above assignment instructs kbuild to descend down in the
  517. directory compressed/ when "make clean" is executed.
  518. To support the clean infrastructure in the Makefiles that builds the
  519. final bootimage there is an optional target named archclean:
  520. Example:
  521. #arch/i386/Makefile
  522. archclean:
  523. $(Q)$(MAKE) $(clean)=arch/i386/boot
  524. When "make clean" is executed, make will descend down in arch/i386/boot,
  525. and clean as usual. The Makefile located in arch/i386/boot/ may use
  526. the subdir- trick to descend further down.
  527. Note 1: arch/$(ARCH)/Makefile cannot use "subdir-", because that file is
  528. included in the top level makefile, and the kbuild infrastructure
  529. is not operational at that point.
  530. Note 2: All directories listed in core-y, libs-y, drivers-y and net-y will
  531. be visited during "make clean".
  532. === 6 Architecture Makefiles
  533. The top level Makefile sets up the environment and does the preparation,
  534. before starting to descend down in the individual directories.
  535. The top level makefile contains the generic part, whereas the
  536. arch/$(ARCH)/Makefile contains what is required to set-up kbuild
  537. to the said architecture.
  538. To do so arch/$(ARCH)/Makefile sets a number of variables, and defines
  539. a few targets.
  540. When kbuild executes the following steps are followed (roughly):
  541. 1) Configuration of the kernel => produced .config
  542. 2) Store kernel version in include/linux/version.h
  543. 3) Symlink include/asm to include/asm-$(ARCH)
  544. 4) Updating all other prerequisites to the target prepare:
  545. - Additional prerequisites are specified in arch/$(ARCH)/Makefile
  546. 5) Recursively descend down in all directories listed in
  547. init-* core* drivers-* net-* libs-* and build all targets.
  548. - The value of the above variables are extended in arch/$(ARCH)/Makefile.
  549. 6) All object files are then linked and the resulting file vmlinux is
  550. located at the root of the src tree.
  551. The very first objects linked are listed in head-y, assigned by
  552. arch/$(ARCH)/Makefile.
  553. 7) Finally the architecture specific part does any required post processing
  554. and builds the final bootimage.
  555. - This includes building boot records
  556. - Preparing initrd images and the like
  557. --- 6.1 Set variables to tweak the build to the architecture
  558. LDFLAGS Generic $(LD) options
  559. Flags used for all invocations of the linker.
  560. Often specifying the emulation is sufficient.
  561. Example:
  562. #arch/s390/Makefile
  563. LDFLAGS := -m elf_s390
  564. Note: EXTRA_LDFLAGS and LDFLAGS_$@ can be used to further customise
  565. the flags used. See chapter 7.
  566. LDFLAGS_MODULE Options for $(LD) when linking modules
  567. LDFLAGS_MODULE is used to set specific flags for $(LD) when
  568. linking the .ko files used for modules.
  569. Default is "-r", for relocatable output.
  570. LDFLAGS_vmlinux Options for $(LD) when linking vmlinux
  571. LDFLAGS_vmlinux is used to specify additional flags to pass to
  572. the linker when linking the final vmlinux.
  573. LDFLAGS_vmlinux uses the LDFLAGS_$@ support.
  574. Example:
  575. #arch/i386/Makefile
  576. LDFLAGS_vmlinux := -e stext
  577. OBJCOPYFLAGS objcopy flags
  578. When $(call if_changed,objcopy) is used to translate a .o file,
  579. then the flags specified in OBJCOPYFLAGS will be used.
  580. $(call if_changed,objcopy) is often used to generate raw binaries on
  581. vmlinux.
  582. Example:
  583. #arch/s390/Makefile
  584. OBJCOPYFLAGS := -O binary
  585. #arch/s390/boot/Makefile
  586. $(obj)/image: vmlinux FORCE
  587. $(call if_changed,objcopy)
  588. In this example the binary $(obj)/image is a binary version of
  589. vmlinux. The usage of $(call if_changed,xxx) will be described later.
  590. AFLAGS $(AS) assembler flags
  591. Default value - see top level Makefile
  592. Append or modify as required per architecture.
  593. Example:
  594. #arch/sparc64/Makefile
  595. AFLAGS += -m64 -mcpu=ultrasparc
  596. CFLAGS $(CC) compiler flags
  597. Default value - see top level Makefile
  598. Append or modify as required per architecture.
  599. Often the CFLAGS variable depends on the configuration.
  600. Example:
  601. #arch/i386/Makefile
  602. cflags-$(CONFIG_M386) += -march=i386
  603. CFLAGS += $(cflags-y)
  604. Many arch Makefiles dynamically run the target C compiler to
  605. probe supported options:
  606. #arch/i386/Makefile
  607. ...
  608. cflags-$(CONFIG_MPENTIUMII) += $(call cc-option,\
  609. -march=pentium2,-march=i686)
  610. ...
  611. # Disable unit-at-a-time mode ...
  612. CFLAGS += $(call cc-option,-fno-unit-at-a-time)
  613. ...
  614. The first examples utilises the trick that a config option expands
  615. to 'y' when selected.
  616. CFLAGS_KERNEL $(CC) options specific for built-in
  617. $(CFLAGS_KERNEL) contains extra C compiler flags used to compile
  618. resident kernel code.
  619. CFLAGS_MODULE $(CC) options specific for modules
  620. $(CFLAGS_MODULE) contains extra C compiler flags used to compile code
  621. for loadable kernel modules.
  622. --- 6.2 Add prerequisites to archprepare:
  623. The archprepare: rule is used to list prerequisites that needs to be
  624. built before starting to descend down in the subdirectories.
  625. This is usual header files containing assembler constants.
  626. Example:
  627. #arch/arm/Makefile
  628. archprepare: maketools
  629. In this example the file target maketools will be processed
  630. before descending down in the subdirectories.
  631. See also chapter XXX-TODO that describe how kbuild supports
  632. generating offset header files.
  633. --- 6.3 List directories to visit when descending
  634. An arch Makefile cooperates with the top Makefile to define variables
  635. which specify how to build the vmlinux file. Note that there is no
  636. corresponding arch-specific section for modules; the module-building
  637. machinery is all architecture-independent.
  638. head-y, init-y, core-y, libs-y, drivers-y, net-y
  639. $(head-y) list objects to be linked first in vmlinux.
  640. $(libs-y) list directories where a lib.a archive can be located.
  641. The rest list directories where a built-in.o object file can be located.
  642. $(init-y) objects will be located after $(head-y).
  643. Then the rest follows in this order:
  644. $(core-y), $(libs-y), $(drivers-y) and $(net-y).
  645. The top level Makefile define values for all generic directories,
  646. and arch/$(ARCH)/Makefile only adds architecture specific directories.
  647. Example:
  648. #arch/sparc64/Makefile
  649. core-y += arch/sparc64/kernel/
  650. libs-y += arch/sparc64/prom/ arch/sparc64/lib/
  651. drivers-$(CONFIG_OPROFILE) += arch/sparc64/oprofile/
  652. --- 6.4 Architecture specific boot images
  653. An arch Makefile specifies goals that take the vmlinux file, compress
  654. it, wrap it in bootstrapping code, and copy the resulting files
  655. somewhere. This includes various kinds of installation commands.
  656. The actual goals are not standardized across architectures.
  657. It is common to locate any additional processing in a boot/
  658. directory below arch/$(ARCH)/.
  659. Kbuild does not provide any smart way to support building a
  660. target specified in boot/. Therefore arch/$(ARCH)/Makefile shall
  661. call make manually to build a target in boot/.
  662. The recommended approach is to include shortcuts in
  663. arch/$(ARCH)/Makefile, and use the full path when calling down
  664. into the arch/$(ARCH)/boot/Makefile.
  665. Example:
  666. #arch/i386/Makefile
  667. boot := arch/i386/boot
  668. bzImage: vmlinux
  669. $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
  670. "$(Q)$(MAKE) $(build)=<dir>" is the recommended way to invoke
  671. make in a subdirectory.
  672. There are no rules for naming of the architecture specific targets,
  673. but executing "make help" will list all relevant targets.
  674. To support this $(archhelp) must be defined.
  675. Example:
  676. #arch/i386/Makefile
  677. define archhelp
  678. echo '* bzImage - Image (arch/$(ARCH)/boot/bzImage)'
  679. endef
  680. When make is executed without arguments, the first goal encountered
  681. will be built. In the top level Makefile the first goal present
  682. is all:.
  683. An architecture shall always per default build a bootable image.
  684. In "make help" the default goal is highlighted with a '*'.
  685. Add a new prerequisite to all: to select a default goal different
  686. from vmlinux.
  687. Example:
  688. #arch/i386/Makefile
  689. all: bzImage
  690. When "make" is executed without arguments, bzImage will be built.
  691. --- 6.5 Building non-kbuild targets
  692. extra-y
  693. extra-y specify additional targets created in the current
  694. directory, in addition to any targets specified by obj-*.
  695. Listing all targets in extra-y is required for two purposes:
  696. 1) Enable kbuild to check changes in command lines
  697. - When $(call if_changed,xxx) is used
  698. 2) kbuild knows what files to delete during "make clean"
  699. Example:
  700. #arch/i386/kernel/Makefile
  701. extra-y := head.o init_task.o
  702. In this example extra-y is used to list object files that
  703. shall be built, but shall not be linked as part of built-in.o.
  704. --- 6.6 Commands useful for building a boot image
  705. Kbuild provides a few macros that are useful when building a
  706. boot image.
  707. if_changed
  708. if_changed is the infrastructure used for the following commands.
  709. Usage:
  710. target: source(s) FORCE
  711. $(call if_changed,ld/objcopy/gzip)
  712. When the rule is evaluated it is checked to see if any files
  713. needs an update, or the commandline has changed since last
  714. invocation. The latter will force a rebuild if any options
  715. to the executable have changed.
  716. Any target that utilises if_changed must be listed in $(targets),
  717. otherwise the command line check will fail, and the target will
  718. always be built.
  719. Assignments to $(targets) are without $(obj)/ prefix.
  720. if_changed may be used in conjunction with custom commands as
  721. defined in 6.7 "Custom kbuild commands".
  722. Note: It is a typical mistake to forget the FORCE prerequisite.
  723. Another common pitfall is that whitespace is sometimes
  724. significant; for instance, the below will fail (note the extra space
  725. after the comma):
  726. target: source(s) FORCE
  727. #WRONG!# $(call if_changed, ld/objcopy/gzip)
  728. ld
  729. Link target. Often LDFLAGS_$@ is used to set specific options to ld.
  730. objcopy
  731. Copy binary. Uses OBJCOPYFLAGS usually specified in
  732. arch/$(ARCH)/Makefile.
  733. OBJCOPYFLAGS_$@ may be used to set additional options.
  734. gzip
  735. Compress target. Use maximum compression to compress target.
  736. Example:
  737. #arch/i386/boot/Makefile
  738. LDFLAGS_bootsect := -Ttext 0x0 -s --oformat binary
  739. LDFLAGS_setup := -Ttext 0x0 -s --oformat binary -e begtext
  740. targets += setup setup.o bootsect bootsect.o
  741. $(obj)/setup $(obj)/bootsect: %: %.o FORCE
  742. $(call if_changed,ld)
  743. In this example there are two possible targets, requiring different
  744. options to the linker. the linker options are specified using the
  745. LDFLAGS_$@ syntax - one for each potential target.
  746. $(targets) are assinged all potential targets, herby kbuild knows
  747. the targets and will:
  748. 1) check for commandline changes
  749. 2) delete target during make clean
  750. The ": %: %.o" part of the prerequisite is a shorthand that
  751. free us from listing the setup.o and bootsect.o files.
  752. Note: It is a common mistake to forget the "target :=" assignment,
  753. resulting in the target file being recompiled for no
  754. obvious reason.
  755. --- 6.7 Custom kbuild commands
  756. When kbuild is executing with KBUILD_VERBOSE=0 then only a shorthand
  757. of a command is normally displayed.
  758. To enable this behaviour for custom commands kbuild requires
  759. two variables to be set:
  760. quiet_cmd_<command> - what shall be echoed
  761. cmd_<command> - the command to execute
  762. Example:
  763. #
  764. quiet_cmd_image = BUILD $@
  765. cmd_image = $(obj)/tools/build $(BUILDFLAGS) \
  766. $(obj)/vmlinux.bin > $@
  767. targets += bzImage
  768. $(obj)/bzImage: $(obj)/vmlinux.bin $(obj)/tools/build FORCE
  769. $(call if_changed,image)
  770. @echo 'Kernel: $@ is ready'
  771. When updating the $(obj)/bzImage target the line:
  772. BUILD arch/i386/boot/bzImage
  773. will be displayed with "make KBUILD_VERBOSE=0".
  774. --- 6.8 Preprocessing linker scripts
  775. When the vmlinux image is build the linker script:
  776. arch/$(ARCH)/kernel/vmlinux.lds is used.
  777. The script is a preprocessed variant of the file vmlinux.lds.S
  778. located in the same directory.
  779. kbuild knows .lds file and includes a rule *lds.S -> *lds.
  780. Example:
  781. #arch/i386/kernel/Makefile
  782. always := vmlinux.lds
  783. #Makefile
  784. export CPPFLAGS_vmlinux.lds += -P -C -U$(ARCH)
  785. The assigment to $(always) is used to tell kbuild to build the
  786. target: vmlinux.lds.
  787. The assignment to $(CPPFLAGS_vmlinux.lds) tell kbuild to use the
  788. specified options when building the target vmlinux.lds.
  789. When building the *.lds target kbuild used the variakles:
  790. CPPFLAGS : Set in top-level Makefile
  791. EXTRA_CPPFLAGS : May be set in the kbuild makefile
  792. CPPFLAGS_$(@F) : Target specific flags.
  793. Note that the full filename is used in this
  794. assignment.
  795. The kbuild infrastructure for *lds file are used in several
  796. architecture specific files.
  797. === 7 Kbuild Variables
  798. The top Makefile exports the following variables:
  799. VERSION, PATCHLEVEL, SUBLEVEL, EXTRAVERSION
  800. These variables define the current kernel version. A few arch
  801. Makefiles actually use these values directly; they should use
  802. $(KERNELRELEASE) instead.
  803. $(VERSION), $(PATCHLEVEL), and $(SUBLEVEL) define the basic
  804. three-part version number, such as "2", "4", and "0". These three
  805. values are always numeric.
  806. $(EXTRAVERSION) defines an even tinier sublevel for pre-patches
  807. or additional patches. It is usually some non-numeric string
  808. such as "-pre4", and is often blank.
  809. KERNELRELEASE
  810. $(KERNELRELEASE) is a single string such as "2.4.0-pre4", suitable
  811. for constructing installation directory names or showing in
  812. version strings. Some arch Makefiles use it for this purpose.
  813. ARCH
  814. This variable defines the target architecture, such as "i386",
  815. "arm", or "sparc". Some kbuild Makefiles test $(ARCH) to
  816. determine which files to compile.
  817. By default, the top Makefile sets $(ARCH) to be the same as the
  818. host system architecture. For a cross build, a user may
  819. override the value of $(ARCH) on the command line:
  820. make ARCH=m68k ...
  821. INSTALL_PATH
  822. This variable defines a place for the arch Makefiles to install
  823. the resident kernel image and System.map file.
  824. Use this for architecture specific install targets.
  825. INSTALL_MOD_PATH, MODLIB
  826. $(INSTALL_MOD_PATH) specifies a prefix to $(MODLIB) for module
  827. installation. This variable is not defined in the Makefile but
  828. may be passed in by the user if desired.
  829. $(MODLIB) specifies the directory for module installation.
  830. The top Makefile defines $(MODLIB) to
  831. $(INSTALL_MOD_PATH)/lib/modules/$(KERNELRELEASE). The user may
  832. override this value on the command line if desired.
  833. === 8 Makefile language
  834. The kernel Makefiles are designed to run with GNU Make. The Makefiles
  835. use only the documented features of GNU Make, but they do use many
  836. GNU extensions.
  837. GNU Make supports elementary list-processing functions. The kernel
  838. Makefiles use a novel style of list building and manipulation with few
  839. "if" statements.
  840. GNU Make has two assignment operators, ":=" and "=". ":=" performs
  841. immediate evaluation of the right-hand side and stores an actual string
  842. into the left-hand side. "=" is like a formula definition; it stores the
  843. right-hand side in an unevaluated form and then evaluates this form each
  844. time the left-hand side is used.
  845. There are some cases where "=" is appropriate. Usually, though, ":="
  846. is the right choice.
  847. === 9 Credits
  848. Original version made by Michael Elizabeth Chastain, <mailto:mec@shout.net>
  849. Updates by Kai Germaschewski <kai@tp1.ruhr-uni-bochum.de>
  850. Updates by Sam Ravnborg <sam@ravnborg.org>
  851. === 10 TODO
  852. - Describe how kbuild support shipped files with _shipped.
  853. - Generating offset header files.
  854. - Add more variables to section 7?