omap-dmic.c 12 KB

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  1. /*
  2. * omap-dmic.c -- OMAP ASoC DMIC DAI driver
  3. *
  4. * Copyright (C) 2010 - 2011 Texas Instruments
  5. *
  6. * Author: David Lambert <dlambert@ti.com>
  7. * Misael Lopez Cruz <misael.lopez@ti.com>
  8. * Liam Girdwood <lrg@ti.com>
  9. * Peter Ujfalusi <peter.ujfalusi@ti.com>
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License
  13. * version 2 as published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  23. * 02110-1301 USA
  24. *
  25. */
  26. #include <linux/init.h>
  27. #include <linux/module.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/err.h>
  30. #include <linux/clk.h>
  31. #include <linux/io.h>
  32. #include <linux/slab.h>
  33. #include <linux/pm_runtime.h>
  34. #include <linux/of_device.h>
  35. #include <sound/core.h>
  36. #include <sound/pcm.h>
  37. #include <sound/pcm_params.h>
  38. #include <sound/initval.h>
  39. #include <sound/soc.h>
  40. #include <sound/dmaengine_pcm.h>
  41. #include "omap-dmic.h"
  42. struct omap_dmic {
  43. struct device *dev;
  44. void __iomem *io_base;
  45. struct clk *fclk;
  46. int fclk_freq;
  47. int out_freq;
  48. int clk_div;
  49. int sysclk;
  50. int threshold;
  51. u32 ch_enabled;
  52. bool active;
  53. struct mutex mutex;
  54. struct snd_dmaengine_dai_dma_data dma_data;
  55. unsigned int dma_req;
  56. };
  57. static inline void omap_dmic_write(struct omap_dmic *dmic, u16 reg, u32 val)
  58. {
  59. __raw_writel(val, dmic->io_base + reg);
  60. }
  61. static inline int omap_dmic_read(struct omap_dmic *dmic, u16 reg)
  62. {
  63. return __raw_readl(dmic->io_base + reg);
  64. }
  65. static inline void omap_dmic_start(struct omap_dmic *dmic)
  66. {
  67. u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  68. /* Configure DMA controller */
  69. omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_SET_REG,
  70. OMAP_DMIC_DMA_ENABLE);
  71. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl | dmic->ch_enabled);
  72. }
  73. static inline void omap_dmic_stop(struct omap_dmic *dmic)
  74. {
  75. u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  76. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
  77. ctrl & ~OMAP_DMIC_UP_ENABLE_MASK);
  78. /* Disable DMA request generation */
  79. omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_CLR_REG,
  80. OMAP_DMIC_DMA_ENABLE);
  81. }
  82. static inline int dmic_is_enabled(struct omap_dmic *dmic)
  83. {
  84. return omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG) &
  85. OMAP_DMIC_UP_ENABLE_MASK;
  86. }
  87. static int omap_dmic_dai_startup(struct snd_pcm_substream *substream,
  88. struct snd_soc_dai *dai)
  89. {
  90. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  91. int ret = 0;
  92. mutex_lock(&dmic->mutex);
  93. if (!dai->active)
  94. dmic->active = 1;
  95. else
  96. ret = -EBUSY;
  97. mutex_unlock(&dmic->mutex);
  98. snd_soc_dai_set_dma_data(dai, substream, &dmic->dma_data);
  99. return ret;
  100. }
  101. static void omap_dmic_dai_shutdown(struct snd_pcm_substream *substream,
  102. struct snd_soc_dai *dai)
  103. {
  104. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  105. mutex_lock(&dmic->mutex);
  106. if (!dai->active)
  107. dmic->active = 0;
  108. mutex_unlock(&dmic->mutex);
  109. }
  110. static int omap_dmic_select_divider(struct omap_dmic *dmic, int sample_rate)
  111. {
  112. int divider = -EINVAL;
  113. /*
  114. * 192KHz rate is only supported with 19.2MHz/3.84MHz clock
  115. * configuration.
  116. */
  117. if (sample_rate == 192000) {
  118. if (dmic->fclk_freq == 19200000 && dmic->out_freq == 3840000)
  119. divider = 0x6; /* Divider: 5 (192KHz sampling rate) */
  120. else
  121. dev_err(dmic->dev,
  122. "invalid clock configuration for 192KHz\n");
  123. return divider;
  124. }
  125. switch (dmic->out_freq) {
  126. case 1536000:
  127. if (dmic->fclk_freq != 24576000)
  128. goto div_err;
  129. divider = 0x4; /* Divider: 16 */
  130. break;
  131. case 2400000:
  132. switch (dmic->fclk_freq) {
  133. case 12000000:
  134. divider = 0x5; /* Divider: 5 */
  135. break;
  136. case 19200000:
  137. divider = 0x0; /* Divider: 8 */
  138. break;
  139. case 24000000:
  140. divider = 0x2; /* Divider: 10 */
  141. break;
  142. default:
  143. goto div_err;
  144. }
  145. break;
  146. case 3072000:
  147. if (dmic->fclk_freq != 24576000)
  148. goto div_err;
  149. divider = 0x3; /* Divider: 8 */
  150. break;
  151. case 3840000:
  152. if (dmic->fclk_freq != 19200000)
  153. goto div_err;
  154. divider = 0x1; /* Divider: 5 (96KHz sampling rate) */
  155. break;
  156. default:
  157. dev_err(dmic->dev, "invalid out frequency: %dHz\n",
  158. dmic->out_freq);
  159. break;
  160. }
  161. return divider;
  162. div_err:
  163. dev_err(dmic->dev, "invalid out frequency %dHz for %dHz input\n",
  164. dmic->out_freq, dmic->fclk_freq);
  165. return -EINVAL;
  166. }
  167. static int omap_dmic_dai_hw_params(struct snd_pcm_substream *substream,
  168. struct snd_pcm_hw_params *params,
  169. struct snd_soc_dai *dai)
  170. {
  171. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  172. struct snd_dmaengine_dai_dma_data *dma_data;
  173. int channels;
  174. dmic->clk_div = omap_dmic_select_divider(dmic, params_rate(params));
  175. if (dmic->clk_div < 0) {
  176. dev_err(dmic->dev, "no valid divider for %dHz from %dHz\n",
  177. dmic->out_freq, dmic->fclk_freq);
  178. return -EINVAL;
  179. }
  180. dmic->ch_enabled = 0;
  181. channels = params_channels(params);
  182. switch (channels) {
  183. case 6:
  184. dmic->ch_enabled |= OMAP_DMIC_UP3_ENABLE;
  185. case 4:
  186. dmic->ch_enabled |= OMAP_DMIC_UP2_ENABLE;
  187. case 2:
  188. dmic->ch_enabled |= OMAP_DMIC_UP1_ENABLE;
  189. break;
  190. default:
  191. dev_err(dmic->dev, "invalid number of legacy channels\n");
  192. return -EINVAL;
  193. }
  194. /* packet size is threshold * channels */
  195. dma_data = snd_soc_dai_get_dma_data(dai, substream);
  196. dma_data->maxburst = dmic->threshold * channels;
  197. return 0;
  198. }
  199. static int omap_dmic_dai_prepare(struct snd_pcm_substream *substream,
  200. struct snd_soc_dai *dai)
  201. {
  202. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  203. u32 ctrl;
  204. /* Configure uplink threshold */
  205. omap_dmic_write(dmic, OMAP_DMIC_FIFO_CTRL_REG, dmic->threshold);
  206. ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  207. /* Set dmic out format */
  208. ctrl &= ~(OMAP_DMIC_FORMAT | OMAP_DMIC_POLAR_MASK);
  209. ctrl |= (OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
  210. OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
  211. /* Configure dmic clock divider */
  212. ctrl &= ~OMAP_DMIC_CLK_DIV_MASK;
  213. ctrl |= OMAP_DMIC_CLK_DIV(dmic->clk_div);
  214. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl);
  215. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
  216. ctrl | OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
  217. OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
  218. return 0;
  219. }
  220. static int omap_dmic_dai_trigger(struct snd_pcm_substream *substream,
  221. int cmd, struct snd_soc_dai *dai)
  222. {
  223. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  224. switch (cmd) {
  225. case SNDRV_PCM_TRIGGER_START:
  226. omap_dmic_start(dmic);
  227. break;
  228. case SNDRV_PCM_TRIGGER_STOP:
  229. omap_dmic_stop(dmic);
  230. break;
  231. default:
  232. break;
  233. }
  234. return 0;
  235. }
  236. static int omap_dmic_select_fclk(struct omap_dmic *dmic, int clk_id,
  237. unsigned int freq)
  238. {
  239. struct clk *parent_clk;
  240. char *parent_clk_name;
  241. int ret = 0;
  242. switch (freq) {
  243. case 12000000:
  244. case 19200000:
  245. case 24000000:
  246. case 24576000:
  247. break;
  248. default:
  249. dev_err(dmic->dev, "invalid input frequency: %dHz\n", freq);
  250. dmic->fclk_freq = 0;
  251. return -EINVAL;
  252. }
  253. if (dmic->sysclk == clk_id) {
  254. dmic->fclk_freq = freq;
  255. return 0;
  256. }
  257. /* re-parent not allowed if a stream is ongoing */
  258. if (dmic->active && dmic_is_enabled(dmic)) {
  259. dev_err(dmic->dev, "can't re-parent when DMIC active\n");
  260. return -EBUSY;
  261. }
  262. switch (clk_id) {
  263. case OMAP_DMIC_SYSCLK_PAD_CLKS:
  264. parent_clk_name = "pad_clks_ck";
  265. break;
  266. case OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS:
  267. parent_clk_name = "slimbus_clk";
  268. break;
  269. case OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS:
  270. parent_clk_name = "dmic_sync_mux_ck";
  271. break;
  272. default:
  273. dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id);
  274. return -EINVAL;
  275. }
  276. parent_clk = clk_get(dmic->dev, parent_clk_name);
  277. if (IS_ERR(parent_clk)) {
  278. dev_err(dmic->dev, "can't get %s\n", parent_clk_name);
  279. return -ENODEV;
  280. }
  281. mutex_lock(&dmic->mutex);
  282. if (dmic->active) {
  283. /* disable clock while reparenting */
  284. pm_runtime_put_sync(dmic->dev);
  285. ret = clk_set_parent(dmic->fclk, parent_clk);
  286. pm_runtime_get_sync(dmic->dev);
  287. } else {
  288. ret = clk_set_parent(dmic->fclk, parent_clk);
  289. }
  290. mutex_unlock(&dmic->mutex);
  291. if (ret < 0) {
  292. dev_err(dmic->dev, "re-parent failed\n");
  293. goto err_busy;
  294. }
  295. dmic->sysclk = clk_id;
  296. dmic->fclk_freq = freq;
  297. err_busy:
  298. clk_put(parent_clk);
  299. return ret;
  300. }
  301. static int omap_dmic_select_outclk(struct omap_dmic *dmic, int clk_id,
  302. unsigned int freq)
  303. {
  304. int ret = 0;
  305. if (clk_id != OMAP_DMIC_ABE_DMIC_CLK) {
  306. dev_err(dmic->dev, "output clk_id (%d) not supported\n",
  307. clk_id);
  308. return -EINVAL;
  309. }
  310. switch (freq) {
  311. case 1536000:
  312. case 2400000:
  313. case 3072000:
  314. case 3840000:
  315. dmic->out_freq = freq;
  316. break;
  317. default:
  318. dev_err(dmic->dev, "invalid out frequency: %dHz\n", freq);
  319. dmic->out_freq = 0;
  320. ret = -EINVAL;
  321. }
  322. return ret;
  323. }
  324. static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
  325. unsigned int freq, int dir)
  326. {
  327. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  328. if (dir == SND_SOC_CLOCK_IN)
  329. return omap_dmic_select_fclk(dmic, clk_id, freq);
  330. else if (dir == SND_SOC_CLOCK_OUT)
  331. return omap_dmic_select_outclk(dmic, clk_id, freq);
  332. dev_err(dmic->dev, "invalid clock direction (%d)\n", dir);
  333. return -EINVAL;
  334. }
  335. static const struct snd_soc_dai_ops omap_dmic_dai_ops = {
  336. .startup = omap_dmic_dai_startup,
  337. .shutdown = omap_dmic_dai_shutdown,
  338. .hw_params = omap_dmic_dai_hw_params,
  339. .prepare = omap_dmic_dai_prepare,
  340. .trigger = omap_dmic_dai_trigger,
  341. .set_sysclk = omap_dmic_set_dai_sysclk,
  342. };
  343. static int omap_dmic_probe(struct snd_soc_dai *dai)
  344. {
  345. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  346. pm_runtime_enable(dmic->dev);
  347. /* Disable lines while request is ongoing */
  348. pm_runtime_get_sync(dmic->dev);
  349. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, 0x00);
  350. pm_runtime_put_sync(dmic->dev);
  351. /* Configure DMIC threshold value */
  352. dmic->threshold = OMAP_DMIC_THRES_MAX - 3;
  353. return 0;
  354. }
  355. static int omap_dmic_remove(struct snd_soc_dai *dai)
  356. {
  357. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  358. pm_runtime_disable(dmic->dev);
  359. return 0;
  360. }
  361. static struct snd_soc_dai_driver omap_dmic_dai = {
  362. .name = "omap-dmic",
  363. .probe = omap_dmic_probe,
  364. .remove = omap_dmic_remove,
  365. .capture = {
  366. .channels_min = 2,
  367. .channels_max = 6,
  368. .rates = SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
  369. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  370. .sig_bits = 24,
  371. },
  372. .ops = &omap_dmic_dai_ops,
  373. };
  374. static const struct snd_soc_component_driver omap_dmic_component = {
  375. .name = "omap-dmic",
  376. };
  377. static int asoc_dmic_probe(struct platform_device *pdev)
  378. {
  379. struct omap_dmic *dmic;
  380. struct resource *res;
  381. int ret;
  382. dmic = devm_kzalloc(&pdev->dev, sizeof(struct omap_dmic), GFP_KERNEL);
  383. if (!dmic)
  384. return -ENOMEM;
  385. platform_set_drvdata(pdev, dmic);
  386. dmic->dev = &pdev->dev;
  387. dmic->sysclk = OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS;
  388. mutex_init(&dmic->mutex);
  389. dmic->fclk = clk_get(dmic->dev, "fck");
  390. if (IS_ERR(dmic->fclk)) {
  391. dev_err(dmic->dev, "cant get fck\n");
  392. return -ENODEV;
  393. }
  394. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
  395. if (!res) {
  396. dev_err(dmic->dev, "invalid dma memory resource\n");
  397. ret = -ENODEV;
  398. goto err_put_clk;
  399. }
  400. dmic->dma_data.addr = res->start + OMAP_DMIC_DATA_REG;
  401. res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  402. if (!res) {
  403. dev_err(dmic->dev, "invalid dma resource\n");
  404. ret = -ENODEV;
  405. goto err_put_clk;
  406. }
  407. dmic->dma_req = res->start;
  408. dmic->dma_data.filter_data = &dmic->dma_req;
  409. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
  410. if (!res) {
  411. dev_err(dmic->dev, "invalid memory resource\n");
  412. ret = -ENODEV;
  413. goto err_put_clk;
  414. }
  415. dmic->io_base = devm_ioremap_resource(&pdev->dev, res);
  416. if (IS_ERR(dmic->io_base))
  417. return PTR_ERR(dmic->io_base);
  418. ret = snd_soc_register_component(&pdev->dev, &omap_dmic_component,
  419. &omap_dmic_dai, 1);
  420. if (ret)
  421. goto err_put_clk;
  422. return 0;
  423. err_put_clk:
  424. clk_put(dmic->fclk);
  425. return ret;
  426. }
  427. static int asoc_dmic_remove(struct platform_device *pdev)
  428. {
  429. struct omap_dmic *dmic = platform_get_drvdata(pdev);
  430. snd_soc_unregister_component(&pdev->dev);
  431. clk_put(dmic->fclk);
  432. return 0;
  433. }
  434. static const struct of_device_id omap_dmic_of_match[] = {
  435. { .compatible = "ti,omap4-dmic", },
  436. { }
  437. };
  438. MODULE_DEVICE_TABLE(of, omap_dmic_of_match);
  439. static struct platform_driver asoc_dmic_driver = {
  440. .driver = {
  441. .name = "omap-dmic",
  442. .owner = THIS_MODULE,
  443. .of_match_table = omap_dmic_of_match,
  444. },
  445. .probe = asoc_dmic_probe,
  446. .remove = asoc_dmic_remove,
  447. };
  448. module_platform_driver(asoc_dmic_driver);
  449. MODULE_ALIAS("platform:omap-dmic");
  450. MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
  451. MODULE_DESCRIPTION("OMAP DMIC ASoC Interface");
  452. MODULE_LICENSE("GPL");