omap3isp.h 4.3 KB

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  1. /*
  2. * omap3isp.h
  3. *
  4. * TI OMAP3 ISP - Platform data
  5. *
  6. * Copyright (C) 2011 Nokia Corporation
  7. *
  8. * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  9. * Sakari Ailus <sakari.ailus@iki.fi>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  23. * 02110-1301 USA
  24. */
  25. #ifndef __MEDIA_OMAP3ISP_H__
  26. #define __MEDIA_OMAP3ISP_H__
  27. struct i2c_board_info;
  28. struct isp_device;
  29. enum isp_interface_type {
  30. ISP_INTERFACE_PARALLEL,
  31. ISP_INTERFACE_CSI2A_PHY2,
  32. ISP_INTERFACE_CCP2B_PHY1,
  33. ISP_INTERFACE_CCP2B_PHY2,
  34. ISP_INTERFACE_CSI2C_PHY1,
  35. };
  36. enum {
  37. ISP_LANE_SHIFT_0 = 0,
  38. ISP_LANE_SHIFT_2 = 1,
  39. ISP_LANE_SHIFT_4 = 2,
  40. ISP_LANE_SHIFT_6 = 3,
  41. };
  42. /**
  43. * struct isp_parallel_platform_data - Parallel interface platform data
  44. * @data_lane_shift: Data lane shifter
  45. * ISP_LANE_SHIFT_0 - CAMEXT[13:0] -> CAM[13:0]
  46. * ISP_LANE_SHIFT_2 - CAMEXT[13:2] -> CAM[11:0]
  47. * ISP_LANE_SHIFT_4 - CAMEXT[13:4] -> CAM[9:0]
  48. * ISP_LANE_SHIFT_6 - CAMEXT[13:6] -> CAM[7:0]
  49. * @clk_pol: Pixel clock polarity
  50. * 0 - Sample on rising edge, 1 - Sample on falling edge
  51. * @hs_pol: Horizontal synchronization polarity
  52. * 0 - Active high, 1 - Active low
  53. * @vs_pol: Vertical synchronization polarity
  54. * 0 - Active high, 1 - Active low
  55. * @data_pol: Data polarity
  56. * 0 - Normal, 1 - One's complement
  57. */
  58. struct isp_parallel_platform_data {
  59. unsigned int data_lane_shift:2;
  60. unsigned int clk_pol:1;
  61. unsigned int hs_pol:1;
  62. unsigned int vs_pol:1;
  63. unsigned int data_pol:1;
  64. };
  65. enum {
  66. ISP_CCP2_PHY_DATA_CLOCK = 0,
  67. ISP_CCP2_PHY_DATA_STROBE = 1,
  68. };
  69. enum {
  70. ISP_CCP2_MODE_MIPI = 0,
  71. ISP_CCP2_MODE_CCP2 = 1,
  72. };
  73. /**
  74. * struct isp_csiphy_lane: CCP2/CSI2 lane position and polarity
  75. * @pos: position of the lane
  76. * @pol: polarity of the lane
  77. */
  78. struct isp_csiphy_lane {
  79. u8 pos;
  80. u8 pol;
  81. };
  82. #define ISP_CSIPHY1_NUM_DATA_LANES 1
  83. #define ISP_CSIPHY2_NUM_DATA_LANES 2
  84. /**
  85. * struct isp_csiphy_lanes_cfg - CCP2/CSI2 lane configuration
  86. * @data: Configuration of one or two data lanes
  87. * @clk: Clock lane configuration
  88. */
  89. struct isp_csiphy_lanes_cfg {
  90. struct isp_csiphy_lane data[ISP_CSIPHY2_NUM_DATA_LANES];
  91. struct isp_csiphy_lane clk;
  92. };
  93. /**
  94. * struct isp_ccp2_platform_data - CCP2 interface platform data
  95. * @strobe_clk_pol: Strobe/clock polarity
  96. * 0 - Non Inverted, 1 - Inverted
  97. * @crc: Enable the cyclic redundancy check
  98. * @ccp2_mode: Enable CCP2 compatibility mode
  99. * ISP_CCP2_MODE_MIPI - MIPI-CSI1 mode
  100. * ISP_CCP2_MODE_CCP2 - CCP2 mode
  101. * @phy_layer: Physical layer selection
  102. * ISP_CCP2_PHY_DATA_CLOCK - Data/clock physical layer
  103. * ISP_CCP2_PHY_DATA_STROBE - Data/strobe physical layer
  104. * @vpclk_div: Video port output clock control
  105. */
  106. struct isp_ccp2_platform_data {
  107. unsigned int strobe_clk_pol:1;
  108. unsigned int crc:1;
  109. unsigned int ccp2_mode:1;
  110. unsigned int phy_layer:1;
  111. unsigned int vpclk_div:2;
  112. struct isp_csiphy_lanes_cfg lanecfg;
  113. };
  114. /**
  115. * struct isp_csi2_platform_data - CSI2 interface platform data
  116. * @crc: Enable the cyclic redundancy check
  117. * @vpclk_div: Video port output clock control
  118. */
  119. struct isp_csi2_platform_data {
  120. unsigned crc:1;
  121. unsigned vpclk_div:2;
  122. struct isp_csiphy_lanes_cfg lanecfg;
  123. };
  124. struct isp_subdev_i2c_board_info {
  125. struct i2c_board_info *board_info;
  126. int i2c_adapter_id;
  127. };
  128. struct isp_v4l2_subdevs_group {
  129. struct isp_subdev_i2c_board_info *subdevs;
  130. enum isp_interface_type interface;
  131. union {
  132. struct isp_parallel_platform_data parallel;
  133. struct isp_ccp2_platform_data ccp2;
  134. struct isp_csi2_platform_data csi2;
  135. } bus; /* gcc < 4.6.0 chokes on anonymous union initializers */
  136. };
  137. struct isp_platform_xclk {
  138. const char *dev_id;
  139. const char *con_id;
  140. };
  141. struct isp_platform_data {
  142. struct isp_platform_xclk xclks[2];
  143. struct isp_v4l2_subdevs_group *subdevs;
  144. void (*set_constraints)(struct isp_device *isp, bool enable);
  145. };
  146. #endif /* __MEDIA_OMAP3ISP_H__ */