events.c 44 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907
  1. /*
  2. * Xen event channels
  3. *
  4. * Xen models interrupts with abstract event channels. Because each
  5. * domain gets 1024 event channels, but NR_IRQ is not that large, we
  6. * must dynamically map irqs<->event channels. The event channels
  7. * interface with the rest of the kernel by defining a xen interrupt
  8. * chip. When an event is received, it is mapped to an irq and sent
  9. * through the normal interrupt processing path.
  10. *
  11. * There are four kinds of events which can be mapped to an event
  12. * channel:
  13. *
  14. * 1. Inter-domain notifications. This includes all the virtual
  15. * device events, since they're driven by front-ends in another domain
  16. * (typically dom0).
  17. * 2. VIRQs, typically used for timers. These are per-cpu events.
  18. * 3. IPIs.
  19. * 4. PIRQs - Hardware interrupts.
  20. *
  21. * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
  22. */
  23. #include <linux/linkage.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/irq.h>
  26. #include <linux/module.h>
  27. #include <linux/string.h>
  28. #include <linux/bootmem.h>
  29. #include <linux/slab.h>
  30. #include <linux/irqnr.h>
  31. #include <linux/pci.h>
  32. #ifdef CONFIG_X86
  33. #include <asm/desc.h>
  34. #include <asm/ptrace.h>
  35. #include <asm/irq.h>
  36. #include <asm/idle.h>
  37. #include <asm/io_apic.h>
  38. #include <asm/xen/page.h>
  39. #include <asm/xen/pci.h>
  40. #endif
  41. #include <asm/sync_bitops.h>
  42. #include <asm/xen/hypercall.h>
  43. #include <asm/xen/hypervisor.h>
  44. #include <xen/xen.h>
  45. #include <xen/hvm.h>
  46. #include <xen/xen-ops.h>
  47. #include <xen/events.h>
  48. #include <xen/interface/xen.h>
  49. #include <xen/interface/event_channel.h>
  50. #include <xen/interface/hvm/hvm_op.h>
  51. #include <xen/interface/hvm/params.h>
  52. #include <xen/interface/physdev.h>
  53. #include <xen/interface/sched.h>
  54. #include <asm/hw_irq.h>
  55. /*
  56. * This lock protects updates to the following mapping and reference-count
  57. * arrays. The lock does not need to be acquired to read the mapping tables.
  58. */
  59. static DEFINE_MUTEX(irq_mapping_update_lock);
  60. static LIST_HEAD(xen_irq_list_head);
  61. /* IRQ <-> VIRQ mapping. */
  62. static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
  63. /* IRQ <-> IPI mapping */
  64. static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
  65. /* Interrupt types. */
  66. enum xen_irq_type {
  67. IRQT_UNBOUND = 0,
  68. IRQT_PIRQ,
  69. IRQT_VIRQ,
  70. IRQT_IPI,
  71. IRQT_EVTCHN
  72. };
  73. /*
  74. * Packed IRQ information:
  75. * type - enum xen_irq_type
  76. * event channel - irq->event channel mapping
  77. * cpu - cpu this event channel is bound to
  78. * index - type-specific information:
  79. * PIRQ - physical IRQ, GSI, flags, and owner domain
  80. * VIRQ - virq number
  81. * IPI - IPI vector
  82. * EVTCHN -
  83. */
  84. struct irq_info {
  85. struct list_head list;
  86. int refcnt;
  87. enum xen_irq_type type; /* type */
  88. unsigned irq;
  89. unsigned short evtchn; /* event channel */
  90. unsigned short cpu; /* cpu bound */
  91. union {
  92. unsigned short virq;
  93. enum ipi_vector ipi;
  94. struct {
  95. unsigned short pirq;
  96. unsigned short gsi;
  97. unsigned char flags;
  98. uint16_t domid;
  99. } pirq;
  100. } u;
  101. };
  102. #define PIRQ_NEEDS_EOI (1 << 0)
  103. #define PIRQ_SHAREABLE (1 << 1)
  104. static int *evtchn_to_irq;
  105. #ifdef CONFIG_X86
  106. static unsigned long *pirq_eoi_map;
  107. #endif
  108. static bool (*pirq_needs_eoi)(unsigned irq);
  109. /*
  110. * Note sizeof(xen_ulong_t) can be more than sizeof(unsigned long). Be
  111. * careful to only use bitops which allow for this (e.g
  112. * test_bit/find_first_bit and friends but not __ffs) and to pass
  113. * BITS_PER_EVTCHN_WORD as the bitmask length.
  114. */
  115. #define BITS_PER_EVTCHN_WORD (sizeof(xen_ulong_t)*8)
  116. /*
  117. * Make a bitmask (i.e. unsigned long *) of a xen_ulong_t
  118. * array. Primarily to avoid long lines (hence the terse name).
  119. */
  120. #define BM(x) (unsigned long *)(x)
  121. /* Find the first set bit in a evtchn mask */
  122. #define EVTCHN_FIRST_BIT(w) find_first_bit(BM(&(w)), BITS_PER_EVTCHN_WORD)
  123. static DEFINE_PER_CPU(xen_ulong_t [NR_EVENT_CHANNELS/BITS_PER_EVTCHN_WORD],
  124. cpu_evtchn_mask);
  125. /* Xen will never allocate port zero for any purpose. */
  126. #define VALID_EVTCHN(chn) ((chn) != 0)
  127. static struct irq_chip xen_dynamic_chip;
  128. static struct irq_chip xen_percpu_chip;
  129. static struct irq_chip xen_pirq_chip;
  130. static void enable_dynirq(struct irq_data *data);
  131. static void disable_dynirq(struct irq_data *data);
  132. /* Get info for IRQ */
  133. static struct irq_info *info_for_irq(unsigned irq)
  134. {
  135. return irq_get_handler_data(irq);
  136. }
  137. /* Constructors for packed IRQ information. */
  138. static void xen_irq_info_common_init(struct irq_info *info,
  139. unsigned irq,
  140. enum xen_irq_type type,
  141. unsigned short evtchn,
  142. unsigned short cpu)
  143. {
  144. BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
  145. info->type = type;
  146. info->irq = irq;
  147. info->evtchn = evtchn;
  148. info->cpu = cpu;
  149. evtchn_to_irq[evtchn] = irq;
  150. irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN);
  151. }
  152. static void xen_irq_info_evtchn_init(unsigned irq,
  153. unsigned short evtchn)
  154. {
  155. struct irq_info *info = info_for_irq(irq);
  156. xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
  157. }
  158. static void xen_irq_info_ipi_init(unsigned cpu,
  159. unsigned irq,
  160. unsigned short evtchn,
  161. enum ipi_vector ipi)
  162. {
  163. struct irq_info *info = info_for_irq(irq);
  164. xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
  165. info->u.ipi = ipi;
  166. per_cpu(ipi_to_irq, cpu)[ipi] = irq;
  167. }
  168. static void xen_irq_info_virq_init(unsigned cpu,
  169. unsigned irq,
  170. unsigned short evtchn,
  171. unsigned short virq)
  172. {
  173. struct irq_info *info = info_for_irq(irq);
  174. xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
  175. info->u.virq = virq;
  176. per_cpu(virq_to_irq, cpu)[virq] = irq;
  177. }
  178. static void xen_irq_info_pirq_init(unsigned irq,
  179. unsigned short evtchn,
  180. unsigned short pirq,
  181. unsigned short gsi,
  182. uint16_t domid,
  183. unsigned char flags)
  184. {
  185. struct irq_info *info = info_for_irq(irq);
  186. xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
  187. info->u.pirq.pirq = pirq;
  188. info->u.pirq.gsi = gsi;
  189. info->u.pirq.domid = domid;
  190. info->u.pirq.flags = flags;
  191. }
  192. /*
  193. * Accessors for packed IRQ information.
  194. */
  195. static unsigned int evtchn_from_irq(unsigned irq)
  196. {
  197. if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
  198. return 0;
  199. return info_for_irq(irq)->evtchn;
  200. }
  201. unsigned irq_from_evtchn(unsigned int evtchn)
  202. {
  203. return evtchn_to_irq[evtchn];
  204. }
  205. EXPORT_SYMBOL_GPL(irq_from_evtchn);
  206. static enum ipi_vector ipi_from_irq(unsigned irq)
  207. {
  208. struct irq_info *info = info_for_irq(irq);
  209. BUG_ON(info == NULL);
  210. BUG_ON(info->type != IRQT_IPI);
  211. return info->u.ipi;
  212. }
  213. static unsigned virq_from_irq(unsigned irq)
  214. {
  215. struct irq_info *info = info_for_irq(irq);
  216. BUG_ON(info == NULL);
  217. BUG_ON(info->type != IRQT_VIRQ);
  218. return info->u.virq;
  219. }
  220. static unsigned pirq_from_irq(unsigned irq)
  221. {
  222. struct irq_info *info = info_for_irq(irq);
  223. BUG_ON(info == NULL);
  224. BUG_ON(info->type != IRQT_PIRQ);
  225. return info->u.pirq.pirq;
  226. }
  227. static enum xen_irq_type type_from_irq(unsigned irq)
  228. {
  229. return info_for_irq(irq)->type;
  230. }
  231. static unsigned cpu_from_irq(unsigned irq)
  232. {
  233. return info_for_irq(irq)->cpu;
  234. }
  235. static unsigned int cpu_from_evtchn(unsigned int evtchn)
  236. {
  237. int irq = evtchn_to_irq[evtchn];
  238. unsigned ret = 0;
  239. if (irq != -1)
  240. ret = cpu_from_irq(irq);
  241. return ret;
  242. }
  243. #ifdef CONFIG_X86
  244. static bool pirq_check_eoi_map(unsigned irq)
  245. {
  246. return test_bit(pirq_from_irq(irq), pirq_eoi_map);
  247. }
  248. #endif
  249. static bool pirq_needs_eoi_flag(unsigned irq)
  250. {
  251. struct irq_info *info = info_for_irq(irq);
  252. BUG_ON(info->type != IRQT_PIRQ);
  253. return info->u.pirq.flags & PIRQ_NEEDS_EOI;
  254. }
  255. static inline xen_ulong_t active_evtchns(unsigned int cpu,
  256. struct shared_info *sh,
  257. unsigned int idx)
  258. {
  259. return sh->evtchn_pending[idx] &
  260. per_cpu(cpu_evtchn_mask, cpu)[idx] &
  261. ~sh->evtchn_mask[idx];
  262. }
  263. static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
  264. {
  265. int irq = evtchn_to_irq[chn];
  266. BUG_ON(irq == -1);
  267. #ifdef CONFIG_SMP
  268. cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
  269. #endif
  270. clear_bit(chn, BM(per_cpu(cpu_evtchn_mask, cpu_from_irq(irq))));
  271. set_bit(chn, BM(per_cpu(cpu_evtchn_mask, cpu)));
  272. info_for_irq(irq)->cpu = cpu;
  273. }
  274. static void init_evtchn_cpu_bindings(void)
  275. {
  276. int i;
  277. #ifdef CONFIG_SMP
  278. struct irq_info *info;
  279. /* By default all event channels notify CPU#0. */
  280. list_for_each_entry(info, &xen_irq_list_head, list) {
  281. struct irq_desc *desc = irq_to_desc(info->irq);
  282. cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
  283. }
  284. #endif
  285. for_each_possible_cpu(i)
  286. memset(per_cpu(cpu_evtchn_mask, i),
  287. (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
  288. }
  289. static inline void clear_evtchn(int port)
  290. {
  291. struct shared_info *s = HYPERVISOR_shared_info;
  292. sync_clear_bit(port, BM(&s->evtchn_pending[0]));
  293. }
  294. static inline void set_evtchn(int port)
  295. {
  296. struct shared_info *s = HYPERVISOR_shared_info;
  297. sync_set_bit(port, BM(&s->evtchn_pending[0]));
  298. }
  299. static inline int test_evtchn(int port)
  300. {
  301. struct shared_info *s = HYPERVISOR_shared_info;
  302. return sync_test_bit(port, BM(&s->evtchn_pending[0]));
  303. }
  304. /**
  305. * notify_remote_via_irq - send event to remote end of event channel via irq
  306. * @irq: irq of event channel to send event to
  307. *
  308. * Unlike notify_remote_via_evtchn(), this is safe to use across
  309. * save/restore. Notifications on a broken connection are silently
  310. * dropped.
  311. */
  312. void notify_remote_via_irq(int irq)
  313. {
  314. int evtchn = evtchn_from_irq(irq);
  315. if (VALID_EVTCHN(evtchn))
  316. notify_remote_via_evtchn(evtchn);
  317. }
  318. EXPORT_SYMBOL_GPL(notify_remote_via_irq);
  319. static void mask_evtchn(int port)
  320. {
  321. struct shared_info *s = HYPERVISOR_shared_info;
  322. sync_set_bit(port, BM(&s->evtchn_mask[0]));
  323. }
  324. static void unmask_evtchn(int port)
  325. {
  326. struct shared_info *s = HYPERVISOR_shared_info;
  327. unsigned int cpu = get_cpu();
  328. int do_hypercall = 0, evtchn_pending = 0;
  329. BUG_ON(!irqs_disabled());
  330. if (unlikely((cpu != cpu_from_evtchn(port))))
  331. do_hypercall = 1;
  332. else {
  333. /*
  334. * Need to clear the mask before checking pending to
  335. * avoid a race with an event becoming pending.
  336. *
  337. * EVTCHNOP_unmask will only trigger an upcall if the
  338. * mask bit was set, so if a hypercall is needed
  339. * remask the event.
  340. */
  341. sync_clear_bit(port, BM(&s->evtchn_mask[0]));
  342. evtchn_pending = sync_test_bit(port, BM(&s->evtchn_pending[0]));
  343. if (unlikely(evtchn_pending && xen_hvm_domain())) {
  344. sync_set_bit(port, BM(&s->evtchn_mask[0]));
  345. do_hypercall = 1;
  346. }
  347. }
  348. /* Slow path (hypercall) if this is a non-local port or if this is
  349. * an hvm domain and an event is pending (hvm domains don't have
  350. * their own implementation of irq_enable). */
  351. if (do_hypercall) {
  352. struct evtchn_unmask unmask = { .port = port };
  353. (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
  354. } else {
  355. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  356. /*
  357. * The following is basically the equivalent of
  358. * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
  359. * the interrupt edge' if the channel is masked.
  360. */
  361. if (evtchn_pending &&
  362. !sync_test_and_set_bit(port / BITS_PER_EVTCHN_WORD,
  363. BM(&vcpu_info->evtchn_pending_sel)))
  364. vcpu_info->evtchn_upcall_pending = 1;
  365. }
  366. put_cpu();
  367. }
  368. static void xen_irq_init(unsigned irq)
  369. {
  370. struct irq_info *info;
  371. #ifdef CONFIG_SMP
  372. struct irq_desc *desc = irq_to_desc(irq);
  373. /* By default all event channels notify CPU#0. */
  374. cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
  375. #endif
  376. info = kzalloc(sizeof(*info), GFP_KERNEL);
  377. if (info == NULL)
  378. panic("Unable to allocate metadata for IRQ%d\n", irq);
  379. info->type = IRQT_UNBOUND;
  380. info->refcnt = -1;
  381. irq_set_handler_data(irq, info);
  382. list_add_tail(&info->list, &xen_irq_list_head);
  383. }
  384. static int __must_check xen_allocate_irq_dynamic(void)
  385. {
  386. int first = 0;
  387. int irq;
  388. #ifdef CONFIG_X86_IO_APIC
  389. /*
  390. * For an HVM guest or domain 0 which see "real" (emulated or
  391. * actual respectively) GSIs we allocate dynamic IRQs
  392. * e.g. those corresponding to event channels or MSIs
  393. * etc. from the range above those "real" GSIs to avoid
  394. * collisions.
  395. */
  396. if (xen_initial_domain() || xen_hvm_domain())
  397. first = get_nr_irqs_gsi();
  398. #endif
  399. irq = irq_alloc_desc_from(first, -1);
  400. if (irq >= 0)
  401. xen_irq_init(irq);
  402. return irq;
  403. }
  404. static int __must_check xen_allocate_irq_gsi(unsigned gsi)
  405. {
  406. int irq;
  407. /*
  408. * A PV guest has no concept of a GSI (since it has no ACPI
  409. * nor access to/knowledge of the physical APICs). Therefore
  410. * all IRQs are dynamically allocated from the entire IRQ
  411. * space.
  412. */
  413. if (xen_pv_domain() && !xen_initial_domain())
  414. return xen_allocate_irq_dynamic();
  415. /* Legacy IRQ descriptors are already allocated by the arch. */
  416. if (gsi < NR_IRQS_LEGACY)
  417. irq = gsi;
  418. else
  419. irq = irq_alloc_desc_at(gsi, -1);
  420. xen_irq_init(irq);
  421. return irq;
  422. }
  423. static void xen_free_irq(unsigned irq)
  424. {
  425. struct irq_info *info = irq_get_handler_data(irq);
  426. if (WARN_ON(!info))
  427. return;
  428. list_del(&info->list);
  429. irq_set_handler_data(irq, NULL);
  430. WARN_ON(info->refcnt > 0);
  431. kfree(info);
  432. /* Legacy IRQ descriptors are managed by the arch. */
  433. if (irq < NR_IRQS_LEGACY)
  434. return;
  435. irq_free_desc(irq);
  436. }
  437. static void pirq_query_unmask(int irq)
  438. {
  439. struct physdev_irq_status_query irq_status;
  440. struct irq_info *info = info_for_irq(irq);
  441. BUG_ON(info->type != IRQT_PIRQ);
  442. irq_status.irq = pirq_from_irq(irq);
  443. if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
  444. irq_status.flags = 0;
  445. info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
  446. if (irq_status.flags & XENIRQSTAT_needs_eoi)
  447. info->u.pirq.flags |= PIRQ_NEEDS_EOI;
  448. }
  449. static bool probing_irq(int irq)
  450. {
  451. struct irq_desc *desc = irq_to_desc(irq);
  452. return desc && desc->action == NULL;
  453. }
  454. static void eoi_pirq(struct irq_data *data)
  455. {
  456. int evtchn = evtchn_from_irq(data->irq);
  457. struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
  458. int rc = 0;
  459. irq_move_irq(data);
  460. if (VALID_EVTCHN(evtchn))
  461. clear_evtchn(evtchn);
  462. if (pirq_needs_eoi(data->irq)) {
  463. rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
  464. WARN_ON(rc);
  465. }
  466. }
  467. static void mask_ack_pirq(struct irq_data *data)
  468. {
  469. disable_dynirq(data);
  470. eoi_pirq(data);
  471. }
  472. static unsigned int __startup_pirq(unsigned int irq)
  473. {
  474. struct evtchn_bind_pirq bind_pirq;
  475. struct irq_info *info = info_for_irq(irq);
  476. int evtchn = evtchn_from_irq(irq);
  477. int rc;
  478. BUG_ON(info->type != IRQT_PIRQ);
  479. if (VALID_EVTCHN(evtchn))
  480. goto out;
  481. bind_pirq.pirq = pirq_from_irq(irq);
  482. /* NB. We are happy to share unless we are probing. */
  483. bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
  484. BIND_PIRQ__WILL_SHARE : 0;
  485. rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
  486. if (rc != 0) {
  487. if (!probing_irq(irq))
  488. printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
  489. irq);
  490. return 0;
  491. }
  492. evtchn = bind_pirq.port;
  493. pirq_query_unmask(irq);
  494. evtchn_to_irq[evtchn] = irq;
  495. bind_evtchn_to_cpu(evtchn, 0);
  496. info->evtchn = evtchn;
  497. out:
  498. unmask_evtchn(evtchn);
  499. eoi_pirq(irq_get_irq_data(irq));
  500. return 0;
  501. }
  502. static unsigned int startup_pirq(struct irq_data *data)
  503. {
  504. return __startup_pirq(data->irq);
  505. }
  506. static void shutdown_pirq(struct irq_data *data)
  507. {
  508. struct evtchn_close close;
  509. unsigned int irq = data->irq;
  510. struct irq_info *info = info_for_irq(irq);
  511. int evtchn = evtchn_from_irq(irq);
  512. BUG_ON(info->type != IRQT_PIRQ);
  513. if (!VALID_EVTCHN(evtchn))
  514. return;
  515. mask_evtchn(evtchn);
  516. close.port = evtchn;
  517. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  518. BUG();
  519. bind_evtchn_to_cpu(evtchn, 0);
  520. evtchn_to_irq[evtchn] = -1;
  521. info->evtchn = 0;
  522. }
  523. static void enable_pirq(struct irq_data *data)
  524. {
  525. startup_pirq(data);
  526. }
  527. static void disable_pirq(struct irq_data *data)
  528. {
  529. disable_dynirq(data);
  530. }
  531. int xen_irq_from_gsi(unsigned gsi)
  532. {
  533. struct irq_info *info;
  534. list_for_each_entry(info, &xen_irq_list_head, list) {
  535. if (info->type != IRQT_PIRQ)
  536. continue;
  537. if (info->u.pirq.gsi == gsi)
  538. return info->irq;
  539. }
  540. return -1;
  541. }
  542. EXPORT_SYMBOL_GPL(xen_irq_from_gsi);
  543. /*
  544. * Do not make any assumptions regarding the relationship between the
  545. * IRQ number returned here and the Xen pirq argument.
  546. *
  547. * Note: We don't assign an event channel until the irq actually started
  548. * up. Return an existing irq if we've already got one for the gsi.
  549. *
  550. * Shareable implies level triggered, not shareable implies edge
  551. * triggered here.
  552. */
  553. int xen_bind_pirq_gsi_to_irq(unsigned gsi,
  554. unsigned pirq, int shareable, char *name)
  555. {
  556. int irq = -1;
  557. struct physdev_irq irq_op;
  558. mutex_lock(&irq_mapping_update_lock);
  559. irq = xen_irq_from_gsi(gsi);
  560. if (irq != -1) {
  561. printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
  562. irq, gsi);
  563. goto out;
  564. }
  565. irq = xen_allocate_irq_gsi(gsi);
  566. if (irq < 0)
  567. goto out;
  568. irq_op.irq = irq;
  569. irq_op.vector = 0;
  570. /* Only the privileged domain can do this. For non-priv, the pcifront
  571. * driver provides a PCI bus that does the call to do exactly
  572. * this in the priv domain. */
  573. if (xen_initial_domain() &&
  574. HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
  575. xen_free_irq(irq);
  576. irq = -ENOSPC;
  577. goto out;
  578. }
  579. xen_irq_info_pirq_init(irq, 0, pirq, gsi, DOMID_SELF,
  580. shareable ? PIRQ_SHAREABLE : 0);
  581. pirq_query_unmask(irq);
  582. /* We try to use the handler with the appropriate semantic for the
  583. * type of interrupt: if the interrupt is an edge triggered
  584. * interrupt we use handle_edge_irq.
  585. *
  586. * On the other hand if the interrupt is level triggered we use
  587. * handle_fasteoi_irq like the native code does for this kind of
  588. * interrupts.
  589. *
  590. * Depending on the Xen version, pirq_needs_eoi might return true
  591. * not only for level triggered interrupts but for edge triggered
  592. * interrupts too. In any case Xen always honors the eoi mechanism,
  593. * not injecting any more pirqs of the same kind if the first one
  594. * hasn't received an eoi yet. Therefore using the fasteoi handler
  595. * is the right choice either way.
  596. */
  597. if (shareable)
  598. irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
  599. handle_fasteoi_irq, name);
  600. else
  601. irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
  602. handle_edge_irq, name);
  603. out:
  604. mutex_unlock(&irq_mapping_update_lock);
  605. return irq;
  606. }
  607. #ifdef CONFIG_PCI_MSI
  608. int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
  609. {
  610. int rc;
  611. struct physdev_get_free_pirq op_get_free_pirq;
  612. op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
  613. rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
  614. WARN_ONCE(rc == -ENOSYS,
  615. "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
  616. return rc ? -1 : op_get_free_pirq.pirq;
  617. }
  618. int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
  619. int pirq, const char *name, domid_t domid)
  620. {
  621. int irq, ret;
  622. mutex_lock(&irq_mapping_update_lock);
  623. irq = xen_allocate_irq_dynamic();
  624. if (irq < 0)
  625. goto out;
  626. irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq,
  627. name);
  628. xen_irq_info_pirq_init(irq, 0, pirq, 0, domid, 0);
  629. ret = irq_set_msi_desc(irq, msidesc);
  630. if (ret < 0)
  631. goto error_irq;
  632. out:
  633. mutex_unlock(&irq_mapping_update_lock);
  634. return irq;
  635. error_irq:
  636. mutex_unlock(&irq_mapping_update_lock);
  637. xen_free_irq(irq);
  638. return ret;
  639. }
  640. #endif
  641. int xen_destroy_irq(int irq)
  642. {
  643. struct irq_desc *desc;
  644. struct physdev_unmap_pirq unmap_irq;
  645. struct irq_info *info = info_for_irq(irq);
  646. int rc = -ENOENT;
  647. mutex_lock(&irq_mapping_update_lock);
  648. desc = irq_to_desc(irq);
  649. if (!desc)
  650. goto out;
  651. if (xen_initial_domain()) {
  652. unmap_irq.pirq = info->u.pirq.pirq;
  653. unmap_irq.domid = info->u.pirq.domid;
  654. rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
  655. /* If another domain quits without making the pci_disable_msix
  656. * call, the Xen hypervisor takes care of freeing the PIRQs
  657. * (free_domain_pirqs).
  658. */
  659. if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
  660. printk(KERN_INFO "domain %d does not have %d anymore\n",
  661. info->u.pirq.domid, info->u.pirq.pirq);
  662. else if (rc) {
  663. printk(KERN_WARNING "unmap irq failed %d\n", rc);
  664. goto out;
  665. }
  666. }
  667. xen_free_irq(irq);
  668. out:
  669. mutex_unlock(&irq_mapping_update_lock);
  670. return rc;
  671. }
  672. int xen_irq_from_pirq(unsigned pirq)
  673. {
  674. int irq;
  675. struct irq_info *info;
  676. mutex_lock(&irq_mapping_update_lock);
  677. list_for_each_entry(info, &xen_irq_list_head, list) {
  678. if (info->type != IRQT_PIRQ)
  679. continue;
  680. irq = info->irq;
  681. if (info->u.pirq.pirq == pirq)
  682. goto out;
  683. }
  684. irq = -1;
  685. out:
  686. mutex_unlock(&irq_mapping_update_lock);
  687. return irq;
  688. }
  689. int xen_pirq_from_irq(unsigned irq)
  690. {
  691. return pirq_from_irq(irq);
  692. }
  693. EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
  694. int bind_evtchn_to_irq(unsigned int evtchn)
  695. {
  696. int irq;
  697. mutex_lock(&irq_mapping_update_lock);
  698. irq = evtchn_to_irq[evtchn];
  699. if (irq == -1) {
  700. irq = xen_allocate_irq_dynamic();
  701. if (irq < 0)
  702. goto out;
  703. irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
  704. handle_edge_irq, "event");
  705. xen_irq_info_evtchn_init(irq, evtchn);
  706. } else {
  707. struct irq_info *info = info_for_irq(irq);
  708. WARN_ON(info == NULL || info->type != IRQT_EVTCHN);
  709. }
  710. out:
  711. mutex_unlock(&irq_mapping_update_lock);
  712. return irq;
  713. }
  714. EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
  715. static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
  716. {
  717. struct evtchn_bind_ipi bind_ipi;
  718. int evtchn, irq;
  719. mutex_lock(&irq_mapping_update_lock);
  720. irq = per_cpu(ipi_to_irq, cpu)[ipi];
  721. if (irq == -1) {
  722. irq = xen_allocate_irq_dynamic();
  723. if (irq < 0)
  724. goto out;
  725. irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
  726. handle_percpu_irq, "ipi");
  727. bind_ipi.vcpu = cpu;
  728. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  729. &bind_ipi) != 0)
  730. BUG();
  731. evtchn = bind_ipi.port;
  732. xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
  733. bind_evtchn_to_cpu(evtchn, cpu);
  734. } else {
  735. struct irq_info *info = info_for_irq(irq);
  736. WARN_ON(info == NULL || info->type != IRQT_IPI);
  737. }
  738. out:
  739. mutex_unlock(&irq_mapping_update_lock);
  740. return irq;
  741. }
  742. static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
  743. unsigned int remote_port)
  744. {
  745. struct evtchn_bind_interdomain bind_interdomain;
  746. int err;
  747. bind_interdomain.remote_dom = remote_domain;
  748. bind_interdomain.remote_port = remote_port;
  749. err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
  750. &bind_interdomain);
  751. return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
  752. }
  753. static int find_virq(unsigned int virq, unsigned int cpu)
  754. {
  755. struct evtchn_status status;
  756. int port, rc = -ENOENT;
  757. memset(&status, 0, sizeof(status));
  758. for (port = 0; port <= NR_EVENT_CHANNELS; port++) {
  759. status.dom = DOMID_SELF;
  760. status.port = port;
  761. rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
  762. if (rc < 0)
  763. continue;
  764. if (status.status != EVTCHNSTAT_virq)
  765. continue;
  766. if (status.u.virq == virq && status.vcpu == cpu) {
  767. rc = port;
  768. break;
  769. }
  770. }
  771. return rc;
  772. }
  773. int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
  774. {
  775. struct evtchn_bind_virq bind_virq;
  776. int evtchn, irq, ret;
  777. mutex_lock(&irq_mapping_update_lock);
  778. irq = per_cpu(virq_to_irq, cpu)[virq];
  779. if (irq == -1) {
  780. irq = xen_allocate_irq_dynamic();
  781. if (irq < 0)
  782. goto out;
  783. irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
  784. handle_percpu_irq, "virq");
  785. bind_virq.virq = virq;
  786. bind_virq.vcpu = cpu;
  787. ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  788. &bind_virq);
  789. if (ret == 0)
  790. evtchn = bind_virq.port;
  791. else {
  792. if (ret == -EEXIST)
  793. ret = find_virq(virq, cpu);
  794. BUG_ON(ret < 0);
  795. evtchn = ret;
  796. }
  797. xen_irq_info_virq_init(cpu, irq, evtchn, virq);
  798. bind_evtchn_to_cpu(evtchn, cpu);
  799. } else {
  800. struct irq_info *info = info_for_irq(irq);
  801. WARN_ON(info == NULL || info->type != IRQT_VIRQ);
  802. }
  803. out:
  804. mutex_unlock(&irq_mapping_update_lock);
  805. return irq;
  806. }
  807. static void unbind_from_irq(unsigned int irq)
  808. {
  809. struct evtchn_close close;
  810. int evtchn = evtchn_from_irq(irq);
  811. struct irq_info *info = irq_get_handler_data(irq);
  812. if (WARN_ON(!info))
  813. return;
  814. mutex_lock(&irq_mapping_update_lock);
  815. if (info->refcnt > 0) {
  816. info->refcnt--;
  817. if (info->refcnt != 0)
  818. goto done;
  819. }
  820. if (VALID_EVTCHN(evtchn)) {
  821. close.port = evtchn;
  822. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  823. BUG();
  824. switch (type_from_irq(irq)) {
  825. case IRQT_VIRQ:
  826. per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
  827. [virq_from_irq(irq)] = -1;
  828. break;
  829. case IRQT_IPI:
  830. per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
  831. [ipi_from_irq(irq)] = -1;
  832. break;
  833. default:
  834. break;
  835. }
  836. /* Closed ports are implicitly re-bound to VCPU0. */
  837. bind_evtchn_to_cpu(evtchn, 0);
  838. evtchn_to_irq[evtchn] = -1;
  839. }
  840. BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
  841. xen_free_irq(irq);
  842. done:
  843. mutex_unlock(&irq_mapping_update_lock);
  844. }
  845. int bind_evtchn_to_irqhandler(unsigned int evtchn,
  846. irq_handler_t handler,
  847. unsigned long irqflags,
  848. const char *devname, void *dev_id)
  849. {
  850. int irq, retval;
  851. irq = bind_evtchn_to_irq(evtchn);
  852. if (irq < 0)
  853. return irq;
  854. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  855. if (retval != 0) {
  856. unbind_from_irq(irq);
  857. return retval;
  858. }
  859. return irq;
  860. }
  861. EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
  862. int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
  863. unsigned int remote_port,
  864. irq_handler_t handler,
  865. unsigned long irqflags,
  866. const char *devname,
  867. void *dev_id)
  868. {
  869. int irq, retval;
  870. irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
  871. if (irq < 0)
  872. return irq;
  873. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  874. if (retval != 0) {
  875. unbind_from_irq(irq);
  876. return retval;
  877. }
  878. return irq;
  879. }
  880. EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
  881. int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
  882. irq_handler_t handler,
  883. unsigned long irqflags, const char *devname, void *dev_id)
  884. {
  885. int irq, retval;
  886. irq = bind_virq_to_irq(virq, cpu);
  887. if (irq < 0)
  888. return irq;
  889. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  890. if (retval != 0) {
  891. unbind_from_irq(irq);
  892. return retval;
  893. }
  894. return irq;
  895. }
  896. EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
  897. int bind_ipi_to_irqhandler(enum ipi_vector ipi,
  898. unsigned int cpu,
  899. irq_handler_t handler,
  900. unsigned long irqflags,
  901. const char *devname,
  902. void *dev_id)
  903. {
  904. int irq, retval;
  905. irq = bind_ipi_to_irq(ipi, cpu);
  906. if (irq < 0)
  907. return irq;
  908. irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
  909. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  910. if (retval != 0) {
  911. unbind_from_irq(irq);
  912. return retval;
  913. }
  914. return irq;
  915. }
  916. void unbind_from_irqhandler(unsigned int irq, void *dev_id)
  917. {
  918. struct irq_info *info = irq_get_handler_data(irq);
  919. if (WARN_ON(!info))
  920. return;
  921. free_irq(irq, dev_id);
  922. unbind_from_irq(irq);
  923. }
  924. EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
  925. int evtchn_make_refcounted(unsigned int evtchn)
  926. {
  927. int irq = evtchn_to_irq[evtchn];
  928. struct irq_info *info;
  929. if (irq == -1)
  930. return -ENOENT;
  931. info = irq_get_handler_data(irq);
  932. if (!info)
  933. return -ENOENT;
  934. WARN_ON(info->refcnt != -1);
  935. info->refcnt = 1;
  936. return 0;
  937. }
  938. EXPORT_SYMBOL_GPL(evtchn_make_refcounted);
  939. int evtchn_get(unsigned int evtchn)
  940. {
  941. int irq;
  942. struct irq_info *info;
  943. int err = -ENOENT;
  944. if (evtchn >= NR_EVENT_CHANNELS)
  945. return -EINVAL;
  946. mutex_lock(&irq_mapping_update_lock);
  947. irq = evtchn_to_irq[evtchn];
  948. if (irq == -1)
  949. goto done;
  950. info = irq_get_handler_data(irq);
  951. if (!info)
  952. goto done;
  953. err = -EINVAL;
  954. if (info->refcnt <= 0)
  955. goto done;
  956. info->refcnt++;
  957. err = 0;
  958. done:
  959. mutex_unlock(&irq_mapping_update_lock);
  960. return err;
  961. }
  962. EXPORT_SYMBOL_GPL(evtchn_get);
  963. void evtchn_put(unsigned int evtchn)
  964. {
  965. int irq = evtchn_to_irq[evtchn];
  966. if (WARN_ON(irq == -1))
  967. return;
  968. unbind_from_irq(irq);
  969. }
  970. EXPORT_SYMBOL_GPL(evtchn_put);
  971. void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
  972. {
  973. int irq = per_cpu(ipi_to_irq, cpu)[vector];
  974. BUG_ON(irq < 0);
  975. notify_remote_via_irq(irq);
  976. }
  977. irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
  978. {
  979. struct shared_info *sh = HYPERVISOR_shared_info;
  980. int cpu = smp_processor_id();
  981. xen_ulong_t *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
  982. int i;
  983. unsigned long flags;
  984. static DEFINE_SPINLOCK(debug_lock);
  985. struct vcpu_info *v;
  986. spin_lock_irqsave(&debug_lock, flags);
  987. printk("\nvcpu %d\n ", cpu);
  988. for_each_online_cpu(i) {
  989. int pending;
  990. v = per_cpu(xen_vcpu, i);
  991. pending = (get_irq_regs() && i == cpu)
  992. ? xen_irqs_disabled(get_irq_regs())
  993. : v->evtchn_upcall_mask;
  994. printk("%d: masked=%d pending=%d event_sel %0*"PRI_xen_ulong"\n ", i,
  995. pending, v->evtchn_upcall_pending,
  996. (int)(sizeof(v->evtchn_pending_sel)*2),
  997. v->evtchn_pending_sel);
  998. }
  999. v = per_cpu(xen_vcpu, cpu);
  1000. printk("\npending:\n ");
  1001. for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
  1002. printk("%0*"PRI_xen_ulong"%s",
  1003. (int)sizeof(sh->evtchn_pending[0])*2,
  1004. sh->evtchn_pending[i],
  1005. i % 8 == 0 ? "\n " : " ");
  1006. printk("\nglobal mask:\n ");
  1007. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  1008. printk("%0*"PRI_xen_ulong"%s",
  1009. (int)(sizeof(sh->evtchn_mask[0])*2),
  1010. sh->evtchn_mask[i],
  1011. i % 8 == 0 ? "\n " : " ");
  1012. printk("\nglobally unmasked:\n ");
  1013. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  1014. printk("%0*"PRI_xen_ulong"%s",
  1015. (int)(sizeof(sh->evtchn_mask[0])*2),
  1016. sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
  1017. i % 8 == 0 ? "\n " : " ");
  1018. printk("\nlocal cpu%d mask:\n ", cpu);
  1019. for (i = (NR_EVENT_CHANNELS/BITS_PER_EVTCHN_WORD)-1; i >= 0; i--)
  1020. printk("%0*"PRI_xen_ulong"%s", (int)(sizeof(cpu_evtchn[0])*2),
  1021. cpu_evtchn[i],
  1022. i % 8 == 0 ? "\n " : " ");
  1023. printk("\nlocally unmasked:\n ");
  1024. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
  1025. xen_ulong_t pending = sh->evtchn_pending[i]
  1026. & ~sh->evtchn_mask[i]
  1027. & cpu_evtchn[i];
  1028. printk("%0*"PRI_xen_ulong"%s",
  1029. (int)(sizeof(sh->evtchn_mask[0])*2),
  1030. pending, i % 8 == 0 ? "\n " : " ");
  1031. }
  1032. printk("\npending list:\n");
  1033. for (i = 0; i < NR_EVENT_CHANNELS; i++) {
  1034. if (sync_test_bit(i, BM(sh->evtchn_pending))) {
  1035. int word_idx = i / BITS_PER_EVTCHN_WORD;
  1036. printk(" %d: event %d -> irq %d%s%s%s\n",
  1037. cpu_from_evtchn(i), i,
  1038. evtchn_to_irq[i],
  1039. sync_test_bit(word_idx, BM(&v->evtchn_pending_sel))
  1040. ? "" : " l2-clear",
  1041. !sync_test_bit(i, BM(sh->evtchn_mask))
  1042. ? "" : " globally-masked",
  1043. sync_test_bit(i, BM(cpu_evtchn))
  1044. ? "" : " locally-masked");
  1045. }
  1046. }
  1047. spin_unlock_irqrestore(&debug_lock, flags);
  1048. return IRQ_HANDLED;
  1049. }
  1050. static DEFINE_PER_CPU(unsigned, xed_nesting_count);
  1051. static DEFINE_PER_CPU(unsigned int, current_word_idx);
  1052. static DEFINE_PER_CPU(unsigned int, current_bit_idx);
  1053. /*
  1054. * Mask out the i least significant bits of w
  1055. */
  1056. #define MASK_LSBS(w, i) (w & ((~((xen_ulong_t)0UL)) << i))
  1057. /*
  1058. * Search the CPUs pending events bitmasks. For each one found, map
  1059. * the event number to an irq, and feed it into do_IRQ() for
  1060. * handling.
  1061. *
  1062. * Xen uses a two-level bitmap to speed searching. The first level is
  1063. * a bitset of words which contain pending event bits. The second
  1064. * level is a bitset of pending events themselves.
  1065. */
  1066. static void __xen_evtchn_do_upcall(void)
  1067. {
  1068. int start_word_idx, start_bit_idx;
  1069. int word_idx, bit_idx;
  1070. int i, irq;
  1071. int cpu = get_cpu();
  1072. struct shared_info *s = HYPERVISOR_shared_info;
  1073. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  1074. unsigned count;
  1075. do {
  1076. xen_ulong_t pending_words;
  1077. xen_ulong_t pending_bits;
  1078. struct irq_desc *desc;
  1079. vcpu_info->evtchn_upcall_pending = 0;
  1080. if (__this_cpu_inc_return(xed_nesting_count) - 1)
  1081. goto out;
  1082. /*
  1083. * Master flag must be cleared /before/ clearing
  1084. * selector flag. xchg_xen_ulong must contain an
  1085. * appropriate barrier.
  1086. */
  1087. if ((irq = per_cpu(virq_to_irq, cpu)[VIRQ_TIMER]) != -1) {
  1088. int evtchn = evtchn_from_irq(irq);
  1089. word_idx = evtchn / BITS_PER_LONG;
  1090. pending_bits = evtchn % BITS_PER_LONG;
  1091. if (active_evtchns(cpu, s, word_idx) & (1ULL << pending_bits)) {
  1092. desc = irq_to_desc(irq);
  1093. if (desc)
  1094. generic_handle_irq_desc(irq, desc);
  1095. }
  1096. }
  1097. pending_words = xchg_xen_ulong(&vcpu_info->evtchn_pending_sel, 0);
  1098. start_word_idx = __this_cpu_read(current_word_idx);
  1099. start_bit_idx = __this_cpu_read(current_bit_idx);
  1100. word_idx = start_word_idx;
  1101. for (i = 0; pending_words != 0; i++) {
  1102. xen_ulong_t words;
  1103. words = MASK_LSBS(pending_words, word_idx);
  1104. /*
  1105. * If we masked out all events, wrap to beginning.
  1106. */
  1107. if (words == 0) {
  1108. word_idx = 0;
  1109. bit_idx = 0;
  1110. continue;
  1111. }
  1112. word_idx = EVTCHN_FIRST_BIT(words);
  1113. pending_bits = active_evtchns(cpu, s, word_idx);
  1114. bit_idx = 0; /* usually scan entire word from start */
  1115. if (word_idx == start_word_idx) {
  1116. /* We scan the starting word in two parts */
  1117. if (i == 0)
  1118. /* 1st time: start in the middle */
  1119. bit_idx = start_bit_idx;
  1120. else
  1121. /* 2nd time: mask bits done already */
  1122. bit_idx &= (1UL << start_bit_idx) - 1;
  1123. }
  1124. do {
  1125. xen_ulong_t bits;
  1126. int port;
  1127. bits = MASK_LSBS(pending_bits, bit_idx);
  1128. /* If we masked out all events, move on. */
  1129. if (bits == 0)
  1130. break;
  1131. bit_idx = EVTCHN_FIRST_BIT(bits);
  1132. /* Process port. */
  1133. port = (word_idx * BITS_PER_EVTCHN_WORD) + bit_idx;
  1134. irq = evtchn_to_irq[port];
  1135. if (irq != -1) {
  1136. desc = irq_to_desc(irq);
  1137. if (desc)
  1138. generic_handle_irq_desc(irq, desc);
  1139. }
  1140. bit_idx = (bit_idx + 1) % BITS_PER_EVTCHN_WORD;
  1141. /* Next caller starts at last processed + 1 */
  1142. __this_cpu_write(current_word_idx,
  1143. bit_idx ? word_idx :
  1144. (word_idx+1) % BITS_PER_EVTCHN_WORD);
  1145. __this_cpu_write(current_bit_idx, bit_idx);
  1146. } while (bit_idx != 0);
  1147. /* Scan start_l1i twice; all others once. */
  1148. if ((word_idx != start_word_idx) || (i != 0))
  1149. pending_words &= ~(1UL << word_idx);
  1150. word_idx = (word_idx + 1) % BITS_PER_EVTCHN_WORD;
  1151. }
  1152. BUG_ON(!irqs_disabled());
  1153. count = __this_cpu_read(xed_nesting_count);
  1154. __this_cpu_write(xed_nesting_count, 0);
  1155. } while (count != 1 || vcpu_info->evtchn_upcall_pending);
  1156. out:
  1157. put_cpu();
  1158. }
  1159. void xen_evtchn_do_upcall(struct pt_regs *regs)
  1160. {
  1161. struct pt_regs *old_regs = set_irq_regs(regs);
  1162. irq_enter();
  1163. #ifdef CONFIG_X86
  1164. exit_idle();
  1165. #endif
  1166. __xen_evtchn_do_upcall();
  1167. irq_exit();
  1168. set_irq_regs(old_regs);
  1169. }
  1170. void xen_hvm_evtchn_do_upcall(void)
  1171. {
  1172. __xen_evtchn_do_upcall();
  1173. }
  1174. EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
  1175. /* Rebind a new event channel to an existing irq. */
  1176. void rebind_evtchn_irq(int evtchn, int irq)
  1177. {
  1178. struct irq_info *info = info_for_irq(irq);
  1179. if (WARN_ON(!info))
  1180. return;
  1181. /* Make sure the irq is masked, since the new event channel
  1182. will also be masked. */
  1183. disable_irq(irq);
  1184. mutex_lock(&irq_mapping_update_lock);
  1185. /* After resume the irq<->evtchn mappings are all cleared out */
  1186. BUG_ON(evtchn_to_irq[evtchn] != -1);
  1187. /* Expect irq to have been bound before,
  1188. so there should be a proper type */
  1189. BUG_ON(info->type == IRQT_UNBOUND);
  1190. xen_irq_info_evtchn_init(irq, evtchn);
  1191. mutex_unlock(&irq_mapping_update_lock);
  1192. /* new event channels are always bound to cpu 0 */
  1193. irq_set_affinity(irq, cpumask_of(0));
  1194. /* Unmask the event channel. */
  1195. enable_irq(irq);
  1196. }
  1197. /* Rebind an evtchn so that it gets delivered to a specific cpu */
  1198. static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
  1199. {
  1200. struct evtchn_bind_vcpu bind_vcpu;
  1201. int evtchn = evtchn_from_irq(irq);
  1202. if (!VALID_EVTCHN(evtchn))
  1203. return -1;
  1204. /*
  1205. * Events delivered via platform PCI interrupts are always
  1206. * routed to vcpu 0 and hence cannot be rebound.
  1207. */
  1208. if (xen_hvm_domain() && !xen_have_vector_callback)
  1209. return -1;
  1210. /* Send future instances of this interrupt to other vcpu. */
  1211. bind_vcpu.port = evtchn;
  1212. bind_vcpu.vcpu = tcpu;
  1213. /*
  1214. * If this fails, it usually just indicates that we're dealing with a
  1215. * virq or IPI channel, which don't actually need to be rebound. Ignore
  1216. * it, but don't do the xenlinux-level rebind in that case.
  1217. */
  1218. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
  1219. bind_evtchn_to_cpu(evtchn, tcpu);
  1220. return 0;
  1221. }
  1222. static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
  1223. bool force)
  1224. {
  1225. unsigned tcpu = cpumask_first(dest);
  1226. return rebind_irq_to_cpu(data->irq, tcpu);
  1227. }
  1228. int resend_irq_on_evtchn(unsigned int irq)
  1229. {
  1230. int masked, evtchn = evtchn_from_irq(irq);
  1231. struct shared_info *s = HYPERVISOR_shared_info;
  1232. if (!VALID_EVTCHN(evtchn))
  1233. return 1;
  1234. masked = sync_test_and_set_bit(evtchn, BM(s->evtchn_mask));
  1235. sync_set_bit(evtchn, BM(s->evtchn_pending));
  1236. if (!masked)
  1237. unmask_evtchn(evtchn);
  1238. return 1;
  1239. }
  1240. static void enable_dynirq(struct irq_data *data)
  1241. {
  1242. int evtchn = evtchn_from_irq(data->irq);
  1243. if (VALID_EVTCHN(evtchn))
  1244. unmask_evtchn(evtchn);
  1245. }
  1246. static void disable_dynirq(struct irq_data *data)
  1247. {
  1248. int evtchn = evtchn_from_irq(data->irq);
  1249. if (VALID_EVTCHN(evtchn))
  1250. mask_evtchn(evtchn);
  1251. }
  1252. static void ack_dynirq(struct irq_data *data)
  1253. {
  1254. int evtchn = evtchn_from_irq(data->irq);
  1255. irq_move_irq(data);
  1256. if (VALID_EVTCHN(evtchn))
  1257. clear_evtchn(evtchn);
  1258. }
  1259. static void mask_ack_dynirq(struct irq_data *data)
  1260. {
  1261. disable_dynirq(data);
  1262. ack_dynirq(data);
  1263. }
  1264. static int retrigger_dynirq(struct irq_data *data)
  1265. {
  1266. int evtchn = evtchn_from_irq(data->irq);
  1267. struct shared_info *sh = HYPERVISOR_shared_info;
  1268. int ret = 0;
  1269. if (VALID_EVTCHN(evtchn)) {
  1270. int masked;
  1271. masked = sync_test_and_set_bit(evtchn, BM(sh->evtchn_mask));
  1272. sync_set_bit(evtchn, BM(sh->evtchn_pending));
  1273. if (!masked)
  1274. unmask_evtchn(evtchn);
  1275. ret = 1;
  1276. }
  1277. return ret;
  1278. }
  1279. static void restore_pirqs(void)
  1280. {
  1281. int pirq, rc, irq, gsi;
  1282. struct physdev_map_pirq map_irq;
  1283. struct irq_info *info;
  1284. list_for_each_entry(info, &xen_irq_list_head, list) {
  1285. if (info->type != IRQT_PIRQ)
  1286. continue;
  1287. pirq = info->u.pirq.pirq;
  1288. gsi = info->u.pirq.gsi;
  1289. irq = info->irq;
  1290. /* save/restore of PT devices doesn't work, so at this point the
  1291. * only devices present are GSI based emulated devices */
  1292. if (!gsi)
  1293. continue;
  1294. map_irq.domid = DOMID_SELF;
  1295. map_irq.type = MAP_PIRQ_TYPE_GSI;
  1296. map_irq.index = gsi;
  1297. map_irq.pirq = pirq;
  1298. rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
  1299. if (rc) {
  1300. printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
  1301. gsi, irq, pirq, rc);
  1302. xen_free_irq(irq);
  1303. continue;
  1304. }
  1305. printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
  1306. __startup_pirq(irq);
  1307. }
  1308. }
  1309. static void restore_cpu_virqs(unsigned int cpu)
  1310. {
  1311. struct evtchn_bind_virq bind_virq;
  1312. int virq, irq, evtchn;
  1313. for (virq = 0; virq < NR_VIRQS; virq++) {
  1314. if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
  1315. continue;
  1316. BUG_ON(virq_from_irq(irq) != virq);
  1317. /* Get a new binding from Xen. */
  1318. bind_virq.virq = virq;
  1319. bind_virq.vcpu = cpu;
  1320. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  1321. &bind_virq) != 0)
  1322. BUG();
  1323. evtchn = bind_virq.port;
  1324. /* Record the new mapping. */
  1325. xen_irq_info_virq_init(cpu, irq, evtchn, virq);
  1326. bind_evtchn_to_cpu(evtchn, cpu);
  1327. }
  1328. }
  1329. static void restore_cpu_ipis(unsigned int cpu)
  1330. {
  1331. struct evtchn_bind_ipi bind_ipi;
  1332. int ipi, irq, evtchn;
  1333. for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
  1334. if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
  1335. continue;
  1336. BUG_ON(ipi_from_irq(irq) != ipi);
  1337. /* Get a new binding from Xen. */
  1338. bind_ipi.vcpu = cpu;
  1339. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  1340. &bind_ipi) != 0)
  1341. BUG();
  1342. evtchn = bind_ipi.port;
  1343. /* Record the new mapping. */
  1344. xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
  1345. bind_evtchn_to_cpu(evtchn, cpu);
  1346. }
  1347. }
  1348. /* Clear an irq's pending state, in preparation for polling on it */
  1349. void xen_clear_irq_pending(int irq)
  1350. {
  1351. int evtchn = evtchn_from_irq(irq);
  1352. if (VALID_EVTCHN(evtchn))
  1353. clear_evtchn(evtchn);
  1354. }
  1355. EXPORT_SYMBOL(xen_clear_irq_pending);
  1356. void xen_set_irq_pending(int irq)
  1357. {
  1358. int evtchn = evtchn_from_irq(irq);
  1359. if (VALID_EVTCHN(evtchn))
  1360. set_evtchn(evtchn);
  1361. }
  1362. bool xen_test_irq_pending(int irq)
  1363. {
  1364. int evtchn = evtchn_from_irq(irq);
  1365. bool ret = false;
  1366. if (VALID_EVTCHN(evtchn))
  1367. ret = test_evtchn(evtchn);
  1368. return ret;
  1369. }
  1370. /* Poll waiting for an irq to become pending with timeout. In the usual case,
  1371. * the irq will be disabled so it won't deliver an interrupt. */
  1372. void xen_poll_irq_timeout(int irq, u64 timeout)
  1373. {
  1374. evtchn_port_t evtchn = evtchn_from_irq(irq);
  1375. if (VALID_EVTCHN(evtchn)) {
  1376. struct sched_poll poll;
  1377. poll.nr_ports = 1;
  1378. poll.timeout = timeout;
  1379. set_xen_guest_handle(poll.ports, &evtchn);
  1380. if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
  1381. BUG();
  1382. }
  1383. }
  1384. EXPORT_SYMBOL(xen_poll_irq_timeout);
  1385. /* Poll waiting for an irq to become pending. In the usual case, the
  1386. * irq will be disabled so it won't deliver an interrupt. */
  1387. void xen_poll_irq(int irq)
  1388. {
  1389. xen_poll_irq_timeout(irq, 0 /* no timeout */);
  1390. }
  1391. /* Check whether the IRQ line is shared with other guests. */
  1392. int xen_test_irq_shared(int irq)
  1393. {
  1394. struct irq_info *info = info_for_irq(irq);
  1395. struct physdev_irq_status_query irq_status;
  1396. if (WARN_ON(!info))
  1397. return -ENOENT;
  1398. irq_status.irq = info->u.pirq.pirq;
  1399. if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
  1400. return 0;
  1401. return !(irq_status.flags & XENIRQSTAT_shared);
  1402. }
  1403. EXPORT_SYMBOL_GPL(xen_test_irq_shared);
  1404. void xen_irq_resume(void)
  1405. {
  1406. unsigned int cpu, evtchn;
  1407. struct irq_info *info;
  1408. init_evtchn_cpu_bindings();
  1409. /* New event-channel space is not 'live' yet. */
  1410. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1411. mask_evtchn(evtchn);
  1412. /* No IRQ <-> event-channel mappings. */
  1413. list_for_each_entry(info, &xen_irq_list_head, list)
  1414. info->evtchn = 0; /* zap event-channel binding */
  1415. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1416. evtchn_to_irq[evtchn] = -1;
  1417. for_each_possible_cpu(cpu) {
  1418. restore_cpu_virqs(cpu);
  1419. restore_cpu_ipis(cpu);
  1420. }
  1421. restore_pirqs();
  1422. }
  1423. static struct irq_chip xen_dynamic_chip __read_mostly = {
  1424. .name = "xen-dyn",
  1425. .irq_disable = disable_dynirq,
  1426. .irq_mask = disable_dynirq,
  1427. .irq_unmask = enable_dynirq,
  1428. .irq_ack = ack_dynirq,
  1429. .irq_mask_ack = mask_ack_dynirq,
  1430. .irq_set_affinity = set_affinity_irq,
  1431. .irq_retrigger = retrigger_dynirq,
  1432. };
  1433. static struct irq_chip xen_pirq_chip __read_mostly = {
  1434. .name = "xen-pirq",
  1435. .irq_startup = startup_pirq,
  1436. .irq_shutdown = shutdown_pirq,
  1437. .irq_enable = enable_pirq,
  1438. .irq_disable = disable_pirq,
  1439. .irq_mask = disable_dynirq,
  1440. .irq_unmask = enable_dynirq,
  1441. .irq_ack = eoi_pirq,
  1442. .irq_eoi = eoi_pirq,
  1443. .irq_mask_ack = mask_ack_pirq,
  1444. .irq_set_affinity = set_affinity_irq,
  1445. .irq_retrigger = retrigger_dynirq,
  1446. };
  1447. static struct irq_chip xen_percpu_chip __read_mostly = {
  1448. .name = "xen-percpu",
  1449. .irq_disable = disable_dynirq,
  1450. .irq_mask = disable_dynirq,
  1451. .irq_unmask = enable_dynirq,
  1452. .irq_ack = ack_dynirq,
  1453. };
  1454. int xen_set_callback_via(uint64_t via)
  1455. {
  1456. struct xen_hvm_param a;
  1457. a.domid = DOMID_SELF;
  1458. a.index = HVM_PARAM_CALLBACK_IRQ;
  1459. a.value = via;
  1460. return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
  1461. }
  1462. EXPORT_SYMBOL_GPL(xen_set_callback_via);
  1463. #ifdef CONFIG_XEN_PVHVM
  1464. /* Vector callbacks are better than PCI interrupts to receive event
  1465. * channel notifications because we can receive vector callbacks on any
  1466. * vcpu and we don't need PCI support or APIC interactions. */
  1467. void xen_callback_vector(void)
  1468. {
  1469. int rc;
  1470. uint64_t callback_via;
  1471. if (xen_have_vector_callback) {
  1472. callback_via = HVM_CALLBACK_VECTOR(HYPERVISOR_CALLBACK_VECTOR);
  1473. rc = xen_set_callback_via(callback_via);
  1474. if (rc) {
  1475. printk(KERN_ERR "Request for Xen HVM callback vector"
  1476. " failed.\n");
  1477. xen_have_vector_callback = 0;
  1478. return;
  1479. }
  1480. printk(KERN_INFO "Xen HVM callback vector for event delivery is "
  1481. "enabled\n");
  1482. /* in the restore case the vector has already been allocated */
  1483. if (!test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors))
  1484. alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR,
  1485. xen_hvm_callback_vector);
  1486. }
  1487. }
  1488. #else
  1489. void xen_callback_vector(void) {}
  1490. #endif
  1491. void __init xen_init_IRQ(void)
  1492. {
  1493. int i;
  1494. evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
  1495. GFP_KERNEL);
  1496. BUG_ON(!evtchn_to_irq);
  1497. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1498. evtchn_to_irq[i] = -1;
  1499. init_evtchn_cpu_bindings();
  1500. /* No event channels are 'live' right now. */
  1501. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1502. mask_evtchn(i);
  1503. pirq_needs_eoi = pirq_needs_eoi_flag;
  1504. #ifdef CONFIG_X86
  1505. if (xen_hvm_domain()) {
  1506. xen_callback_vector();
  1507. native_init_IRQ();
  1508. /* pci_xen_hvm_init must be called after native_init_IRQ so that
  1509. * __acpi_register_gsi can point at the right function */
  1510. pci_xen_hvm_init();
  1511. } else {
  1512. int rc;
  1513. struct physdev_pirq_eoi_gmfn eoi_gmfn;
  1514. irq_ctx_init(smp_processor_id());
  1515. if (xen_initial_domain())
  1516. pci_xen_initial_domain();
  1517. pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
  1518. eoi_gmfn.gmfn = virt_to_mfn(pirq_eoi_map);
  1519. rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn);
  1520. if (rc != 0) {
  1521. free_page((unsigned long) pirq_eoi_map);
  1522. pirq_eoi_map = NULL;
  1523. } else
  1524. pirq_needs_eoi = pirq_check_eoi_map;
  1525. }
  1526. #endif
  1527. }