bnx2fc_hwi.c 62 KB

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  1. /* bnx2fc_hwi.c: Broadcom NetXtreme II Linux FCoE offload driver.
  2. * This file contains the code that low level functions that interact
  3. * with 57712 FCoE firmware.
  4. *
  5. * Copyright (c) 2008 - 2013 Broadcom Corporation
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation.
  10. *
  11. * Written by: Bhanu Prakash Gollapudi (bprakash@broadcom.com)
  12. */
  13. #include "bnx2fc.h"
  14. DECLARE_PER_CPU(struct bnx2fc_percpu_s, bnx2fc_percpu);
  15. static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
  16. struct fcoe_kcqe *new_cqe_kcqe);
  17. static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
  18. struct fcoe_kcqe *ofld_kcqe);
  19. static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
  20. struct fcoe_kcqe *ofld_kcqe);
  21. static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code);
  22. static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
  23. struct fcoe_kcqe *destroy_kcqe);
  24. int bnx2fc_send_stat_req(struct bnx2fc_hba *hba)
  25. {
  26. struct fcoe_kwqe_stat stat_req;
  27. struct kwqe *kwqe_arr[2];
  28. int num_kwqes = 1;
  29. int rc = 0;
  30. memset(&stat_req, 0x00, sizeof(struct fcoe_kwqe_stat));
  31. stat_req.hdr.op_code = FCOE_KWQE_OPCODE_STAT;
  32. stat_req.hdr.flags =
  33. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  34. stat_req.stat_params_addr_lo = (u32) hba->stats_buf_dma;
  35. stat_req.stat_params_addr_hi = (u32) ((u64)hba->stats_buf_dma >> 32);
  36. kwqe_arr[0] = (struct kwqe *) &stat_req;
  37. if (hba->cnic && hba->cnic->submit_kwqes)
  38. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  39. return rc;
  40. }
  41. /**
  42. * bnx2fc_send_fw_fcoe_init_msg - initiates initial handshake with FCoE f/w
  43. *
  44. * @hba: adapter structure pointer
  45. *
  46. * Send down FCoE firmware init KWQEs which initiates the initial handshake
  47. * with the f/w.
  48. *
  49. */
  50. int bnx2fc_send_fw_fcoe_init_msg(struct bnx2fc_hba *hba)
  51. {
  52. struct fcoe_kwqe_init1 fcoe_init1;
  53. struct fcoe_kwqe_init2 fcoe_init2;
  54. struct fcoe_kwqe_init3 fcoe_init3;
  55. struct kwqe *kwqe_arr[3];
  56. int num_kwqes = 3;
  57. int rc = 0;
  58. if (!hba->cnic) {
  59. printk(KERN_ERR PFX "hba->cnic NULL during fcoe fw init\n");
  60. return -ENODEV;
  61. }
  62. /* fill init1 KWQE */
  63. memset(&fcoe_init1, 0x00, sizeof(struct fcoe_kwqe_init1));
  64. fcoe_init1.hdr.op_code = FCOE_KWQE_OPCODE_INIT1;
  65. fcoe_init1.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  66. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  67. fcoe_init1.num_tasks = hba->max_tasks;
  68. fcoe_init1.sq_num_wqes = BNX2FC_SQ_WQES_MAX;
  69. fcoe_init1.rq_num_wqes = BNX2FC_RQ_WQES_MAX;
  70. fcoe_init1.rq_buffer_log_size = BNX2FC_RQ_BUF_LOG_SZ;
  71. fcoe_init1.cq_num_wqes = BNX2FC_CQ_WQES_MAX;
  72. fcoe_init1.dummy_buffer_addr_lo = (u32) hba->dummy_buf_dma;
  73. fcoe_init1.dummy_buffer_addr_hi = (u32) ((u64)hba->dummy_buf_dma >> 32);
  74. fcoe_init1.task_list_pbl_addr_lo = (u32) hba->task_ctx_bd_dma;
  75. fcoe_init1.task_list_pbl_addr_hi =
  76. (u32) ((u64) hba->task_ctx_bd_dma >> 32);
  77. fcoe_init1.mtu = BNX2FC_MINI_JUMBO_MTU;
  78. fcoe_init1.flags = (PAGE_SHIFT <<
  79. FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT);
  80. fcoe_init1.num_sessions_log = BNX2FC_NUM_MAX_SESS_LOG;
  81. /* fill init2 KWQE */
  82. memset(&fcoe_init2, 0x00, sizeof(struct fcoe_kwqe_init2));
  83. fcoe_init2.hdr.op_code = FCOE_KWQE_OPCODE_INIT2;
  84. fcoe_init2.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  85. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  86. fcoe_init2.hsi_major_version = FCOE_HSI_MAJOR_VERSION;
  87. fcoe_init2.hsi_minor_version = FCOE_HSI_MINOR_VERSION;
  88. fcoe_init2.hash_tbl_pbl_addr_lo = (u32) hba->hash_tbl_pbl_dma;
  89. fcoe_init2.hash_tbl_pbl_addr_hi = (u32)
  90. ((u64) hba->hash_tbl_pbl_dma >> 32);
  91. fcoe_init2.t2_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_dma;
  92. fcoe_init2.t2_hash_tbl_addr_hi = (u32)
  93. ((u64) hba->t2_hash_tbl_dma >> 32);
  94. fcoe_init2.t2_ptr_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_ptr_dma;
  95. fcoe_init2.t2_ptr_hash_tbl_addr_hi = (u32)
  96. ((u64) hba->t2_hash_tbl_ptr_dma >> 32);
  97. fcoe_init2.free_list_count = BNX2FC_NUM_MAX_SESS;
  98. /* fill init3 KWQE */
  99. memset(&fcoe_init3, 0x00, sizeof(struct fcoe_kwqe_init3));
  100. fcoe_init3.hdr.op_code = FCOE_KWQE_OPCODE_INIT3;
  101. fcoe_init3.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  102. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  103. fcoe_init3.error_bit_map_lo = 0xffffffff;
  104. fcoe_init3.error_bit_map_hi = 0xffffffff;
  105. /*
  106. * enable both cached connection and cached tasks
  107. * 0 = none, 1 = cached connection, 2 = cached tasks, 3 = both
  108. */
  109. fcoe_init3.perf_config = 3;
  110. kwqe_arr[0] = (struct kwqe *) &fcoe_init1;
  111. kwqe_arr[1] = (struct kwqe *) &fcoe_init2;
  112. kwqe_arr[2] = (struct kwqe *) &fcoe_init3;
  113. if (hba->cnic && hba->cnic->submit_kwqes)
  114. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  115. return rc;
  116. }
  117. int bnx2fc_send_fw_fcoe_destroy_msg(struct bnx2fc_hba *hba)
  118. {
  119. struct fcoe_kwqe_destroy fcoe_destroy;
  120. struct kwqe *kwqe_arr[2];
  121. int num_kwqes = 1;
  122. int rc = -1;
  123. /* fill destroy KWQE */
  124. memset(&fcoe_destroy, 0x00, sizeof(struct fcoe_kwqe_destroy));
  125. fcoe_destroy.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY;
  126. fcoe_destroy.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  127. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  128. kwqe_arr[0] = (struct kwqe *) &fcoe_destroy;
  129. if (hba->cnic && hba->cnic->submit_kwqes)
  130. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  131. return rc;
  132. }
  133. /**
  134. * bnx2fc_send_session_ofld_req - initiates FCoE Session offload process
  135. *
  136. * @port: port structure pointer
  137. * @tgt: bnx2fc_rport structure pointer
  138. */
  139. int bnx2fc_send_session_ofld_req(struct fcoe_port *port,
  140. struct bnx2fc_rport *tgt)
  141. {
  142. struct fc_lport *lport = port->lport;
  143. struct bnx2fc_interface *interface = port->priv;
  144. struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface);
  145. struct bnx2fc_hba *hba = interface->hba;
  146. struct kwqe *kwqe_arr[4];
  147. struct fcoe_kwqe_conn_offload1 ofld_req1;
  148. struct fcoe_kwqe_conn_offload2 ofld_req2;
  149. struct fcoe_kwqe_conn_offload3 ofld_req3;
  150. struct fcoe_kwqe_conn_offload4 ofld_req4;
  151. struct fc_rport_priv *rdata = tgt->rdata;
  152. struct fc_rport *rport = tgt->rport;
  153. int num_kwqes = 4;
  154. u32 port_id;
  155. int rc = 0;
  156. u16 conn_id;
  157. /* Initialize offload request 1 structure */
  158. memset(&ofld_req1, 0x00, sizeof(struct fcoe_kwqe_conn_offload1));
  159. ofld_req1.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN1;
  160. ofld_req1.hdr.flags =
  161. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  162. conn_id = (u16)tgt->fcoe_conn_id;
  163. ofld_req1.fcoe_conn_id = conn_id;
  164. ofld_req1.sq_addr_lo = (u32) tgt->sq_dma;
  165. ofld_req1.sq_addr_hi = (u32)((u64) tgt->sq_dma >> 32);
  166. ofld_req1.rq_pbl_addr_lo = (u32) tgt->rq_pbl_dma;
  167. ofld_req1.rq_pbl_addr_hi = (u32)((u64) tgt->rq_pbl_dma >> 32);
  168. ofld_req1.rq_first_pbe_addr_lo = (u32) tgt->rq_dma;
  169. ofld_req1.rq_first_pbe_addr_hi =
  170. (u32)((u64) tgt->rq_dma >> 32);
  171. ofld_req1.rq_prod = 0x8000;
  172. /* Initialize offload request 2 structure */
  173. memset(&ofld_req2, 0x00, sizeof(struct fcoe_kwqe_conn_offload2));
  174. ofld_req2.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN2;
  175. ofld_req2.hdr.flags =
  176. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  177. ofld_req2.tx_max_fc_pay_len = rdata->maxframe_size;
  178. ofld_req2.cq_addr_lo = (u32) tgt->cq_dma;
  179. ofld_req2.cq_addr_hi = (u32)((u64)tgt->cq_dma >> 32);
  180. ofld_req2.xferq_addr_lo = (u32) tgt->xferq_dma;
  181. ofld_req2.xferq_addr_hi = (u32)((u64)tgt->xferq_dma >> 32);
  182. ofld_req2.conn_db_addr_lo = (u32)tgt->conn_db_dma;
  183. ofld_req2.conn_db_addr_hi = (u32)((u64)tgt->conn_db_dma >> 32);
  184. /* Initialize offload request 3 structure */
  185. memset(&ofld_req3, 0x00, sizeof(struct fcoe_kwqe_conn_offload3));
  186. ofld_req3.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN3;
  187. ofld_req3.hdr.flags =
  188. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  189. ofld_req3.vlan_tag = interface->vlan_id <<
  190. FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT;
  191. ofld_req3.vlan_tag |= 3 << FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT;
  192. port_id = fc_host_port_id(lport->host);
  193. if (port_id == 0) {
  194. BNX2FC_HBA_DBG(lport, "ofld_req: port_id = 0, link down?\n");
  195. return -EINVAL;
  196. }
  197. /*
  198. * Store s_id of the initiator for further reference. This will
  199. * be used during disable/destroy during linkdown processing as
  200. * when the lport is reset, the port_id also is reset to 0
  201. */
  202. tgt->sid = port_id;
  203. ofld_req3.s_id[0] = (port_id & 0x000000FF);
  204. ofld_req3.s_id[1] = (port_id & 0x0000FF00) >> 8;
  205. ofld_req3.s_id[2] = (port_id & 0x00FF0000) >> 16;
  206. port_id = rport->port_id;
  207. ofld_req3.d_id[0] = (port_id & 0x000000FF);
  208. ofld_req3.d_id[1] = (port_id & 0x0000FF00) >> 8;
  209. ofld_req3.d_id[2] = (port_id & 0x00FF0000) >> 16;
  210. ofld_req3.tx_total_conc_seqs = rdata->max_seq;
  211. ofld_req3.tx_max_conc_seqs_c3 = rdata->max_seq;
  212. ofld_req3.rx_max_fc_pay_len = lport->mfs;
  213. ofld_req3.rx_total_conc_seqs = BNX2FC_MAX_SEQS;
  214. ofld_req3.rx_max_conc_seqs_c3 = BNX2FC_MAX_SEQS;
  215. ofld_req3.rx_open_seqs_exch_c3 = 1;
  216. ofld_req3.confq_first_pbe_addr_lo = tgt->confq_dma;
  217. ofld_req3.confq_first_pbe_addr_hi = (u32)((u64) tgt->confq_dma >> 32);
  218. /* set mul_n_port_ids supported flag to 0, until it is supported */
  219. ofld_req3.flags = 0;
  220. /*
  221. ofld_req3.flags |= (((lport->send_sp_features & FC_SP_FT_MNA) ? 1:0) <<
  222. FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT);
  223. */
  224. /* Info from PLOGI response */
  225. ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_EDTR) ? 1 : 0) <<
  226. FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT);
  227. ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_SEQC) ? 1 : 0) <<
  228. FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT);
  229. /*
  230. * Info from PRLI response, this info is used for sequence level error
  231. * recovery support
  232. */
  233. if (tgt->dev_type == TYPE_TAPE) {
  234. ofld_req3.flags |= 1 <<
  235. FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT;
  236. ofld_req3.flags |= (((rdata->flags & FC_RP_FLAGS_REC_SUPPORTED)
  237. ? 1 : 0) <<
  238. FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT);
  239. }
  240. /* vlan flag */
  241. ofld_req3.flags |= (interface->vlan_enabled <<
  242. FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT);
  243. /* C2_VALID and ACK flags are not set as they are not supported */
  244. /* Initialize offload request 4 structure */
  245. memset(&ofld_req4, 0x00, sizeof(struct fcoe_kwqe_conn_offload4));
  246. ofld_req4.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN4;
  247. ofld_req4.hdr.flags =
  248. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  249. ofld_req4.e_d_tov_timer_val = lport->e_d_tov / 20;
  250. ofld_req4.src_mac_addr_lo[0] = port->data_src_addr[5];
  251. /* local mac */
  252. ofld_req4.src_mac_addr_lo[1] = port->data_src_addr[4];
  253. ofld_req4.src_mac_addr_mid[0] = port->data_src_addr[3];
  254. ofld_req4.src_mac_addr_mid[1] = port->data_src_addr[2];
  255. ofld_req4.src_mac_addr_hi[0] = port->data_src_addr[1];
  256. ofld_req4.src_mac_addr_hi[1] = port->data_src_addr[0];
  257. ofld_req4.dst_mac_addr_lo[0] = ctlr->dest_addr[5];
  258. /* fcf mac */
  259. ofld_req4.dst_mac_addr_lo[1] = ctlr->dest_addr[4];
  260. ofld_req4.dst_mac_addr_mid[0] = ctlr->dest_addr[3];
  261. ofld_req4.dst_mac_addr_mid[1] = ctlr->dest_addr[2];
  262. ofld_req4.dst_mac_addr_hi[0] = ctlr->dest_addr[1];
  263. ofld_req4.dst_mac_addr_hi[1] = ctlr->dest_addr[0];
  264. ofld_req4.lcq_addr_lo = (u32) tgt->lcq_dma;
  265. ofld_req4.lcq_addr_hi = (u32)((u64) tgt->lcq_dma >> 32);
  266. ofld_req4.confq_pbl_base_addr_lo = (u32) tgt->confq_pbl_dma;
  267. ofld_req4.confq_pbl_base_addr_hi =
  268. (u32)((u64) tgt->confq_pbl_dma >> 32);
  269. kwqe_arr[0] = (struct kwqe *) &ofld_req1;
  270. kwqe_arr[1] = (struct kwqe *) &ofld_req2;
  271. kwqe_arr[2] = (struct kwqe *) &ofld_req3;
  272. kwqe_arr[3] = (struct kwqe *) &ofld_req4;
  273. if (hba->cnic && hba->cnic->submit_kwqes)
  274. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  275. return rc;
  276. }
  277. /**
  278. * bnx2fc_send_session_enable_req - initiates FCoE Session enablement
  279. *
  280. * @port: port structure pointer
  281. * @tgt: bnx2fc_rport structure pointer
  282. */
  283. int bnx2fc_send_session_enable_req(struct fcoe_port *port,
  284. struct bnx2fc_rport *tgt)
  285. {
  286. struct kwqe *kwqe_arr[2];
  287. struct bnx2fc_interface *interface = port->priv;
  288. struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface);
  289. struct bnx2fc_hba *hba = interface->hba;
  290. struct fcoe_kwqe_conn_enable_disable enbl_req;
  291. struct fc_lport *lport = port->lport;
  292. struct fc_rport *rport = tgt->rport;
  293. int num_kwqes = 1;
  294. int rc = 0;
  295. u32 port_id;
  296. memset(&enbl_req, 0x00,
  297. sizeof(struct fcoe_kwqe_conn_enable_disable));
  298. enbl_req.hdr.op_code = FCOE_KWQE_OPCODE_ENABLE_CONN;
  299. enbl_req.hdr.flags =
  300. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  301. enbl_req.src_mac_addr_lo[0] = port->data_src_addr[5];
  302. /* local mac */
  303. enbl_req.src_mac_addr_lo[1] = port->data_src_addr[4];
  304. enbl_req.src_mac_addr_mid[0] = port->data_src_addr[3];
  305. enbl_req.src_mac_addr_mid[1] = port->data_src_addr[2];
  306. enbl_req.src_mac_addr_hi[0] = port->data_src_addr[1];
  307. enbl_req.src_mac_addr_hi[1] = port->data_src_addr[0];
  308. memcpy(tgt->src_addr, port->data_src_addr, ETH_ALEN);
  309. enbl_req.dst_mac_addr_lo[0] = ctlr->dest_addr[5];
  310. enbl_req.dst_mac_addr_lo[1] = ctlr->dest_addr[4];
  311. enbl_req.dst_mac_addr_mid[0] = ctlr->dest_addr[3];
  312. enbl_req.dst_mac_addr_mid[1] = ctlr->dest_addr[2];
  313. enbl_req.dst_mac_addr_hi[0] = ctlr->dest_addr[1];
  314. enbl_req.dst_mac_addr_hi[1] = ctlr->dest_addr[0];
  315. port_id = fc_host_port_id(lport->host);
  316. if (port_id != tgt->sid) {
  317. printk(KERN_ERR PFX "WARN: enable_req port_id = 0x%x,"
  318. "sid = 0x%x\n", port_id, tgt->sid);
  319. port_id = tgt->sid;
  320. }
  321. enbl_req.s_id[0] = (port_id & 0x000000FF);
  322. enbl_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
  323. enbl_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
  324. port_id = rport->port_id;
  325. enbl_req.d_id[0] = (port_id & 0x000000FF);
  326. enbl_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
  327. enbl_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
  328. enbl_req.vlan_tag = interface->vlan_id <<
  329. FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
  330. enbl_req.vlan_tag |= 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
  331. enbl_req.vlan_flag = interface->vlan_enabled;
  332. enbl_req.context_id = tgt->context_id;
  333. enbl_req.conn_id = tgt->fcoe_conn_id;
  334. kwqe_arr[0] = (struct kwqe *) &enbl_req;
  335. if (hba->cnic && hba->cnic->submit_kwqes)
  336. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  337. return rc;
  338. }
  339. /**
  340. * bnx2fc_send_session_disable_req - initiates FCoE Session disable
  341. *
  342. * @port: port structure pointer
  343. * @tgt: bnx2fc_rport structure pointer
  344. */
  345. int bnx2fc_send_session_disable_req(struct fcoe_port *port,
  346. struct bnx2fc_rport *tgt)
  347. {
  348. struct bnx2fc_interface *interface = port->priv;
  349. struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface);
  350. struct bnx2fc_hba *hba = interface->hba;
  351. struct fcoe_kwqe_conn_enable_disable disable_req;
  352. struct kwqe *kwqe_arr[2];
  353. struct fc_rport *rport = tgt->rport;
  354. int num_kwqes = 1;
  355. int rc = 0;
  356. u32 port_id;
  357. memset(&disable_req, 0x00,
  358. sizeof(struct fcoe_kwqe_conn_enable_disable));
  359. disable_req.hdr.op_code = FCOE_KWQE_OPCODE_DISABLE_CONN;
  360. disable_req.hdr.flags =
  361. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  362. disable_req.src_mac_addr_lo[0] = tgt->src_addr[5];
  363. disable_req.src_mac_addr_lo[1] = tgt->src_addr[4];
  364. disable_req.src_mac_addr_mid[0] = tgt->src_addr[3];
  365. disable_req.src_mac_addr_mid[1] = tgt->src_addr[2];
  366. disable_req.src_mac_addr_hi[0] = tgt->src_addr[1];
  367. disable_req.src_mac_addr_hi[1] = tgt->src_addr[0];
  368. disable_req.dst_mac_addr_lo[0] = ctlr->dest_addr[5];
  369. disable_req.dst_mac_addr_lo[1] = ctlr->dest_addr[4];
  370. disable_req.dst_mac_addr_mid[0] = ctlr->dest_addr[3];
  371. disable_req.dst_mac_addr_mid[1] = ctlr->dest_addr[2];
  372. disable_req.dst_mac_addr_hi[0] = ctlr->dest_addr[1];
  373. disable_req.dst_mac_addr_hi[1] = ctlr->dest_addr[0];
  374. port_id = tgt->sid;
  375. disable_req.s_id[0] = (port_id & 0x000000FF);
  376. disable_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
  377. disable_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
  378. port_id = rport->port_id;
  379. disable_req.d_id[0] = (port_id & 0x000000FF);
  380. disable_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
  381. disable_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
  382. disable_req.context_id = tgt->context_id;
  383. disable_req.conn_id = tgt->fcoe_conn_id;
  384. disable_req.vlan_tag = interface->vlan_id <<
  385. FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
  386. disable_req.vlan_tag |=
  387. 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
  388. disable_req.vlan_flag = interface->vlan_enabled;
  389. kwqe_arr[0] = (struct kwqe *) &disable_req;
  390. if (hba->cnic && hba->cnic->submit_kwqes)
  391. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  392. return rc;
  393. }
  394. /**
  395. * bnx2fc_send_session_destroy_req - initiates FCoE Session destroy
  396. *
  397. * @port: port structure pointer
  398. * @tgt: bnx2fc_rport structure pointer
  399. */
  400. int bnx2fc_send_session_destroy_req(struct bnx2fc_hba *hba,
  401. struct bnx2fc_rport *tgt)
  402. {
  403. struct fcoe_kwqe_conn_destroy destroy_req;
  404. struct kwqe *kwqe_arr[2];
  405. int num_kwqes = 1;
  406. int rc = 0;
  407. memset(&destroy_req, 0x00, sizeof(struct fcoe_kwqe_conn_destroy));
  408. destroy_req.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY_CONN;
  409. destroy_req.hdr.flags =
  410. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  411. destroy_req.context_id = tgt->context_id;
  412. destroy_req.conn_id = tgt->fcoe_conn_id;
  413. kwqe_arr[0] = (struct kwqe *) &destroy_req;
  414. if (hba->cnic && hba->cnic->submit_kwqes)
  415. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  416. return rc;
  417. }
  418. static bool is_valid_lport(struct bnx2fc_hba *hba, struct fc_lport *lport)
  419. {
  420. struct bnx2fc_lport *blport;
  421. spin_lock_bh(&hba->hba_lock);
  422. list_for_each_entry(blport, &hba->vports, list) {
  423. if (blport->lport == lport) {
  424. spin_unlock_bh(&hba->hba_lock);
  425. return true;
  426. }
  427. }
  428. spin_unlock_bh(&hba->hba_lock);
  429. return false;
  430. }
  431. static void bnx2fc_unsol_els_work(struct work_struct *work)
  432. {
  433. struct bnx2fc_unsol_els *unsol_els;
  434. struct fc_lport *lport;
  435. struct bnx2fc_hba *hba;
  436. struct fc_frame *fp;
  437. unsol_els = container_of(work, struct bnx2fc_unsol_els, unsol_els_work);
  438. lport = unsol_els->lport;
  439. fp = unsol_els->fp;
  440. hba = unsol_els->hba;
  441. if (is_valid_lport(hba, lport))
  442. fc_exch_recv(lport, fp);
  443. kfree(unsol_els);
  444. }
  445. void bnx2fc_process_l2_frame_compl(struct bnx2fc_rport *tgt,
  446. unsigned char *buf,
  447. u32 frame_len, u16 l2_oxid)
  448. {
  449. struct fcoe_port *port = tgt->port;
  450. struct fc_lport *lport = port->lport;
  451. struct bnx2fc_interface *interface = port->priv;
  452. struct bnx2fc_unsol_els *unsol_els;
  453. struct fc_frame_header *fh;
  454. struct fc_frame *fp;
  455. struct sk_buff *skb;
  456. u32 payload_len;
  457. u32 crc;
  458. u8 op;
  459. unsol_els = kzalloc(sizeof(*unsol_els), GFP_ATOMIC);
  460. if (!unsol_els) {
  461. BNX2FC_TGT_DBG(tgt, "Unable to allocate unsol_work\n");
  462. return;
  463. }
  464. BNX2FC_TGT_DBG(tgt, "l2_frame_compl l2_oxid = 0x%x, frame_len = %d\n",
  465. l2_oxid, frame_len);
  466. payload_len = frame_len - sizeof(struct fc_frame_header);
  467. fp = fc_frame_alloc(lport, payload_len);
  468. if (!fp) {
  469. printk(KERN_ERR PFX "fc_frame_alloc failure\n");
  470. kfree(unsol_els);
  471. return;
  472. }
  473. fh = (struct fc_frame_header *) fc_frame_header_get(fp);
  474. /* Copy FC Frame header and payload into the frame */
  475. memcpy(fh, buf, frame_len);
  476. if (l2_oxid != FC_XID_UNKNOWN)
  477. fh->fh_ox_id = htons(l2_oxid);
  478. skb = fp_skb(fp);
  479. if ((fh->fh_r_ctl == FC_RCTL_ELS_REQ) ||
  480. (fh->fh_r_ctl == FC_RCTL_ELS_REP)) {
  481. if (fh->fh_type == FC_TYPE_ELS) {
  482. op = fc_frame_payload_op(fp);
  483. if ((op == ELS_TEST) || (op == ELS_ESTC) ||
  484. (op == ELS_FAN) || (op == ELS_CSU)) {
  485. /*
  486. * No need to reply for these
  487. * ELS requests
  488. */
  489. printk(KERN_ERR PFX "dropping ELS 0x%x\n", op);
  490. kfree_skb(skb);
  491. kfree(unsol_els);
  492. return;
  493. }
  494. }
  495. crc = fcoe_fc_crc(fp);
  496. fc_frame_init(fp);
  497. fr_dev(fp) = lport;
  498. fr_sof(fp) = FC_SOF_I3;
  499. fr_eof(fp) = FC_EOF_T;
  500. fr_crc(fp) = cpu_to_le32(~crc);
  501. unsol_els->lport = lport;
  502. unsol_els->hba = interface->hba;
  503. unsol_els->fp = fp;
  504. INIT_WORK(&unsol_els->unsol_els_work, bnx2fc_unsol_els_work);
  505. queue_work(bnx2fc_wq, &unsol_els->unsol_els_work);
  506. } else {
  507. BNX2FC_HBA_DBG(lport, "fh_r_ctl = 0x%x\n", fh->fh_r_ctl);
  508. kfree_skb(skb);
  509. kfree(unsol_els);
  510. }
  511. }
  512. static void bnx2fc_process_unsol_compl(struct bnx2fc_rport *tgt, u16 wqe)
  513. {
  514. u8 num_rq;
  515. struct fcoe_err_report_entry *err_entry;
  516. unsigned char *rq_data;
  517. unsigned char *buf = NULL, *buf1;
  518. int i;
  519. u16 xid;
  520. u32 frame_len, len;
  521. struct bnx2fc_cmd *io_req = NULL;
  522. struct fcoe_task_ctx_entry *task, *task_page;
  523. struct bnx2fc_interface *interface = tgt->port->priv;
  524. struct bnx2fc_hba *hba = interface->hba;
  525. int task_idx, index;
  526. int rc = 0;
  527. u64 err_warn_bit_map;
  528. u8 err_warn = 0xff;
  529. BNX2FC_TGT_DBG(tgt, "Entered UNSOL COMPLETION wqe = 0x%x\n", wqe);
  530. switch (wqe & FCOE_UNSOLICITED_CQE_SUBTYPE) {
  531. case FCOE_UNSOLICITED_FRAME_CQE_TYPE:
  532. frame_len = (wqe & FCOE_UNSOLICITED_CQE_PKT_LEN) >>
  533. FCOE_UNSOLICITED_CQE_PKT_LEN_SHIFT;
  534. num_rq = (frame_len + BNX2FC_RQ_BUF_SZ - 1) / BNX2FC_RQ_BUF_SZ;
  535. spin_lock_bh(&tgt->tgt_lock);
  536. rq_data = (unsigned char *)bnx2fc_get_next_rqe(tgt, num_rq);
  537. spin_unlock_bh(&tgt->tgt_lock);
  538. if (rq_data) {
  539. buf = rq_data;
  540. } else {
  541. buf1 = buf = kmalloc((num_rq * BNX2FC_RQ_BUF_SZ),
  542. GFP_ATOMIC);
  543. if (!buf1) {
  544. BNX2FC_TGT_DBG(tgt, "Memory alloc failure\n");
  545. break;
  546. }
  547. for (i = 0; i < num_rq; i++) {
  548. spin_lock_bh(&tgt->tgt_lock);
  549. rq_data = (unsigned char *)
  550. bnx2fc_get_next_rqe(tgt, 1);
  551. spin_unlock_bh(&tgt->tgt_lock);
  552. len = BNX2FC_RQ_BUF_SZ;
  553. memcpy(buf1, rq_data, len);
  554. buf1 += len;
  555. }
  556. }
  557. bnx2fc_process_l2_frame_compl(tgt, buf, frame_len,
  558. FC_XID_UNKNOWN);
  559. if (buf != rq_data)
  560. kfree(buf);
  561. spin_lock_bh(&tgt->tgt_lock);
  562. bnx2fc_return_rqe(tgt, num_rq);
  563. spin_unlock_bh(&tgt->tgt_lock);
  564. break;
  565. case FCOE_ERROR_DETECTION_CQE_TYPE:
  566. /*
  567. * In case of error reporting CQE a single RQ entry
  568. * is consumed.
  569. */
  570. spin_lock_bh(&tgt->tgt_lock);
  571. num_rq = 1;
  572. err_entry = (struct fcoe_err_report_entry *)
  573. bnx2fc_get_next_rqe(tgt, 1);
  574. xid = err_entry->fc_hdr.ox_id;
  575. BNX2FC_TGT_DBG(tgt, "Unsol Error Frame OX_ID = 0x%x\n", xid);
  576. BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x\n",
  577. err_entry->data.err_warn_bitmap_hi,
  578. err_entry->data.err_warn_bitmap_lo);
  579. BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x\n",
  580. err_entry->data.tx_buf_off, err_entry->data.rx_buf_off);
  581. if (xid > hba->max_xid) {
  582. BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n",
  583. xid);
  584. goto ret_err_rqe;
  585. }
  586. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  587. index = xid % BNX2FC_TASKS_PER_PAGE;
  588. task_page = (struct fcoe_task_ctx_entry *)
  589. hba->task_ctx[task_idx];
  590. task = &(task_page[index]);
  591. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  592. if (!io_req)
  593. goto ret_err_rqe;
  594. if (io_req->cmd_type != BNX2FC_SCSI_CMD) {
  595. printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n");
  596. goto ret_err_rqe;
  597. }
  598. if (test_and_clear_bit(BNX2FC_FLAG_IO_CLEANUP,
  599. &io_req->req_flags)) {
  600. BNX2FC_IO_DBG(io_req, "unsol_err: cleanup in "
  601. "progress.. ignore unsol err\n");
  602. goto ret_err_rqe;
  603. }
  604. err_warn_bit_map = (u64)
  605. ((u64)err_entry->data.err_warn_bitmap_hi << 32) |
  606. (u64)err_entry->data.err_warn_bitmap_lo;
  607. for (i = 0; i < BNX2FC_NUM_ERR_BITS; i++) {
  608. if (err_warn_bit_map & (u64)((u64)1 << i)) {
  609. err_warn = i;
  610. break;
  611. }
  612. }
  613. /*
  614. * If ABTS is already in progress, and FW error is
  615. * received after that, do not cancel the timeout_work
  616. * and let the error recovery continue by explicitly
  617. * logging out the target, when the ABTS eventually
  618. * times out.
  619. */
  620. if (test_bit(BNX2FC_FLAG_ISSUE_ABTS, &io_req->req_flags)) {
  621. printk(KERN_ERR PFX "err_warn: io_req (0x%x) already "
  622. "in ABTS processing\n", xid);
  623. goto ret_err_rqe;
  624. }
  625. BNX2FC_TGT_DBG(tgt, "err = 0x%x\n", err_warn);
  626. if (tgt->dev_type != TYPE_TAPE)
  627. goto skip_rec;
  628. switch (err_warn) {
  629. case FCOE_ERROR_CODE_REC_TOV_TIMER_EXPIRATION:
  630. case FCOE_ERROR_CODE_DATA_OOO_RO:
  631. case FCOE_ERROR_CODE_COMMON_INCORRECT_SEQ_CNT:
  632. case FCOE_ERROR_CODE_DATA_SOFI3_SEQ_ACTIVE_SET:
  633. case FCOE_ERROR_CODE_FCP_RSP_OPENED_SEQ:
  634. case FCOE_ERROR_CODE_DATA_SOFN_SEQ_ACTIVE_RESET:
  635. BNX2FC_TGT_DBG(tgt, "REC TOV popped for xid - 0x%x\n",
  636. xid);
  637. memcpy(&io_req->err_entry, err_entry,
  638. sizeof(struct fcoe_err_report_entry));
  639. if (!test_bit(BNX2FC_FLAG_SRR_SENT,
  640. &io_req->req_flags)) {
  641. spin_unlock_bh(&tgt->tgt_lock);
  642. rc = bnx2fc_send_rec(io_req);
  643. spin_lock_bh(&tgt->tgt_lock);
  644. if (rc)
  645. goto skip_rec;
  646. } else
  647. printk(KERN_ERR PFX "SRR in progress\n");
  648. goto ret_err_rqe;
  649. break;
  650. default:
  651. break;
  652. }
  653. skip_rec:
  654. set_bit(BNX2FC_FLAG_ISSUE_ABTS, &io_req->req_flags);
  655. /*
  656. * Cancel the timeout_work, as we received IO
  657. * completion with FW error.
  658. */
  659. if (cancel_delayed_work(&io_req->timeout_work))
  660. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  661. rc = bnx2fc_initiate_abts(io_req);
  662. if (rc != SUCCESS) {
  663. printk(KERN_ERR PFX "err_warn: initiate_abts "
  664. "failed xid = 0x%x. issue cleanup\n",
  665. io_req->xid);
  666. bnx2fc_initiate_cleanup(io_req);
  667. }
  668. ret_err_rqe:
  669. bnx2fc_return_rqe(tgt, 1);
  670. spin_unlock_bh(&tgt->tgt_lock);
  671. break;
  672. case FCOE_WARNING_DETECTION_CQE_TYPE:
  673. /*
  674. *In case of warning reporting CQE a single RQ entry
  675. * is consumes.
  676. */
  677. spin_lock_bh(&tgt->tgt_lock);
  678. num_rq = 1;
  679. err_entry = (struct fcoe_err_report_entry *)
  680. bnx2fc_get_next_rqe(tgt, 1);
  681. xid = cpu_to_be16(err_entry->fc_hdr.ox_id);
  682. BNX2FC_TGT_DBG(tgt, "Unsol Warning Frame OX_ID = 0x%x\n", xid);
  683. BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x",
  684. err_entry->data.err_warn_bitmap_hi,
  685. err_entry->data.err_warn_bitmap_lo);
  686. BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x",
  687. err_entry->data.tx_buf_off, err_entry->data.rx_buf_off);
  688. if (xid > hba->max_xid) {
  689. BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n", xid);
  690. goto ret_warn_rqe;
  691. }
  692. err_warn_bit_map = (u64)
  693. ((u64)err_entry->data.err_warn_bitmap_hi << 32) |
  694. (u64)err_entry->data.err_warn_bitmap_lo;
  695. for (i = 0; i < BNX2FC_NUM_ERR_BITS; i++) {
  696. if (err_warn_bit_map & (u64) (1 << i)) {
  697. err_warn = i;
  698. break;
  699. }
  700. }
  701. BNX2FC_TGT_DBG(tgt, "warn = 0x%x\n", err_warn);
  702. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  703. index = xid % BNX2FC_TASKS_PER_PAGE;
  704. task_page = (struct fcoe_task_ctx_entry *)
  705. interface->hba->task_ctx[task_idx];
  706. task = &(task_page[index]);
  707. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  708. if (!io_req)
  709. goto ret_warn_rqe;
  710. if (io_req->cmd_type != BNX2FC_SCSI_CMD) {
  711. printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n");
  712. goto ret_warn_rqe;
  713. }
  714. memcpy(&io_req->err_entry, err_entry,
  715. sizeof(struct fcoe_err_report_entry));
  716. if (err_warn == FCOE_ERROR_CODE_REC_TOV_TIMER_EXPIRATION)
  717. /* REC_TOV is not a warning code */
  718. BUG_ON(1);
  719. else
  720. BNX2FC_TGT_DBG(tgt, "Unsolicited warning\n");
  721. ret_warn_rqe:
  722. bnx2fc_return_rqe(tgt, 1);
  723. spin_unlock_bh(&tgt->tgt_lock);
  724. break;
  725. default:
  726. printk(KERN_ERR PFX "Unsol Compl: Invalid CQE Subtype\n");
  727. break;
  728. }
  729. }
  730. void bnx2fc_process_cq_compl(struct bnx2fc_rport *tgt, u16 wqe)
  731. {
  732. struct fcoe_task_ctx_entry *task;
  733. struct fcoe_task_ctx_entry *task_page;
  734. struct fcoe_port *port = tgt->port;
  735. struct bnx2fc_interface *interface = port->priv;
  736. struct bnx2fc_hba *hba = interface->hba;
  737. struct bnx2fc_cmd *io_req;
  738. int task_idx, index;
  739. u16 xid;
  740. u8 cmd_type;
  741. u8 rx_state = 0;
  742. u8 num_rq;
  743. spin_lock_bh(&tgt->tgt_lock);
  744. xid = wqe & FCOE_PEND_WQ_CQE_TASK_ID;
  745. if (xid >= hba->max_tasks) {
  746. printk(KERN_ERR PFX "ERROR:xid out of range\n");
  747. spin_unlock_bh(&tgt->tgt_lock);
  748. return;
  749. }
  750. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  751. index = xid % BNX2FC_TASKS_PER_PAGE;
  752. task_page = (struct fcoe_task_ctx_entry *)hba->task_ctx[task_idx];
  753. task = &(task_page[index]);
  754. num_rq = ((task->rxwr_txrd.var_ctx.rx_flags &
  755. FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE) >>
  756. FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT);
  757. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  758. if (io_req == NULL) {
  759. printk(KERN_ERR PFX "ERROR? cq_compl - io_req is NULL\n");
  760. spin_unlock_bh(&tgt->tgt_lock);
  761. return;
  762. }
  763. /* Timestamp IO completion time */
  764. cmd_type = io_req->cmd_type;
  765. rx_state = ((task->rxwr_txrd.var_ctx.rx_flags &
  766. FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE) >>
  767. FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT);
  768. /* Process other IO completion types */
  769. switch (cmd_type) {
  770. case BNX2FC_SCSI_CMD:
  771. if (rx_state == FCOE_TASK_RX_STATE_COMPLETED) {
  772. bnx2fc_process_scsi_cmd_compl(io_req, task, num_rq);
  773. spin_unlock_bh(&tgt->tgt_lock);
  774. return;
  775. }
  776. if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
  777. bnx2fc_process_abts_compl(io_req, task, num_rq);
  778. else if (rx_state ==
  779. FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
  780. bnx2fc_process_cleanup_compl(io_req, task, num_rq);
  781. else
  782. printk(KERN_ERR PFX "Invalid rx state - %d\n",
  783. rx_state);
  784. break;
  785. case BNX2FC_TASK_MGMT_CMD:
  786. BNX2FC_IO_DBG(io_req, "Processing TM complete\n");
  787. bnx2fc_process_tm_compl(io_req, task, num_rq);
  788. break;
  789. case BNX2FC_ABTS:
  790. /*
  791. * ABTS request received by firmware. ABTS response
  792. * will be delivered to the task belonging to the IO
  793. * that was aborted
  794. */
  795. BNX2FC_IO_DBG(io_req, "cq_compl- ABTS sent out by fw\n");
  796. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  797. break;
  798. case BNX2FC_ELS:
  799. if (rx_state == FCOE_TASK_RX_STATE_COMPLETED)
  800. bnx2fc_process_els_compl(io_req, task, num_rq);
  801. else if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
  802. bnx2fc_process_abts_compl(io_req, task, num_rq);
  803. else if (rx_state ==
  804. FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
  805. bnx2fc_process_cleanup_compl(io_req, task, num_rq);
  806. else
  807. printk(KERN_ERR PFX "Invalid rx state = %d\n",
  808. rx_state);
  809. break;
  810. case BNX2FC_CLEANUP:
  811. BNX2FC_IO_DBG(io_req, "cq_compl- cleanup resp rcvd\n");
  812. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  813. break;
  814. case BNX2FC_SEQ_CLEANUP:
  815. BNX2FC_IO_DBG(io_req, "cq_compl(0x%x) - seq cleanup resp\n",
  816. io_req->xid);
  817. bnx2fc_process_seq_cleanup_compl(io_req, task, rx_state);
  818. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  819. break;
  820. default:
  821. printk(KERN_ERR PFX "Invalid cmd_type %d\n", cmd_type);
  822. break;
  823. }
  824. spin_unlock_bh(&tgt->tgt_lock);
  825. }
  826. void bnx2fc_arm_cq(struct bnx2fc_rport *tgt)
  827. {
  828. struct b577xx_fcoe_rx_doorbell *rx_db = &tgt->rx_db;
  829. u32 msg;
  830. wmb();
  831. rx_db->doorbell_cq_cons = tgt->cq_cons_idx | (tgt->cq_curr_toggle_bit <<
  832. FCOE_CQE_TOGGLE_BIT_SHIFT);
  833. msg = *((u32 *)rx_db);
  834. writel(cpu_to_le32(msg), tgt->ctx_base);
  835. mmiowb();
  836. }
  837. struct bnx2fc_work *bnx2fc_alloc_work(struct bnx2fc_rport *tgt, u16 wqe)
  838. {
  839. struct bnx2fc_work *work;
  840. work = kzalloc(sizeof(struct bnx2fc_work), GFP_ATOMIC);
  841. if (!work)
  842. return NULL;
  843. INIT_LIST_HEAD(&work->list);
  844. work->tgt = tgt;
  845. work->wqe = wqe;
  846. return work;
  847. }
  848. int bnx2fc_process_new_cqes(struct bnx2fc_rport *tgt)
  849. {
  850. struct fcoe_cqe *cq;
  851. u32 cq_cons;
  852. struct fcoe_cqe *cqe;
  853. u32 num_free_sqes = 0;
  854. u32 num_cqes = 0;
  855. u16 wqe;
  856. /*
  857. * cq_lock is a low contention lock used to protect
  858. * the CQ data structure from being freed up during
  859. * the upload operation
  860. */
  861. spin_lock_bh(&tgt->cq_lock);
  862. if (!tgt->cq) {
  863. printk(KERN_ERR PFX "process_new_cqes: cq is NULL\n");
  864. spin_unlock_bh(&tgt->cq_lock);
  865. return 0;
  866. }
  867. cq = tgt->cq;
  868. cq_cons = tgt->cq_cons_idx;
  869. cqe = &cq[cq_cons];
  870. while (((wqe = cqe->wqe) & FCOE_CQE_TOGGLE_BIT) ==
  871. (tgt->cq_curr_toggle_bit <<
  872. FCOE_CQE_TOGGLE_BIT_SHIFT)) {
  873. /* new entry on the cq */
  874. if (wqe & FCOE_CQE_CQE_TYPE) {
  875. /* Unsolicited event notification */
  876. bnx2fc_process_unsol_compl(tgt, wqe);
  877. } else {
  878. /* Pending work request completion */
  879. struct bnx2fc_work *work = NULL;
  880. struct bnx2fc_percpu_s *fps = NULL;
  881. unsigned int cpu = wqe % num_possible_cpus();
  882. fps = &per_cpu(bnx2fc_percpu, cpu);
  883. spin_lock_bh(&fps->fp_work_lock);
  884. if (unlikely(!fps->iothread))
  885. goto unlock;
  886. work = bnx2fc_alloc_work(tgt, wqe);
  887. if (work)
  888. list_add_tail(&work->list,
  889. &fps->work_list);
  890. unlock:
  891. spin_unlock_bh(&fps->fp_work_lock);
  892. /* Pending work request completion */
  893. if (fps->iothread && work)
  894. wake_up_process(fps->iothread);
  895. else
  896. bnx2fc_process_cq_compl(tgt, wqe);
  897. num_free_sqes++;
  898. }
  899. cqe++;
  900. tgt->cq_cons_idx++;
  901. num_cqes++;
  902. if (tgt->cq_cons_idx == BNX2FC_CQ_WQES_MAX) {
  903. tgt->cq_cons_idx = 0;
  904. cqe = cq;
  905. tgt->cq_curr_toggle_bit =
  906. 1 - tgt->cq_curr_toggle_bit;
  907. }
  908. }
  909. if (num_cqes) {
  910. /* Arm CQ only if doorbell is mapped */
  911. if (tgt->ctx_base)
  912. bnx2fc_arm_cq(tgt);
  913. atomic_add(num_free_sqes, &tgt->free_sqes);
  914. }
  915. spin_unlock_bh(&tgt->cq_lock);
  916. return 0;
  917. }
  918. /**
  919. * bnx2fc_fastpath_notification - process global event queue (KCQ)
  920. *
  921. * @hba: adapter structure pointer
  922. * @new_cqe_kcqe: pointer to newly DMA'd KCQ entry
  923. *
  924. * Fast path event notification handler
  925. */
  926. static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
  927. struct fcoe_kcqe *new_cqe_kcqe)
  928. {
  929. u32 conn_id = new_cqe_kcqe->fcoe_conn_id;
  930. struct bnx2fc_rport *tgt = hba->tgt_ofld_list[conn_id];
  931. if (!tgt) {
  932. printk(KERN_ERR PFX "conn_id 0x%x not valid\n", conn_id);
  933. return;
  934. }
  935. bnx2fc_process_new_cqes(tgt);
  936. }
  937. /**
  938. * bnx2fc_process_ofld_cmpl - process FCoE session offload completion
  939. *
  940. * @hba: adapter structure pointer
  941. * @ofld_kcqe: connection offload kcqe pointer
  942. *
  943. * handle session offload completion, enable the session if offload is
  944. * successful.
  945. */
  946. static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
  947. struct fcoe_kcqe *ofld_kcqe)
  948. {
  949. struct bnx2fc_rport *tgt;
  950. struct fcoe_port *port;
  951. struct bnx2fc_interface *interface;
  952. u32 conn_id;
  953. u32 context_id;
  954. conn_id = ofld_kcqe->fcoe_conn_id;
  955. context_id = ofld_kcqe->fcoe_conn_context_id;
  956. tgt = hba->tgt_ofld_list[conn_id];
  957. if (!tgt) {
  958. printk(KERN_ALERT PFX "ERROR:ofld_cmpl: No pending ofld req\n");
  959. return;
  960. }
  961. BNX2FC_TGT_DBG(tgt, "Entered ofld compl - context_id = 0x%x\n",
  962. ofld_kcqe->fcoe_conn_context_id);
  963. port = tgt->port;
  964. interface = tgt->port->priv;
  965. if (hba != interface->hba) {
  966. printk(KERN_ERR PFX "ERROR:ofld_cmpl: HBA mis-match\n");
  967. goto ofld_cmpl_err;
  968. }
  969. /*
  970. * cnic has allocated a context_id for this session; use this
  971. * while enabling the session.
  972. */
  973. tgt->context_id = context_id;
  974. if (ofld_kcqe->completion_status) {
  975. if (ofld_kcqe->completion_status ==
  976. FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE) {
  977. printk(KERN_ERR PFX "unable to allocate FCoE context "
  978. "resources\n");
  979. set_bit(BNX2FC_FLAG_CTX_ALLOC_FAILURE, &tgt->flags);
  980. }
  981. } else {
  982. /* FW offload request successfully completed */
  983. set_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
  984. }
  985. ofld_cmpl_err:
  986. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  987. wake_up_interruptible(&tgt->ofld_wait);
  988. }
  989. /**
  990. * bnx2fc_process_enable_conn_cmpl - process FCoE session enable completion
  991. *
  992. * @hba: adapter structure pointer
  993. * @ofld_kcqe: connection offload kcqe pointer
  994. *
  995. * handle session enable completion, mark the rport as ready
  996. */
  997. static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
  998. struct fcoe_kcqe *ofld_kcqe)
  999. {
  1000. struct bnx2fc_rport *tgt;
  1001. struct bnx2fc_interface *interface;
  1002. u32 conn_id;
  1003. u32 context_id;
  1004. context_id = ofld_kcqe->fcoe_conn_context_id;
  1005. conn_id = ofld_kcqe->fcoe_conn_id;
  1006. tgt = hba->tgt_ofld_list[conn_id];
  1007. if (!tgt) {
  1008. printk(KERN_ERR PFX "ERROR:enbl_cmpl: No pending ofld req\n");
  1009. return;
  1010. }
  1011. BNX2FC_TGT_DBG(tgt, "Enable compl - context_id = 0x%x\n",
  1012. ofld_kcqe->fcoe_conn_context_id);
  1013. /*
  1014. * context_id should be the same for this target during offload
  1015. * and enable
  1016. */
  1017. if (tgt->context_id != context_id) {
  1018. printk(KERN_ERR PFX "context id mis-match\n");
  1019. return;
  1020. }
  1021. interface = tgt->port->priv;
  1022. if (hba != interface->hba) {
  1023. printk(KERN_ERR PFX "bnx2fc-enbl_cmpl: HBA mis-match\n");
  1024. goto enbl_cmpl_err;
  1025. }
  1026. if (!ofld_kcqe->completion_status)
  1027. /* enable successful - rport ready for issuing IOs */
  1028. set_bit(BNX2FC_FLAG_ENABLED, &tgt->flags);
  1029. enbl_cmpl_err:
  1030. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  1031. wake_up_interruptible(&tgt->ofld_wait);
  1032. }
  1033. static void bnx2fc_process_conn_disable_cmpl(struct bnx2fc_hba *hba,
  1034. struct fcoe_kcqe *disable_kcqe)
  1035. {
  1036. struct bnx2fc_rport *tgt;
  1037. u32 conn_id;
  1038. conn_id = disable_kcqe->fcoe_conn_id;
  1039. tgt = hba->tgt_ofld_list[conn_id];
  1040. if (!tgt) {
  1041. printk(KERN_ERR PFX "ERROR: disable_cmpl: No disable req\n");
  1042. return;
  1043. }
  1044. BNX2FC_TGT_DBG(tgt, PFX "disable_cmpl: conn_id %d\n", conn_id);
  1045. if (disable_kcqe->completion_status) {
  1046. printk(KERN_ERR PFX "Disable failed with cmpl status %d\n",
  1047. disable_kcqe->completion_status);
  1048. set_bit(BNX2FC_FLAG_DISABLE_FAILED, &tgt->flags);
  1049. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  1050. wake_up_interruptible(&tgt->upld_wait);
  1051. } else {
  1052. /* disable successful */
  1053. BNX2FC_TGT_DBG(tgt, "disable successful\n");
  1054. clear_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
  1055. clear_bit(BNX2FC_FLAG_ENABLED, &tgt->flags);
  1056. set_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
  1057. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  1058. wake_up_interruptible(&tgt->upld_wait);
  1059. }
  1060. }
  1061. static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
  1062. struct fcoe_kcqe *destroy_kcqe)
  1063. {
  1064. struct bnx2fc_rport *tgt;
  1065. u32 conn_id;
  1066. conn_id = destroy_kcqe->fcoe_conn_id;
  1067. tgt = hba->tgt_ofld_list[conn_id];
  1068. if (!tgt) {
  1069. printk(KERN_ERR PFX "destroy_cmpl: No destroy req\n");
  1070. return;
  1071. }
  1072. BNX2FC_TGT_DBG(tgt, "destroy_cmpl: conn_id %d\n", conn_id);
  1073. if (destroy_kcqe->completion_status) {
  1074. printk(KERN_ERR PFX "Destroy conn failed, cmpl status %d\n",
  1075. destroy_kcqe->completion_status);
  1076. return;
  1077. } else {
  1078. /* destroy successful */
  1079. BNX2FC_TGT_DBG(tgt, "upload successful\n");
  1080. clear_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
  1081. set_bit(BNX2FC_FLAG_DESTROYED, &tgt->flags);
  1082. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  1083. wake_up_interruptible(&tgt->upld_wait);
  1084. }
  1085. }
  1086. static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code)
  1087. {
  1088. switch (err_code) {
  1089. case FCOE_KCQE_COMPLETION_STATUS_INVALID_OPCODE:
  1090. printk(KERN_ERR PFX "init_failure due to invalid opcode\n");
  1091. break;
  1092. case FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE:
  1093. printk(KERN_ERR PFX "init failed due to ctx alloc failure\n");
  1094. break;
  1095. case FCOE_KCQE_COMPLETION_STATUS_NIC_ERROR:
  1096. printk(KERN_ERR PFX "init_failure due to NIC error\n");
  1097. break;
  1098. case FCOE_KCQE_COMPLETION_STATUS_ERROR:
  1099. printk(KERN_ERR PFX "init failure due to compl status err\n");
  1100. break;
  1101. case FCOE_KCQE_COMPLETION_STATUS_WRONG_HSI_VERSION:
  1102. printk(KERN_ERR PFX "init failure due to HSI mismatch\n");
  1103. break;
  1104. default:
  1105. printk(KERN_ERR PFX "Unknown Error code %d\n", err_code);
  1106. }
  1107. }
  1108. /**
  1109. * bnx2fc_indicae_kcqe - process KCQE
  1110. *
  1111. * @hba: adapter structure pointer
  1112. * @kcqe: kcqe pointer
  1113. * @num_cqe: Number of completion queue elements
  1114. *
  1115. * Generic KCQ event handler
  1116. */
  1117. void bnx2fc_indicate_kcqe(void *context, struct kcqe *kcq[],
  1118. u32 num_cqe)
  1119. {
  1120. struct bnx2fc_hba *hba = (struct bnx2fc_hba *)context;
  1121. int i = 0;
  1122. struct fcoe_kcqe *kcqe = NULL;
  1123. while (i < num_cqe) {
  1124. kcqe = (struct fcoe_kcqe *) kcq[i++];
  1125. switch (kcqe->op_code) {
  1126. case FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION:
  1127. bnx2fc_fastpath_notification(hba, kcqe);
  1128. break;
  1129. case FCOE_KCQE_OPCODE_OFFLOAD_CONN:
  1130. bnx2fc_process_ofld_cmpl(hba, kcqe);
  1131. break;
  1132. case FCOE_KCQE_OPCODE_ENABLE_CONN:
  1133. bnx2fc_process_enable_conn_cmpl(hba, kcqe);
  1134. break;
  1135. case FCOE_KCQE_OPCODE_INIT_FUNC:
  1136. if (kcqe->completion_status !=
  1137. FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
  1138. bnx2fc_init_failure(hba,
  1139. kcqe->completion_status);
  1140. } else {
  1141. set_bit(ADAPTER_STATE_UP, &hba->adapter_state);
  1142. bnx2fc_get_link_state(hba);
  1143. printk(KERN_INFO PFX "[%.2x]: FCOE_INIT passed\n",
  1144. (u8)hba->pcidev->bus->number);
  1145. }
  1146. break;
  1147. case FCOE_KCQE_OPCODE_DESTROY_FUNC:
  1148. if (kcqe->completion_status !=
  1149. FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
  1150. printk(KERN_ERR PFX "DESTROY failed\n");
  1151. } else {
  1152. printk(KERN_ERR PFX "DESTROY success\n");
  1153. }
  1154. set_bit(BNX2FC_FLAG_DESTROY_CMPL, &hba->flags);
  1155. wake_up_interruptible(&hba->destroy_wait);
  1156. break;
  1157. case FCOE_KCQE_OPCODE_DISABLE_CONN:
  1158. bnx2fc_process_conn_disable_cmpl(hba, kcqe);
  1159. break;
  1160. case FCOE_KCQE_OPCODE_DESTROY_CONN:
  1161. bnx2fc_process_conn_destroy_cmpl(hba, kcqe);
  1162. break;
  1163. case FCOE_KCQE_OPCODE_STAT_FUNC:
  1164. if (kcqe->completion_status !=
  1165. FCOE_KCQE_COMPLETION_STATUS_SUCCESS)
  1166. printk(KERN_ERR PFX "STAT failed\n");
  1167. complete(&hba->stat_req_done);
  1168. break;
  1169. case FCOE_KCQE_OPCODE_FCOE_ERROR:
  1170. /* fall thru */
  1171. default:
  1172. printk(KERN_ERR PFX "unknown opcode 0x%x\n",
  1173. kcqe->op_code);
  1174. }
  1175. }
  1176. }
  1177. void bnx2fc_add_2_sq(struct bnx2fc_rport *tgt, u16 xid)
  1178. {
  1179. struct fcoe_sqe *sqe;
  1180. sqe = &tgt->sq[tgt->sq_prod_idx];
  1181. /* Fill SQ WQE */
  1182. sqe->wqe = xid << FCOE_SQE_TASK_ID_SHIFT;
  1183. sqe->wqe |= tgt->sq_curr_toggle_bit << FCOE_SQE_TOGGLE_BIT_SHIFT;
  1184. /* Advance SQ Prod Idx */
  1185. if (++tgt->sq_prod_idx == BNX2FC_SQ_WQES_MAX) {
  1186. tgt->sq_prod_idx = 0;
  1187. tgt->sq_curr_toggle_bit = 1 - tgt->sq_curr_toggle_bit;
  1188. }
  1189. }
  1190. void bnx2fc_ring_doorbell(struct bnx2fc_rport *tgt)
  1191. {
  1192. struct b577xx_doorbell_set_prod *sq_db = &tgt->sq_db;
  1193. u32 msg;
  1194. wmb();
  1195. sq_db->prod = tgt->sq_prod_idx |
  1196. (tgt->sq_curr_toggle_bit << 15);
  1197. msg = *((u32 *)sq_db);
  1198. writel(cpu_to_le32(msg), tgt->ctx_base);
  1199. mmiowb();
  1200. }
  1201. int bnx2fc_map_doorbell(struct bnx2fc_rport *tgt)
  1202. {
  1203. u32 context_id = tgt->context_id;
  1204. struct fcoe_port *port = tgt->port;
  1205. u32 reg_off;
  1206. resource_size_t reg_base;
  1207. struct bnx2fc_interface *interface = port->priv;
  1208. struct bnx2fc_hba *hba = interface->hba;
  1209. reg_base = pci_resource_start(hba->pcidev,
  1210. BNX2X_DOORBELL_PCI_BAR);
  1211. reg_off = BNX2FC_5771X_DB_PAGE_SIZE *
  1212. (context_id & 0x1FFFF) + DPM_TRIGER_TYPE;
  1213. tgt->ctx_base = ioremap_nocache(reg_base + reg_off, 4);
  1214. if (!tgt->ctx_base)
  1215. return -ENOMEM;
  1216. return 0;
  1217. }
  1218. char *bnx2fc_get_next_rqe(struct bnx2fc_rport *tgt, u8 num_items)
  1219. {
  1220. char *buf = (char *)tgt->rq + (tgt->rq_cons_idx * BNX2FC_RQ_BUF_SZ);
  1221. if (tgt->rq_cons_idx + num_items > BNX2FC_RQ_WQES_MAX)
  1222. return NULL;
  1223. tgt->rq_cons_idx += num_items;
  1224. if (tgt->rq_cons_idx >= BNX2FC_RQ_WQES_MAX)
  1225. tgt->rq_cons_idx -= BNX2FC_RQ_WQES_MAX;
  1226. return buf;
  1227. }
  1228. void bnx2fc_return_rqe(struct bnx2fc_rport *tgt, u8 num_items)
  1229. {
  1230. /* return the rq buffer */
  1231. u32 next_prod_idx = tgt->rq_prod_idx + num_items;
  1232. if ((next_prod_idx & 0x7fff) == BNX2FC_RQ_WQES_MAX) {
  1233. /* Wrap around RQ */
  1234. next_prod_idx += 0x8000 - BNX2FC_RQ_WQES_MAX;
  1235. }
  1236. tgt->rq_prod_idx = next_prod_idx;
  1237. tgt->conn_db->rq_prod = tgt->rq_prod_idx;
  1238. }
  1239. void bnx2fc_init_seq_cleanup_task(struct bnx2fc_cmd *seq_clnp_req,
  1240. struct fcoe_task_ctx_entry *task,
  1241. struct bnx2fc_cmd *orig_io_req,
  1242. u32 offset)
  1243. {
  1244. struct scsi_cmnd *sc_cmd = orig_io_req->sc_cmd;
  1245. struct bnx2fc_rport *tgt = seq_clnp_req->tgt;
  1246. struct bnx2fc_interface *interface = tgt->port->priv;
  1247. struct fcoe_bd_ctx *bd = orig_io_req->bd_tbl->bd_tbl;
  1248. struct fcoe_task_ctx_entry *orig_task;
  1249. struct fcoe_task_ctx_entry *task_page;
  1250. struct fcoe_ext_mul_sges_ctx *sgl;
  1251. u8 task_type = FCOE_TASK_TYPE_SEQUENCE_CLEANUP;
  1252. u8 orig_task_type;
  1253. u16 orig_xid = orig_io_req->xid;
  1254. u32 context_id = tgt->context_id;
  1255. u64 phys_addr = (u64)orig_io_req->bd_tbl->bd_tbl_dma;
  1256. u32 orig_offset = offset;
  1257. int bd_count;
  1258. int orig_task_idx, index;
  1259. int i;
  1260. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1261. if (sc_cmd->sc_data_direction == DMA_TO_DEVICE)
  1262. orig_task_type = FCOE_TASK_TYPE_WRITE;
  1263. else
  1264. orig_task_type = FCOE_TASK_TYPE_READ;
  1265. /* Tx flags */
  1266. task->txwr_rxrd.const_ctx.tx_flags =
  1267. FCOE_TASK_TX_STATE_SEQUENCE_CLEANUP <<
  1268. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1269. /* init flags */
  1270. task->txwr_rxrd.const_ctx.init_flags = task_type <<
  1271. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1272. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1273. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1274. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1275. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1276. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1277. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1278. task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid;
  1279. task->txwr_rxrd.union_ctx.cleanup.ctx.rolled_tx_seq_cnt = 0;
  1280. task->txwr_rxrd.union_ctx.cleanup.ctx.rolled_tx_data_offset = offset;
  1281. bd_count = orig_io_req->bd_tbl->bd_valid;
  1282. /* obtain the appropriate bd entry from relative offset */
  1283. for (i = 0; i < bd_count; i++) {
  1284. if (offset < bd[i].buf_len)
  1285. break;
  1286. offset -= bd[i].buf_len;
  1287. }
  1288. phys_addr += (i * sizeof(struct fcoe_bd_ctx));
  1289. if (orig_task_type == FCOE_TASK_TYPE_WRITE) {
  1290. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
  1291. (u32)phys_addr;
  1292. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
  1293. (u32)((u64)phys_addr >> 32);
  1294. task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size =
  1295. bd_count;
  1296. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_off =
  1297. offset; /* adjusted offset */
  1298. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_idx = i;
  1299. } else {
  1300. orig_task_idx = orig_xid / BNX2FC_TASKS_PER_PAGE;
  1301. index = orig_xid % BNX2FC_TASKS_PER_PAGE;
  1302. task_page = (struct fcoe_task_ctx_entry *)
  1303. interface->hba->task_ctx[orig_task_idx];
  1304. orig_task = &(task_page[index]);
  1305. /* Multiple SGEs were used for this IO */
  1306. sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
  1307. sgl->mul_sgl.cur_sge_addr.lo = (u32)phys_addr;
  1308. sgl->mul_sgl.cur_sge_addr.hi = (u32)((u64)phys_addr >> 32);
  1309. sgl->mul_sgl.sgl_size = bd_count;
  1310. sgl->mul_sgl.cur_sge_off = offset; /*adjusted offset */
  1311. sgl->mul_sgl.cur_sge_idx = i;
  1312. memset(&task->rxwr_only.rx_seq_ctx, 0,
  1313. sizeof(struct fcoe_rx_seq_ctx));
  1314. task->rxwr_only.rx_seq_ctx.low_exp_ro = orig_offset;
  1315. task->rxwr_only.rx_seq_ctx.high_exp_ro = orig_offset;
  1316. }
  1317. }
  1318. void bnx2fc_init_cleanup_task(struct bnx2fc_cmd *io_req,
  1319. struct fcoe_task_ctx_entry *task,
  1320. u16 orig_xid)
  1321. {
  1322. u8 task_type = FCOE_TASK_TYPE_EXCHANGE_CLEANUP;
  1323. struct bnx2fc_rport *tgt = io_req->tgt;
  1324. u32 context_id = tgt->context_id;
  1325. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1326. /* Tx Write Rx Read */
  1327. /* init flags */
  1328. task->txwr_rxrd.const_ctx.init_flags = task_type <<
  1329. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1330. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1331. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1332. if (tgt->dev_type == TYPE_TAPE)
  1333. task->txwr_rxrd.const_ctx.init_flags |=
  1334. FCOE_TASK_DEV_TYPE_TAPE <<
  1335. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1336. else
  1337. task->txwr_rxrd.const_ctx.init_flags |=
  1338. FCOE_TASK_DEV_TYPE_DISK <<
  1339. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1340. task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid;
  1341. /* Tx flags */
  1342. task->txwr_rxrd.const_ctx.tx_flags =
  1343. FCOE_TASK_TX_STATE_EXCHANGE_CLEANUP <<
  1344. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1345. /* Rx Read Tx Write */
  1346. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1347. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1348. task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
  1349. FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
  1350. }
  1351. void bnx2fc_init_mp_task(struct bnx2fc_cmd *io_req,
  1352. struct fcoe_task_ctx_entry *task)
  1353. {
  1354. struct bnx2fc_mp_req *mp_req = &(io_req->mp_req);
  1355. struct bnx2fc_rport *tgt = io_req->tgt;
  1356. struct fc_frame_header *fc_hdr;
  1357. struct fcoe_ext_mul_sges_ctx *sgl;
  1358. u8 task_type = 0;
  1359. u64 *hdr;
  1360. u64 temp_hdr[3];
  1361. u32 context_id;
  1362. /* Obtain task_type */
  1363. if ((io_req->cmd_type == BNX2FC_TASK_MGMT_CMD) ||
  1364. (io_req->cmd_type == BNX2FC_ELS)) {
  1365. task_type = FCOE_TASK_TYPE_MIDPATH;
  1366. } else if (io_req->cmd_type == BNX2FC_ABTS) {
  1367. task_type = FCOE_TASK_TYPE_ABTS;
  1368. }
  1369. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1370. /* Setup the task from io_req for easy reference */
  1371. io_req->task = task;
  1372. BNX2FC_IO_DBG(io_req, "Init MP task for cmd_type = %d task_type = %d\n",
  1373. io_req->cmd_type, task_type);
  1374. /* Tx only */
  1375. if ((task_type == FCOE_TASK_TYPE_MIDPATH) ||
  1376. (task_type == FCOE_TASK_TYPE_UNSOLICITED)) {
  1377. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
  1378. (u32)mp_req->mp_req_bd_dma;
  1379. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
  1380. (u32)((u64)mp_req->mp_req_bd_dma >> 32);
  1381. task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size = 1;
  1382. }
  1383. /* Tx Write Rx Read */
  1384. /* init flags */
  1385. task->txwr_rxrd.const_ctx.init_flags = task_type <<
  1386. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1387. if (tgt->dev_type == TYPE_TAPE)
  1388. task->txwr_rxrd.const_ctx.init_flags |=
  1389. FCOE_TASK_DEV_TYPE_TAPE <<
  1390. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1391. else
  1392. task->txwr_rxrd.const_ctx.init_flags |=
  1393. FCOE_TASK_DEV_TYPE_DISK <<
  1394. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1395. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1396. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1397. /* tx flags */
  1398. task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_INIT <<
  1399. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1400. /* Rx Write Tx Read */
  1401. task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len;
  1402. /* rx flags */
  1403. task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
  1404. FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
  1405. context_id = tgt->context_id;
  1406. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1407. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1408. fc_hdr = &(mp_req->req_fc_hdr);
  1409. if (task_type == FCOE_TASK_TYPE_MIDPATH) {
  1410. fc_hdr->fh_ox_id = cpu_to_be16(io_req->xid);
  1411. fc_hdr->fh_rx_id = htons(0xffff);
  1412. task->rxwr_txrd.var_ctx.rx_id = 0xffff;
  1413. } else if (task_type == FCOE_TASK_TYPE_UNSOLICITED) {
  1414. fc_hdr->fh_rx_id = cpu_to_be16(io_req->xid);
  1415. }
  1416. /* Fill FC Header into middle path buffer */
  1417. hdr = (u64 *) &task->txwr_rxrd.union_ctx.tx_frame.fc_hdr;
  1418. memcpy(temp_hdr, fc_hdr, sizeof(temp_hdr));
  1419. hdr[0] = cpu_to_be64(temp_hdr[0]);
  1420. hdr[1] = cpu_to_be64(temp_hdr[1]);
  1421. hdr[2] = cpu_to_be64(temp_hdr[2]);
  1422. /* Rx Only */
  1423. if (task_type == FCOE_TASK_TYPE_MIDPATH) {
  1424. sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
  1425. sgl->mul_sgl.cur_sge_addr.lo = (u32)mp_req->mp_resp_bd_dma;
  1426. sgl->mul_sgl.cur_sge_addr.hi =
  1427. (u32)((u64)mp_req->mp_resp_bd_dma >> 32);
  1428. sgl->mul_sgl.sgl_size = 1;
  1429. }
  1430. }
  1431. void bnx2fc_init_task(struct bnx2fc_cmd *io_req,
  1432. struct fcoe_task_ctx_entry *task)
  1433. {
  1434. u8 task_type;
  1435. struct scsi_cmnd *sc_cmd = io_req->sc_cmd;
  1436. struct io_bdt *bd_tbl = io_req->bd_tbl;
  1437. struct bnx2fc_rport *tgt = io_req->tgt;
  1438. struct fcoe_cached_sge_ctx *cached_sge;
  1439. struct fcoe_ext_mul_sges_ctx *sgl;
  1440. int dev_type = tgt->dev_type;
  1441. u64 *fcp_cmnd;
  1442. u64 tmp_fcp_cmnd[4];
  1443. u32 context_id;
  1444. int cnt, i;
  1445. int bd_count;
  1446. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1447. /* Setup the task from io_req for easy reference */
  1448. io_req->task = task;
  1449. if (sc_cmd->sc_data_direction == DMA_TO_DEVICE)
  1450. task_type = FCOE_TASK_TYPE_WRITE;
  1451. else
  1452. task_type = FCOE_TASK_TYPE_READ;
  1453. /* Tx only */
  1454. bd_count = bd_tbl->bd_valid;
  1455. cached_sge = &task->rxwr_only.union_ctx.read_info.sgl_ctx.cached_sge;
  1456. if (task_type == FCOE_TASK_TYPE_WRITE) {
  1457. if ((dev_type == TYPE_DISK) && (bd_count == 1)) {
  1458. struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
  1459. task->txwr_only.sgl_ctx.cached_sge.cur_buf_addr.lo =
  1460. cached_sge->cur_buf_addr.lo =
  1461. fcoe_bd_tbl->buf_addr_lo;
  1462. task->txwr_only.sgl_ctx.cached_sge.cur_buf_addr.hi =
  1463. cached_sge->cur_buf_addr.hi =
  1464. fcoe_bd_tbl->buf_addr_hi;
  1465. task->txwr_only.sgl_ctx.cached_sge.cur_buf_rem =
  1466. cached_sge->cur_buf_rem =
  1467. fcoe_bd_tbl->buf_len;
  1468. task->txwr_rxrd.const_ctx.init_flags |= 1 <<
  1469. FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
  1470. } else {
  1471. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
  1472. (u32)bd_tbl->bd_tbl_dma;
  1473. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
  1474. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1475. task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size =
  1476. bd_tbl->bd_valid;
  1477. }
  1478. }
  1479. /*Tx Write Rx Read */
  1480. /* Init state to NORMAL */
  1481. task->txwr_rxrd.const_ctx.init_flags |= task_type <<
  1482. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1483. if (dev_type == TYPE_TAPE) {
  1484. task->txwr_rxrd.const_ctx.init_flags |=
  1485. FCOE_TASK_DEV_TYPE_TAPE <<
  1486. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1487. io_req->rec_retry = 0;
  1488. io_req->rec_retry = 0;
  1489. } else
  1490. task->txwr_rxrd.const_ctx.init_flags |=
  1491. FCOE_TASK_DEV_TYPE_DISK <<
  1492. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1493. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1494. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1495. /* tx flags */
  1496. task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_NORMAL <<
  1497. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1498. /* Set initial seq counter */
  1499. task->txwr_rxrd.union_ctx.tx_seq.ctx.seq_cnt = 1;
  1500. /* Fill FCP_CMND IU */
  1501. fcp_cmnd = (u64 *)
  1502. task->txwr_rxrd.union_ctx.fcp_cmd.opaque;
  1503. bnx2fc_build_fcp_cmnd(io_req, (struct fcp_cmnd *)&tmp_fcp_cmnd);
  1504. /* swap fcp_cmnd */
  1505. cnt = sizeof(struct fcp_cmnd) / sizeof(u64);
  1506. for (i = 0; i < cnt; i++) {
  1507. *fcp_cmnd = cpu_to_be64(tmp_fcp_cmnd[i]);
  1508. fcp_cmnd++;
  1509. }
  1510. /* Rx Write Tx Read */
  1511. task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len;
  1512. context_id = tgt->context_id;
  1513. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1514. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1515. /* rx flags */
  1516. /* Set state to "waiting for the first packet" */
  1517. task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
  1518. FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
  1519. task->rxwr_txrd.var_ctx.rx_id = 0xffff;
  1520. /* Rx Only */
  1521. if (task_type != FCOE_TASK_TYPE_READ)
  1522. return;
  1523. sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
  1524. bd_count = bd_tbl->bd_valid;
  1525. if (dev_type == TYPE_DISK) {
  1526. if (bd_count == 1) {
  1527. struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
  1528. cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo;
  1529. cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi;
  1530. cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len;
  1531. task->txwr_rxrd.const_ctx.init_flags |= 1 <<
  1532. FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
  1533. } else if (bd_count == 2) {
  1534. struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
  1535. cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo;
  1536. cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi;
  1537. cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len;
  1538. fcoe_bd_tbl++;
  1539. cached_sge->second_buf_addr.lo =
  1540. fcoe_bd_tbl->buf_addr_lo;
  1541. cached_sge->second_buf_addr.hi =
  1542. fcoe_bd_tbl->buf_addr_hi;
  1543. cached_sge->second_buf_rem = fcoe_bd_tbl->buf_len;
  1544. task->txwr_rxrd.const_ctx.init_flags |= 1 <<
  1545. FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
  1546. } else {
  1547. sgl->mul_sgl.cur_sge_addr.lo = (u32)bd_tbl->bd_tbl_dma;
  1548. sgl->mul_sgl.cur_sge_addr.hi =
  1549. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1550. sgl->mul_sgl.sgl_size = bd_count;
  1551. }
  1552. } else {
  1553. sgl->mul_sgl.cur_sge_addr.lo = (u32)bd_tbl->bd_tbl_dma;
  1554. sgl->mul_sgl.cur_sge_addr.hi =
  1555. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1556. sgl->mul_sgl.sgl_size = bd_count;
  1557. }
  1558. }
  1559. /**
  1560. * bnx2fc_setup_task_ctx - allocate and map task context
  1561. *
  1562. * @hba: pointer to adapter structure
  1563. *
  1564. * allocate memory for task context, and associated BD table to be used
  1565. * by firmware
  1566. *
  1567. */
  1568. int bnx2fc_setup_task_ctx(struct bnx2fc_hba *hba)
  1569. {
  1570. int rc = 0;
  1571. struct regpair *task_ctx_bdt;
  1572. dma_addr_t addr;
  1573. int task_ctx_arr_sz;
  1574. int i;
  1575. /*
  1576. * Allocate task context bd table. A page size of bd table
  1577. * can map 256 buffers. Each buffer contains 32 task context
  1578. * entries. Hence the limit with one page is 8192 task context
  1579. * entries.
  1580. */
  1581. hba->task_ctx_bd_tbl = dma_alloc_coherent(&hba->pcidev->dev,
  1582. PAGE_SIZE,
  1583. &hba->task_ctx_bd_dma,
  1584. GFP_KERNEL);
  1585. if (!hba->task_ctx_bd_tbl) {
  1586. printk(KERN_ERR PFX "unable to allocate task context BDT\n");
  1587. rc = -1;
  1588. goto out;
  1589. }
  1590. memset(hba->task_ctx_bd_tbl, 0, PAGE_SIZE);
  1591. /*
  1592. * Allocate task_ctx which is an array of pointers pointing to
  1593. * a page containing 32 task contexts
  1594. */
  1595. task_ctx_arr_sz = (hba->max_tasks / BNX2FC_TASKS_PER_PAGE);
  1596. hba->task_ctx = kzalloc((task_ctx_arr_sz * sizeof(void *)),
  1597. GFP_KERNEL);
  1598. if (!hba->task_ctx) {
  1599. printk(KERN_ERR PFX "unable to allocate task context array\n");
  1600. rc = -1;
  1601. goto out1;
  1602. }
  1603. /*
  1604. * Allocate task_ctx_dma which is an array of dma addresses
  1605. */
  1606. hba->task_ctx_dma = kmalloc((task_ctx_arr_sz *
  1607. sizeof(dma_addr_t)), GFP_KERNEL);
  1608. if (!hba->task_ctx_dma) {
  1609. printk(KERN_ERR PFX "unable to alloc context mapping array\n");
  1610. rc = -1;
  1611. goto out2;
  1612. }
  1613. task_ctx_bdt = (struct regpair *)hba->task_ctx_bd_tbl;
  1614. for (i = 0; i < task_ctx_arr_sz; i++) {
  1615. hba->task_ctx[i] = dma_alloc_coherent(&hba->pcidev->dev,
  1616. PAGE_SIZE,
  1617. &hba->task_ctx_dma[i],
  1618. GFP_KERNEL);
  1619. if (!hba->task_ctx[i]) {
  1620. printk(KERN_ERR PFX "unable to alloc task context\n");
  1621. rc = -1;
  1622. goto out3;
  1623. }
  1624. memset(hba->task_ctx[i], 0, PAGE_SIZE);
  1625. addr = (u64)hba->task_ctx_dma[i];
  1626. task_ctx_bdt->hi = cpu_to_le32((u64)addr >> 32);
  1627. task_ctx_bdt->lo = cpu_to_le32((u32)addr);
  1628. task_ctx_bdt++;
  1629. }
  1630. return 0;
  1631. out3:
  1632. for (i = 0; i < task_ctx_arr_sz; i++) {
  1633. if (hba->task_ctx[i]) {
  1634. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1635. hba->task_ctx[i], hba->task_ctx_dma[i]);
  1636. hba->task_ctx[i] = NULL;
  1637. }
  1638. }
  1639. kfree(hba->task_ctx_dma);
  1640. hba->task_ctx_dma = NULL;
  1641. out2:
  1642. kfree(hba->task_ctx);
  1643. hba->task_ctx = NULL;
  1644. out1:
  1645. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1646. hba->task_ctx_bd_tbl, hba->task_ctx_bd_dma);
  1647. hba->task_ctx_bd_tbl = NULL;
  1648. out:
  1649. return rc;
  1650. }
  1651. void bnx2fc_free_task_ctx(struct bnx2fc_hba *hba)
  1652. {
  1653. int task_ctx_arr_sz;
  1654. int i;
  1655. if (hba->task_ctx_bd_tbl) {
  1656. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1657. hba->task_ctx_bd_tbl,
  1658. hba->task_ctx_bd_dma);
  1659. hba->task_ctx_bd_tbl = NULL;
  1660. }
  1661. task_ctx_arr_sz = (hba->max_tasks / BNX2FC_TASKS_PER_PAGE);
  1662. if (hba->task_ctx) {
  1663. for (i = 0; i < task_ctx_arr_sz; i++) {
  1664. if (hba->task_ctx[i]) {
  1665. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1666. hba->task_ctx[i],
  1667. hba->task_ctx_dma[i]);
  1668. hba->task_ctx[i] = NULL;
  1669. }
  1670. }
  1671. kfree(hba->task_ctx);
  1672. hba->task_ctx = NULL;
  1673. }
  1674. kfree(hba->task_ctx_dma);
  1675. hba->task_ctx_dma = NULL;
  1676. }
  1677. static void bnx2fc_free_hash_table(struct bnx2fc_hba *hba)
  1678. {
  1679. int i;
  1680. int segment_count;
  1681. int hash_table_size;
  1682. u32 *pbl;
  1683. segment_count = hba->hash_tbl_segment_count;
  1684. hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL *
  1685. sizeof(struct fcoe_hash_table_entry);
  1686. pbl = hba->hash_tbl_pbl;
  1687. for (i = 0; i < segment_count; ++i) {
  1688. dma_addr_t dma_address;
  1689. dma_address = le32_to_cpu(*pbl);
  1690. ++pbl;
  1691. dma_address += ((u64)le32_to_cpu(*pbl)) << 32;
  1692. ++pbl;
  1693. dma_free_coherent(&hba->pcidev->dev,
  1694. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1695. hba->hash_tbl_segments[i],
  1696. dma_address);
  1697. }
  1698. if (hba->hash_tbl_pbl) {
  1699. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1700. hba->hash_tbl_pbl,
  1701. hba->hash_tbl_pbl_dma);
  1702. hba->hash_tbl_pbl = NULL;
  1703. }
  1704. }
  1705. static int bnx2fc_allocate_hash_table(struct bnx2fc_hba *hba)
  1706. {
  1707. int i;
  1708. int hash_table_size;
  1709. int segment_count;
  1710. int segment_array_size;
  1711. int dma_segment_array_size;
  1712. dma_addr_t *dma_segment_array;
  1713. u32 *pbl;
  1714. hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL *
  1715. sizeof(struct fcoe_hash_table_entry);
  1716. segment_count = hash_table_size + BNX2FC_HASH_TBL_CHUNK_SIZE - 1;
  1717. segment_count /= BNX2FC_HASH_TBL_CHUNK_SIZE;
  1718. hba->hash_tbl_segment_count = segment_count;
  1719. segment_array_size = segment_count * sizeof(*hba->hash_tbl_segments);
  1720. hba->hash_tbl_segments = kzalloc(segment_array_size, GFP_KERNEL);
  1721. if (!hba->hash_tbl_segments) {
  1722. printk(KERN_ERR PFX "hash table pointers alloc failed\n");
  1723. return -ENOMEM;
  1724. }
  1725. dma_segment_array_size = segment_count * sizeof(*dma_segment_array);
  1726. dma_segment_array = kzalloc(dma_segment_array_size, GFP_KERNEL);
  1727. if (!dma_segment_array) {
  1728. printk(KERN_ERR PFX "hash table pointers (dma) alloc failed\n");
  1729. return -ENOMEM;
  1730. }
  1731. for (i = 0; i < segment_count; ++i) {
  1732. hba->hash_tbl_segments[i] =
  1733. dma_alloc_coherent(&hba->pcidev->dev,
  1734. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1735. &dma_segment_array[i],
  1736. GFP_KERNEL);
  1737. if (!hba->hash_tbl_segments[i]) {
  1738. printk(KERN_ERR PFX "hash segment alloc failed\n");
  1739. while (--i >= 0) {
  1740. dma_free_coherent(&hba->pcidev->dev,
  1741. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1742. hba->hash_tbl_segments[i],
  1743. dma_segment_array[i]);
  1744. hba->hash_tbl_segments[i] = NULL;
  1745. }
  1746. kfree(dma_segment_array);
  1747. return -ENOMEM;
  1748. }
  1749. memset(hba->hash_tbl_segments[i], 0,
  1750. BNX2FC_HASH_TBL_CHUNK_SIZE);
  1751. }
  1752. hba->hash_tbl_pbl = dma_alloc_coherent(&hba->pcidev->dev,
  1753. PAGE_SIZE,
  1754. &hba->hash_tbl_pbl_dma,
  1755. GFP_KERNEL);
  1756. if (!hba->hash_tbl_pbl) {
  1757. printk(KERN_ERR PFX "hash table pbl alloc failed\n");
  1758. kfree(dma_segment_array);
  1759. return -ENOMEM;
  1760. }
  1761. memset(hba->hash_tbl_pbl, 0, PAGE_SIZE);
  1762. pbl = hba->hash_tbl_pbl;
  1763. for (i = 0; i < segment_count; ++i) {
  1764. u64 paddr = dma_segment_array[i];
  1765. *pbl = cpu_to_le32((u32) paddr);
  1766. ++pbl;
  1767. *pbl = cpu_to_le32((u32) (paddr >> 32));
  1768. ++pbl;
  1769. }
  1770. pbl = hba->hash_tbl_pbl;
  1771. i = 0;
  1772. while (*pbl && *(pbl + 1)) {
  1773. u32 lo;
  1774. u32 hi;
  1775. lo = *pbl;
  1776. ++pbl;
  1777. hi = *pbl;
  1778. ++pbl;
  1779. ++i;
  1780. }
  1781. kfree(dma_segment_array);
  1782. return 0;
  1783. }
  1784. /**
  1785. * bnx2fc_setup_fw_resc - Allocate and map hash table and dummy buffer
  1786. *
  1787. * @hba: Pointer to adapter structure
  1788. *
  1789. */
  1790. int bnx2fc_setup_fw_resc(struct bnx2fc_hba *hba)
  1791. {
  1792. u64 addr;
  1793. u32 mem_size;
  1794. int i;
  1795. if (bnx2fc_allocate_hash_table(hba))
  1796. return -ENOMEM;
  1797. mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
  1798. hba->t2_hash_tbl_ptr = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
  1799. &hba->t2_hash_tbl_ptr_dma,
  1800. GFP_KERNEL);
  1801. if (!hba->t2_hash_tbl_ptr) {
  1802. printk(KERN_ERR PFX "unable to allocate t2 hash table ptr\n");
  1803. bnx2fc_free_fw_resc(hba);
  1804. return -ENOMEM;
  1805. }
  1806. memset(hba->t2_hash_tbl_ptr, 0x00, mem_size);
  1807. mem_size = BNX2FC_NUM_MAX_SESS *
  1808. sizeof(struct fcoe_t2_hash_table_entry);
  1809. hba->t2_hash_tbl = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
  1810. &hba->t2_hash_tbl_dma,
  1811. GFP_KERNEL);
  1812. if (!hba->t2_hash_tbl) {
  1813. printk(KERN_ERR PFX "unable to allocate t2 hash table\n");
  1814. bnx2fc_free_fw_resc(hba);
  1815. return -ENOMEM;
  1816. }
  1817. memset(hba->t2_hash_tbl, 0x00, mem_size);
  1818. for (i = 0; i < BNX2FC_NUM_MAX_SESS; i++) {
  1819. addr = (unsigned long) hba->t2_hash_tbl_dma +
  1820. ((i+1) * sizeof(struct fcoe_t2_hash_table_entry));
  1821. hba->t2_hash_tbl[i].next.lo = addr & 0xffffffff;
  1822. hba->t2_hash_tbl[i].next.hi = addr >> 32;
  1823. }
  1824. hba->dummy_buffer = dma_alloc_coherent(&hba->pcidev->dev,
  1825. PAGE_SIZE, &hba->dummy_buf_dma,
  1826. GFP_KERNEL);
  1827. if (!hba->dummy_buffer) {
  1828. printk(KERN_ERR PFX "unable to alloc MP Dummy Buffer\n");
  1829. bnx2fc_free_fw_resc(hba);
  1830. return -ENOMEM;
  1831. }
  1832. hba->stats_buffer = dma_alloc_coherent(&hba->pcidev->dev,
  1833. PAGE_SIZE,
  1834. &hba->stats_buf_dma,
  1835. GFP_KERNEL);
  1836. if (!hba->stats_buffer) {
  1837. printk(KERN_ERR PFX "unable to alloc Stats Buffer\n");
  1838. bnx2fc_free_fw_resc(hba);
  1839. return -ENOMEM;
  1840. }
  1841. memset(hba->stats_buffer, 0x00, PAGE_SIZE);
  1842. return 0;
  1843. }
  1844. void bnx2fc_free_fw_resc(struct bnx2fc_hba *hba)
  1845. {
  1846. u32 mem_size;
  1847. if (hba->stats_buffer) {
  1848. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1849. hba->stats_buffer, hba->stats_buf_dma);
  1850. hba->stats_buffer = NULL;
  1851. }
  1852. if (hba->dummy_buffer) {
  1853. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1854. hba->dummy_buffer, hba->dummy_buf_dma);
  1855. hba->dummy_buffer = NULL;
  1856. }
  1857. if (hba->t2_hash_tbl_ptr) {
  1858. mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
  1859. dma_free_coherent(&hba->pcidev->dev, mem_size,
  1860. hba->t2_hash_tbl_ptr,
  1861. hba->t2_hash_tbl_ptr_dma);
  1862. hba->t2_hash_tbl_ptr = NULL;
  1863. }
  1864. if (hba->t2_hash_tbl) {
  1865. mem_size = BNX2FC_NUM_MAX_SESS *
  1866. sizeof(struct fcoe_t2_hash_table_entry);
  1867. dma_free_coherent(&hba->pcidev->dev, mem_size,
  1868. hba->t2_hash_tbl, hba->t2_hash_tbl_dma);
  1869. hba->t2_hash_tbl = NULL;
  1870. }
  1871. bnx2fc_free_hash_table(hba);
  1872. }