pinctrl-bcm2835.c 28 KB

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  1. /*
  2. * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
  3. *
  4. * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
  5. *
  6. * This driver is inspired by:
  7. * pinctrl-nomadik.c, please see original file for copyright information
  8. * pinctrl-tegra.c, please see original file for copyright information
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. */
  20. #include <linux/bitmap.h>
  21. #include <linux/bug.h>
  22. #include <linux/delay.h>
  23. #include <linux/device.h>
  24. #include <linux/err.h>
  25. #include <linux/gpio.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/io.h>
  28. #include <linux/irq.h>
  29. #include <linux/irqdesc.h>
  30. #include <linux/irqdomain.h>
  31. #include <linux/module.h>
  32. #include <linux/of_address.h>
  33. #include <linux/of.h>
  34. #include <linux/of_irq.h>
  35. #include <linux/pinctrl/consumer.h>
  36. #include <linux/pinctrl/machine.h>
  37. #include <linux/pinctrl/pinconf.h>
  38. #include <linux/pinctrl/pinctrl.h>
  39. #include <linux/pinctrl/pinmux.h>
  40. #include <linux/platform_device.h>
  41. #include <linux/seq_file.h>
  42. #include <linux/slab.h>
  43. #include <linux/spinlock.h>
  44. #include <linux/types.h>
  45. #define MODULE_NAME "pinctrl-bcm2835"
  46. #define BCM2835_NUM_GPIOS 54
  47. #define BCM2835_NUM_BANKS 2
  48. #define BCM2835_PIN_BITMAP_SZ \
  49. DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
  50. /* GPIO register offsets */
  51. #define GPFSEL0 0x0 /* Function Select */
  52. #define GPSET0 0x1c /* Pin Output Set */
  53. #define GPCLR0 0x28 /* Pin Output Clear */
  54. #define GPLEV0 0x34 /* Pin Level */
  55. #define GPEDS0 0x40 /* Pin Event Detect Status */
  56. #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
  57. #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
  58. #define GPHEN0 0x64 /* Pin High Detect Enable */
  59. #define GPLEN0 0x70 /* Pin Low Detect Enable */
  60. #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
  61. #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
  62. #define GPPUD 0x94 /* Pin Pull-up/down Enable */
  63. #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
  64. #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
  65. #define FSEL_SHIFT(p) (((p) % 10) * 3)
  66. #define GPIO_REG_OFFSET(p) ((p) / 32)
  67. #define GPIO_REG_SHIFT(p) ((p) % 32)
  68. enum bcm2835_pinconf_param {
  69. /* argument: bcm2835_pinconf_pull */
  70. BCM2835_PINCONF_PARAM_PULL,
  71. };
  72. enum bcm2835_pinconf_pull {
  73. BCM2835_PINCONFIG_PULL_NONE,
  74. BCM2835_PINCONFIG_PULL_DOWN,
  75. BCM2835_PINCONFIG_PULL_UP,
  76. };
  77. #define BCM2835_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
  78. #define BCM2835_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
  79. #define BCM2835_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
  80. struct bcm2835_gpio_irqdata {
  81. struct bcm2835_pinctrl *pc;
  82. int bank;
  83. };
  84. struct bcm2835_pinctrl {
  85. struct device *dev;
  86. void __iomem *base;
  87. int irq[BCM2835_NUM_BANKS];
  88. /* note: locking assumes each bank will have its own unsigned long */
  89. unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
  90. unsigned int irq_type[BCM2835_NUM_GPIOS];
  91. struct pinctrl_dev *pctl_dev;
  92. struct irq_domain *irq_domain;
  93. struct gpio_chip gpio_chip;
  94. struct pinctrl_gpio_range gpio_range;
  95. struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_BANKS];
  96. spinlock_t irq_lock[BCM2835_NUM_BANKS];
  97. };
  98. static struct lock_class_key gpio_lock_class;
  99. /* pins are just named GPIO0..GPIO53 */
  100. #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
  101. struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
  102. BCM2835_GPIO_PIN(0),
  103. BCM2835_GPIO_PIN(1),
  104. BCM2835_GPIO_PIN(2),
  105. BCM2835_GPIO_PIN(3),
  106. BCM2835_GPIO_PIN(4),
  107. BCM2835_GPIO_PIN(5),
  108. BCM2835_GPIO_PIN(6),
  109. BCM2835_GPIO_PIN(7),
  110. BCM2835_GPIO_PIN(8),
  111. BCM2835_GPIO_PIN(9),
  112. BCM2835_GPIO_PIN(10),
  113. BCM2835_GPIO_PIN(11),
  114. BCM2835_GPIO_PIN(12),
  115. BCM2835_GPIO_PIN(13),
  116. BCM2835_GPIO_PIN(14),
  117. BCM2835_GPIO_PIN(15),
  118. BCM2835_GPIO_PIN(16),
  119. BCM2835_GPIO_PIN(17),
  120. BCM2835_GPIO_PIN(18),
  121. BCM2835_GPIO_PIN(19),
  122. BCM2835_GPIO_PIN(20),
  123. BCM2835_GPIO_PIN(21),
  124. BCM2835_GPIO_PIN(22),
  125. BCM2835_GPIO_PIN(23),
  126. BCM2835_GPIO_PIN(24),
  127. BCM2835_GPIO_PIN(25),
  128. BCM2835_GPIO_PIN(26),
  129. BCM2835_GPIO_PIN(27),
  130. BCM2835_GPIO_PIN(28),
  131. BCM2835_GPIO_PIN(29),
  132. BCM2835_GPIO_PIN(30),
  133. BCM2835_GPIO_PIN(31),
  134. BCM2835_GPIO_PIN(32),
  135. BCM2835_GPIO_PIN(33),
  136. BCM2835_GPIO_PIN(34),
  137. BCM2835_GPIO_PIN(35),
  138. BCM2835_GPIO_PIN(36),
  139. BCM2835_GPIO_PIN(37),
  140. BCM2835_GPIO_PIN(38),
  141. BCM2835_GPIO_PIN(39),
  142. BCM2835_GPIO_PIN(40),
  143. BCM2835_GPIO_PIN(41),
  144. BCM2835_GPIO_PIN(42),
  145. BCM2835_GPIO_PIN(43),
  146. BCM2835_GPIO_PIN(44),
  147. BCM2835_GPIO_PIN(45),
  148. BCM2835_GPIO_PIN(46),
  149. BCM2835_GPIO_PIN(47),
  150. BCM2835_GPIO_PIN(48),
  151. BCM2835_GPIO_PIN(49),
  152. BCM2835_GPIO_PIN(50),
  153. BCM2835_GPIO_PIN(51),
  154. BCM2835_GPIO_PIN(52),
  155. BCM2835_GPIO_PIN(53),
  156. };
  157. /* one pin per group */
  158. static const char * const bcm2835_gpio_groups[] = {
  159. "gpio0",
  160. "gpio1",
  161. "gpio2",
  162. "gpio3",
  163. "gpio4",
  164. "gpio5",
  165. "gpio6",
  166. "gpio7",
  167. "gpio8",
  168. "gpio9",
  169. "gpio10",
  170. "gpio11",
  171. "gpio12",
  172. "gpio13",
  173. "gpio14",
  174. "gpio15",
  175. "gpio16",
  176. "gpio17",
  177. "gpio18",
  178. "gpio19",
  179. "gpio20",
  180. "gpio21",
  181. "gpio22",
  182. "gpio23",
  183. "gpio24",
  184. "gpio25",
  185. "gpio26",
  186. "gpio27",
  187. "gpio28",
  188. "gpio29",
  189. "gpio30",
  190. "gpio31",
  191. "gpio32",
  192. "gpio33",
  193. "gpio34",
  194. "gpio35",
  195. "gpio36",
  196. "gpio37",
  197. "gpio38",
  198. "gpio39",
  199. "gpio40",
  200. "gpio41",
  201. "gpio42",
  202. "gpio43",
  203. "gpio44",
  204. "gpio45",
  205. "gpio46",
  206. "gpio47",
  207. "gpio48",
  208. "gpio49",
  209. "gpio50",
  210. "gpio51",
  211. "gpio52",
  212. "gpio53",
  213. };
  214. enum bcm2835_fsel {
  215. BCM2835_FSEL_GPIO_IN = 0,
  216. BCM2835_FSEL_GPIO_OUT = 1,
  217. BCM2835_FSEL_ALT0 = 4,
  218. BCM2835_FSEL_ALT1 = 5,
  219. BCM2835_FSEL_ALT2 = 6,
  220. BCM2835_FSEL_ALT3 = 7,
  221. BCM2835_FSEL_ALT4 = 3,
  222. BCM2835_FSEL_ALT5 = 2,
  223. BCM2835_FSEL_COUNT = 8,
  224. BCM2835_FSEL_MASK = 0x7,
  225. };
  226. static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
  227. [BCM2835_FSEL_GPIO_IN] = "gpio_in",
  228. [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
  229. [BCM2835_FSEL_ALT0] = "alt0",
  230. [BCM2835_FSEL_ALT1] = "alt1",
  231. [BCM2835_FSEL_ALT2] = "alt2",
  232. [BCM2835_FSEL_ALT3] = "alt3",
  233. [BCM2835_FSEL_ALT4] = "alt4",
  234. [BCM2835_FSEL_ALT5] = "alt5",
  235. };
  236. static const char * const irq_type_names[] = {
  237. [IRQ_TYPE_NONE] = "none",
  238. [IRQ_TYPE_EDGE_RISING] = "edge-rising",
  239. [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
  240. [IRQ_TYPE_EDGE_BOTH] = "edge-both",
  241. [IRQ_TYPE_LEVEL_HIGH] = "level-high",
  242. [IRQ_TYPE_LEVEL_LOW] = "level-low",
  243. };
  244. static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
  245. {
  246. return readl(pc->base + reg);
  247. }
  248. static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
  249. u32 val)
  250. {
  251. writel(val, pc->base + reg);
  252. }
  253. static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
  254. unsigned bit)
  255. {
  256. reg += GPIO_REG_OFFSET(bit) * 4;
  257. return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
  258. }
  259. /* note NOT a read/modify/write cycle */
  260. static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
  261. unsigned reg, unsigned bit)
  262. {
  263. reg += GPIO_REG_OFFSET(bit) * 4;
  264. bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
  265. }
  266. static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
  267. struct bcm2835_pinctrl *pc, unsigned pin)
  268. {
  269. u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
  270. enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
  271. dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
  272. bcm2835_functions[status]);
  273. return status;
  274. }
  275. static inline void bcm2835_pinctrl_fsel_set(
  276. struct bcm2835_pinctrl *pc, unsigned pin,
  277. enum bcm2835_fsel fsel)
  278. {
  279. u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
  280. enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
  281. dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
  282. bcm2835_functions[cur]);
  283. if (cur == fsel)
  284. return;
  285. if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
  286. /* always transition through GPIO_IN */
  287. val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
  288. val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
  289. dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
  290. bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
  291. bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
  292. }
  293. val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
  294. val |= fsel << FSEL_SHIFT(pin);
  295. dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
  296. bcm2835_functions[fsel]);
  297. bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
  298. }
  299. static int bcm2835_gpio_request(struct gpio_chip *chip, unsigned offset)
  300. {
  301. return pinctrl_request_gpio(chip->base + offset);
  302. }
  303. static void bcm2835_gpio_free(struct gpio_chip *chip, unsigned offset)
  304. {
  305. pinctrl_free_gpio(chip->base + offset);
  306. }
  307. static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  308. {
  309. return pinctrl_gpio_direction_input(chip->base + offset);
  310. }
  311. static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
  312. {
  313. struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
  314. return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
  315. }
  316. static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
  317. unsigned offset, int value)
  318. {
  319. return pinctrl_gpio_direction_output(chip->base + offset);
  320. }
  321. static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  322. {
  323. struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
  324. bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
  325. }
  326. static int bcm2835_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
  327. {
  328. struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
  329. return irq_linear_revmap(pc->irq_domain, offset);
  330. }
  331. static struct gpio_chip bcm2835_gpio_chip = {
  332. .label = MODULE_NAME,
  333. .owner = THIS_MODULE,
  334. .request = bcm2835_gpio_request,
  335. .free = bcm2835_gpio_free,
  336. .direction_input = bcm2835_gpio_direction_input,
  337. .direction_output = bcm2835_gpio_direction_output,
  338. .get = bcm2835_gpio_get,
  339. .set = bcm2835_gpio_set,
  340. .to_irq = bcm2835_gpio_to_irq,
  341. .base = -1,
  342. .ngpio = BCM2835_NUM_GPIOS,
  343. .can_sleep = 0,
  344. };
  345. static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id)
  346. {
  347. struct bcm2835_gpio_irqdata *irqdata = dev_id;
  348. struct bcm2835_pinctrl *pc = irqdata->pc;
  349. int bank = irqdata->bank;
  350. unsigned long events;
  351. unsigned offset;
  352. unsigned gpio;
  353. unsigned int type;
  354. events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
  355. events &= pc->enabled_irq_map[bank];
  356. for_each_set_bit(offset, &events, 32) {
  357. gpio = (32 * bank) + offset;
  358. type = pc->irq_type[gpio];
  359. /* ack edge triggered IRQs immediately */
  360. if (!(type & IRQ_TYPE_LEVEL_MASK))
  361. bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
  362. generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio));
  363. /* ack level triggered IRQ after handling them */
  364. if (type & IRQ_TYPE_LEVEL_MASK)
  365. bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
  366. }
  367. return events ? IRQ_HANDLED : IRQ_NONE;
  368. }
  369. static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
  370. unsigned reg, unsigned offset, bool enable)
  371. {
  372. u32 value;
  373. reg += GPIO_REG_OFFSET(offset) * 4;
  374. value = bcm2835_gpio_rd(pc, reg);
  375. if (enable)
  376. value |= BIT(GPIO_REG_SHIFT(offset));
  377. else
  378. value &= ~(BIT(GPIO_REG_SHIFT(offset)));
  379. bcm2835_gpio_wr(pc, reg, value);
  380. }
  381. /* fast path for IRQ handler */
  382. static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
  383. unsigned offset, bool enable)
  384. {
  385. switch (pc->irq_type[offset]) {
  386. case IRQ_TYPE_EDGE_RISING:
  387. __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
  388. break;
  389. case IRQ_TYPE_EDGE_FALLING:
  390. __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
  391. break;
  392. case IRQ_TYPE_EDGE_BOTH:
  393. __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
  394. __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
  395. break;
  396. case IRQ_TYPE_LEVEL_HIGH:
  397. __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
  398. break;
  399. case IRQ_TYPE_LEVEL_LOW:
  400. __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
  401. break;
  402. }
  403. }
  404. static void bcm2835_gpio_irq_enable(struct irq_data *data)
  405. {
  406. struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
  407. unsigned gpio = irqd_to_hwirq(data);
  408. unsigned offset = GPIO_REG_SHIFT(gpio);
  409. unsigned bank = GPIO_REG_OFFSET(gpio);
  410. unsigned long flags;
  411. spin_lock_irqsave(&pc->irq_lock[bank], flags);
  412. set_bit(offset, &pc->enabled_irq_map[bank]);
  413. bcm2835_gpio_irq_config(pc, gpio, true);
  414. spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
  415. }
  416. static void bcm2835_gpio_irq_disable(struct irq_data *data)
  417. {
  418. struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
  419. unsigned gpio = irqd_to_hwirq(data);
  420. unsigned offset = GPIO_REG_SHIFT(gpio);
  421. unsigned bank = GPIO_REG_OFFSET(gpio);
  422. unsigned long flags;
  423. spin_lock_irqsave(&pc->irq_lock[bank], flags);
  424. bcm2835_gpio_irq_config(pc, gpio, false);
  425. clear_bit(offset, &pc->enabled_irq_map[bank]);
  426. spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
  427. }
  428. static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
  429. unsigned offset, unsigned int type)
  430. {
  431. switch (type) {
  432. case IRQ_TYPE_NONE:
  433. case IRQ_TYPE_EDGE_RISING:
  434. case IRQ_TYPE_EDGE_FALLING:
  435. case IRQ_TYPE_EDGE_BOTH:
  436. case IRQ_TYPE_LEVEL_HIGH:
  437. case IRQ_TYPE_LEVEL_LOW:
  438. pc->irq_type[offset] = type;
  439. break;
  440. default:
  441. return -EINVAL;
  442. }
  443. return 0;
  444. }
  445. /* slower path for reconfiguring IRQ type */
  446. static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
  447. unsigned offset, unsigned int type)
  448. {
  449. switch (type) {
  450. case IRQ_TYPE_NONE:
  451. if (pc->irq_type[offset] != type) {
  452. bcm2835_gpio_irq_config(pc, offset, false);
  453. pc->irq_type[offset] = type;
  454. }
  455. break;
  456. case IRQ_TYPE_EDGE_RISING:
  457. if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
  458. /* RISING already enabled, disable FALLING */
  459. pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
  460. bcm2835_gpio_irq_config(pc, offset, false);
  461. pc->irq_type[offset] = type;
  462. } else if (pc->irq_type[offset] != type) {
  463. bcm2835_gpio_irq_config(pc, offset, false);
  464. pc->irq_type[offset] = type;
  465. bcm2835_gpio_irq_config(pc, offset, true);
  466. }
  467. break;
  468. case IRQ_TYPE_EDGE_FALLING:
  469. if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
  470. /* FALLING already enabled, disable RISING */
  471. pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
  472. bcm2835_gpio_irq_config(pc, offset, false);
  473. pc->irq_type[offset] = type;
  474. } else if (pc->irq_type[offset] != type) {
  475. bcm2835_gpio_irq_config(pc, offset, false);
  476. pc->irq_type[offset] = type;
  477. bcm2835_gpio_irq_config(pc, offset, true);
  478. }
  479. break;
  480. case IRQ_TYPE_EDGE_BOTH:
  481. if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
  482. /* RISING already enabled, enable FALLING too */
  483. pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
  484. bcm2835_gpio_irq_config(pc, offset, true);
  485. pc->irq_type[offset] = type;
  486. } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
  487. /* FALLING already enabled, enable RISING too */
  488. pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
  489. bcm2835_gpio_irq_config(pc, offset, true);
  490. pc->irq_type[offset] = type;
  491. } else if (pc->irq_type[offset] != type) {
  492. bcm2835_gpio_irq_config(pc, offset, false);
  493. pc->irq_type[offset] = type;
  494. bcm2835_gpio_irq_config(pc, offset, true);
  495. }
  496. break;
  497. case IRQ_TYPE_LEVEL_HIGH:
  498. case IRQ_TYPE_LEVEL_LOW:
  499. if (pc->irq_type[offset] != type) {
  500. bcm2835_gpio_irq_config(pc, offset, false);
  501. pc->irq_type[offset] = type;
  502. bcm2835_gpio_irq_config(pc, offset, true);
  503. }
  504. break;
  505. default:
  506. return -EINVAL;
  507. }
  508. return 0;
  509. }
  510. static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
  511. {
  512. struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
  513. unsigned gpio = irqd_to_hwirq(data);
  514. unsigned offset = GPIO_REG_SHIFT(gpio);
  515. unsigned bank = GPIO_REG_OFFSET(gpio);
  516. unsigned long flags;
  517. int ret;
  518. spin_lock_irqsave(&pc->irq_lock[bank], flags);
  519. if (test_bit(offset, &pc->enabled_irq_map[bank]))
  520. ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
  521. else
  522. ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
  523. spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
  524. return ret;
  525. }
  526. static struct irq_chip bcm2835_gpio_irq_chip = {
  527. .name = MODULE_NAME,
  528. .irq_enable = bcm2835_gpio_irq_enable,
  529. .irq_disable = bcm2835_gpio_irq_disable,
  530. .irq_set_type = bcm2835_gpio_irq_set_type,
  531. };
  532. static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
  533. {
  534. return ARRAY_SIZE(bcm2835_gpio_groups);
  535. }
  536. static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
  537. unsigned selector)
  538. {
  539. return bcm2835_gpio_groups[selector];
  540. }
  541. static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
  542. unsigned selector,
  543. const unsigned **pins,
  544. unsigned *num_pins)
  545. {
  546. *pins = &bcm2835_gpio_pins[selector].number;
  547. *num_pins = 1;
  548. return 0;
  549. }
  550. static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
  551. struct seq_file *s,
  552. unsigned offset)
  553. {
  554. struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
  555. enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
  556. const char *fname = bcm2835_functions[fsel];
  557. int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
  558. int irq = irq_find_mapping(pc->irq_domain, offset);
  559. seq_printf(s, "function %s in %s; irq %d (%s)",
  560. fname, value ? "hi" : "lo",
  561. irq, irq_type_names[pc->irq_type[offset]]);
  562. }
  563. static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
  564. struct pinctrl_map *maps, unsigned num_maps)
  565. {
  566. int i;
  567. for (i = 0; i < num_maps; i++)
  568. if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
  569. kfree(maps[i].data.configs.configs);
  570. kfree(maps);
  571. }
  572. static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
  573. struct device_node *np, u32 pin, u32 fnum,
  574. struct pinctrl_map **maps)
  575. {
  576. struct pinctrl_map *map = *maps;
  577. if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
  578. dev_err(pc->dev, "%s: invalid brcm,function %d\n",
  579. of_node_full_name(np), fnum);
  580. return -EINVAL;
  581. }
  582. map->type = PIN_MAP_TYPE_MUX_GROUP;
  583. map->data.mux.group = bcm2835_gpio_groups[pin];
  584. map->data.mux.function = bcm2835_functions[fnum];
  585. (*maps)++;
  586. return 0;
  587. }
  588. static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
  589. struct device_node *np, u32 pin, u32 pull,
  590. struct pinctrl_map **maps)
  591. {
  592. struct pinctrl_map *map = *maps;
  593. unsigned long *configs;
  594. if (pull > 2) {
  595. dev_err(pc->dev, "%s: invalid brcm,pull %d\n",
  596. of_node_full_name(np), pull);
  597. return -EINVAL;
  598. }
  599. configs = kzalloc(sizeof(*configs), GFP_KERNEL);
  600. if (!configs)
  601. return -ENOMEM;
  602. configs[0] = BCM2835_PINCONF_PACK(BCM2835_PINCONF_PARAM_PULL, pull);
  603. map->type = PIN_MAP_TYPE_CONFIGS_PIN;
  604. map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
  605. map->data.configs.configs = configs;
  606. map->data.configs.num_configs = 1;
  607. (*maps)++;
  608. return 0;
  609. }
  610. static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
  611. struct device_node *np,
  612. struct pinctrl_map **map, unsigned *num_maps)
  613. {
  614. struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
  615. struct property *pins, *funcs, *pulls;
  616. int num_pins, num_funcs, num_pulls, maps_per_pin;
  617. struct pinctrl_map *maps, *cur_map;
  618. int i, err;
  619. u32 pin, func, pull;
  620. pins = of_find_property(np, "brcm,pins", NULL);
  621. if (!pins) {
  622. dev_err(pc->dev, "%s: missing brcm,pins property\n",
  623. of_node_full_name(np));
  624. return -EINVAL;
  625. }
  626. funcs = of_find_property(np, "brcm,function", NULL);
  627. pulls = of_find_property(np, "brcm,pull", NULL);
  628. if (!funcs && !pulls) {
  629. dev_err(pc->dev,
  630. "%s: neither brcm,function nor brcm,pull specified\n",
  631. of_node_full_name(np));
  632. return -EINVAL;
  633. }
  634. num_pins = pins->length / 4;
  635. num_funcs = funcs ? (funcs->length / 4) : 0;
  636. num_pulls = pulls ? (pulls->length / 4) : 0;
  637. if (num_funcs > 1 && num_funcs != num_pins) {
  638. dev_err(pc->dev,
  639. "%s: brcm,function must have 1 or %d entries\n",
  640. of_node_full_name(np), num_pins);
  641. return -EINVAL;
  642. }
  643. if (num_pulls > 1 && num_pulls != num_pins) {
  644. dev_err(pc->dev,
  645. "%s: brcm,pull must have 1 or %d entries\n",
  646. of_node_full_name(np), num_pins);
  647. return -EINVAL;
  648. }
  649. maps_per_pin = 0;
  650. if (num_funcs)
  651. maps_per_pin++;
  652. if (num_pulls)
  653. maps_per_pin++;
  654. cur_map = maps = kzalloc(num_pins * maps_per_pin * sizeof(*maps),
  655. GFP_KERNEL);
  656. if (!maps)
  657. return -ENOMEM;
  658. for (i = 0; i < num_pins; i++) {
  659. err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
  660. if (err)
  661. goto out;
  662. if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
  663. dev_err(pc->dev, "%s: invalid brcm,pins value %d\n",
  664. of_node_full_name(np), pin);
  665. err = -EINVAL;
  666. goto out;
  667. }
  668. if (num_funcs) {
  669. err = of_property_read_u32_index(np, "brcm,function",
  670. (num_funcs > 1) ? i : 0, &func);
  671. if (err)
  672. goto out;
  673. err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
  674. func, &cur_map);
  675. if (err)
  676. goto out;
  677. }
  678. if (num_pulls) {
  679. err = of_property_read_u32_index(np, "brcm,pull",
  680. (num_funcs > 1) ? i : 0, &pull);
  681. if (err)
  682. goto out;
  683. err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
  684. pull, &cur_map);
  685. if (err)
  686. goto out;
  687. }
  688. }
  689. *map = maps;
  690. *num_maps = num_pins * maps_per_pin;
  691. return 0;
  692. out:
  693. kfree(maps);
  694. return err;
  695. }
  696. static const struct pinctrl_ops bcm2835_pctl_ops = {
  697. .get_groups_count = bcm2835_pctl_get_groups_count,
  698. .get_group_name = bcm2835_pctl_get_group_name,
  699. .get_group_pins = bcm2835_pctl_get_group_pins,
  700. .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
  701. .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
  702. .dt_free_map = bcm2835_pctl_dt_free_map,
  703. };
  704. static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
  705. {
  706. return BCM2835_FSEL_COUNT;
  707. }
  708. static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
  709. unsigned selector)
  710. {
  711. return bcm2835_functions[selector];
  712. }
  713. static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
  714. unsigned selector,
  715. const char * const **groups,
  716. unsigned * const num_groups)
  717. {
  718. /* every pin can do every function */
  719. *groups = bcm2835_gpio_groups;
  720. *num_groups = ARRAY_SIZE(bcm2835_gpio_groups);
  721. return 0;
  722. }
  723. static int bcm2835_pmx_enable(struct pinctrl_dev *pctldev,
  724. unsigned func_selector,
  725. unsigned group_selector)
  726. {
  727. struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
  728. bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
  729. return 0;
  730. }
  731. static void bcm2835_pmx_disable(struct pinctrl_dev *pctldev,
  732. unsigned func_selector,
  733. unsigned group_selector)
  734. {
  735. struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
  736. /* disable by setting to GPIO_IN */
  737. bcm2835_pinctrl_fsel_set(pc, group_selector, BCM2835_FSEL_GPIO_IN);
  738. }
  739. static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
  740. struct pinctrl_gpio_range *range,
  741. unsigned offset)
  742. {
  743. struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
  744. /* disable by setting to GPIO_IN */
  745. bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
  746. }
  747. static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
  748. struct pinctrl_gpio_range *range,
  749. unsigned offset,
  750. bool input)
  751. {
  752. struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
  753. enum bcm2835_fsel fsel = input ?
  754. BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
  755. bcm2835_pinctrl_fsel_set(pc, offset, fsel);
  756. return 0;
  757. }
  758. static const struct pinmux_ops bcm2835_pmx_ops = {
  759. .get_functions_count = bcm2835_pmx_get_functions_count,
  760. .get_function_name = bcm2835_pmx_get_function_name,
  761. .get_function_groups = bcm2835_pmx_get_function_groups,
  762. .enable = bcm2835_pmx_enable,
  763. .disable = bcm2835_pmx_disable,
  764. .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
  765. .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
  766. };
  767. static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
  768. unsigned pin, unsigned long *config)
  769. {
  770. /* No way to read back config in HW */
  771. return -ENOTSUPP;
  772. }
  773. static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
  774. unsigned pin, unsigned long config)
  775. {
  776. struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
  777. enum bcm2835_pinconf_param param = BCM2835_PINCONF_UNPACK_PARAM(config);
  778. u16 arg = BCM2835_PINCONF_UNPACK_ARG(config);
  779. u32 off, bit;
  780. if (param != BCM2835_PINCONF_PARAM_PULL)
  781. return -EINVAL;
  782. off = GPIO_REG_OFFSET(pin);
  783. bit = GPIO_REG_SHIFT(pin);
  784. bcm2835_gpio_wr(pc, GPPUD, arg & 3);
  785. /*
  786. * Docs say to wait 150 cycles, but not of what. We assume a
  787. * 1 MHz clock here, which is pretty slow...
  788. */
  789. udelay(150);
  790. bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
  791. udelay(150);
  792. bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
  793. return 0;
  794. }
  795. static const struct pinconf_ops bcm2835_pinconf_ops = {
  796. .pin_config_get = bcm2835_pinconf_get,
  797. .pin_config_set = bcm2835_pinconf_set,
  798. };
  799. static struct pinctrl_desc bcm2835_pinctrl_desc = {
  800. .name = MODULE_NAME,
  801. .pins = bcm2835_gpio_pins,
  802. .npins = ARRAY_SIZE(bcm2835_gpio_pins),
  803. .pctlops = &bcm2835_pctl_ops,
  804. .pmxops = &bcm2835_pmx_ops,
  805. .confops = &bcm2835_pinconf_ops,
  806. .owner = THIS_MODULE,
  807. };
  808. static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
  809. .name = MODULE_NAME,
  810. .npins = BCM2835_NUM_GPIOS,
  811. };
  812. static int bcm2835_pinctrl_probe(struct platform_device *pdev)
  813. {
  814. struct device *dev = &pdev->dev;
  815. struct device_node *np = dev->of_node;
  816. struct bcm2835_pinctrl *pc;
  817. struct resource iomem;
  818. int err, i;
  819. BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS);
  820. BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS);
  821. pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
  822. if (!pc)
  823. return -ENOMEM;
  824. platform_set_drvdata(pdev, pc);
  825. pc->dev = dev;
  826. err = of_address_to_resource(np, 0, &iomem);
  827. if (err) {
  828. dev_err(dev, "could not get IO memory\n");
  829. return err;
  830. }
  831. pc->base = devm_ioremap_resource(dev, &iomem);
  832. if (IS_ERR(pc->base))
  833. return PTR_ERR(pc->base);
  834. pc->gpio_chip = bcm2835_gpio_chip;
  835. pc->gpio_chip.dev = dev;
  836. pc->gpio_chip.of_node = np;
  837. pc->irq_domain = irq_domain_add_linear(np, BCM2835_NUM_GPIOS,
  838. &irq_domain_simple_ops, NULL);
  839. if (!pc->irq_domain) {
  840. dev_err(dev, "could not create IRQ domain\n");
  841. return -ENOMEM;
  842. }
  843. for (i = 0; i < BCM2835_NUM_GPIOS; i++) {
  844. int irq = irq_create_mapping(pc->irq_domain, i);
  845. irq_set_lockdep_class(irq, &gpio_lock_class);
  846. irq_set_chip_and_handler(irq, &bcm2835_gpio_irq_chip,
  847. handle_simple_irq);
  848. irq_set_chip_data(irq, pc);
  849. set_irq_flags(irq, IRQF_VALID);
  850. }
  851. for (i = 0; i < BCM2835_NUM_BANKS; i++) {
  852. unsigned long events;
  853. unsigned offset;
  854. int len;
  855. char *name;
  856. /* clear event detection flags */
  857. bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
  858. bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
  859. bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
  860. bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
  861. bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
  862. bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
  863. /* clear all the events */
  864. events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
  865. for_each_set_bit(offset, &events, 32)
  866. bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
  867. pc->irq[i] = irq_of_parse_and_map(np, i);
  868. pc->irq_data[i].pc = pc;
  869. pc->irq_data[i].bank = i;
  870. spin_lock_init(&pc->irq_lock[i]);
  871. len = strlen(dev_name(pc->dev)) + 16;
  872. name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
  873. if (!name)
  874. return -ENOMEM;
  875. snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
  876. err = devm_request_irq(dev, pc->irq[i],
  877. bcm2835_gpio_irq_handler, IRQF_SHARED,
  878. name, &pc->irq_data[i]);
  879. if (err) {
  880. dev_err(dev, "unable to request IRQ %d\n", pc->irq[i]);
  881. return err;
  882. }
  883. }
  884. err = gpiochip_add(&pc->gpio_chip);
  885. if (err) {
  886. dev_err(dev, "could not add GPIO chip\n");
  887. return err;
  888. }
  889. pc->pctl_dev = pinctrl_register(&bcm2835_pinctrl_desc, dev, pc);
  890. if (!pc->pctl_dev) {
  891. gpiochip_remove(&pc->gpio_chip);
  892. return -EINVAL;
  893. }
  894. pc->gpio_range = bcm2835_pinctrl_gpio_range;
  895. pc->gpio_range.base = pc->gpio_chip.base;
  896. pc->gpio_range.gc = &pc->gpio_chip;
  897. pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
  898. return 0;
  899. }
  900. static int bcm2835_pinctrl_remove(struct platform_device *pdev)
  901. {
  902. struct bcm2835_pinctrl *pc = platform_get_drvdata(pdev);
  903. pinctrl_unregister(pc->pctl_dev);
  904. gpiochip_remove(&pc->gpio_chip);
  905. return 0;
  906. }
  907. static struct of_device_id bcm2835_pinctrl_match[] = {
  908. { .compatible = "brcm,bcm2835-gpio" },
  909. {}
  910. };
  911. MODULE_DEVICE_TABLE(of, bcm2835_pinctrl_match);
  912. static struct platform_driver bcm2835_pinctrl_driver = {
  913. .probe = bcm2835_pinctrl_probe,
  914. .remove = bcm2835_pinctrl_remove,
  915. .driver = {
  916. .name = MODULE_NAME,
  917. .owner = THIS_MODULE,
  918. .of_match_table = bcm2835_pinctrl_match,
  919. },
  920. };
  921. module_platform_driver(bcm2835_pinctrl_driver);
  922. MODULE_AUTHOR("Chris Boot, Simon Arlott, Stephen Warren");
  923. MODULE_DESCRIPTION("BCM2835 Pin control driver");
  924. MODULE_LICENSE("GPL");