resource_tracker.c 89 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
  4. * All rights reserved.
  5. * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
  6. *
  7. * This software is available to you under a choice of one of two
  8. * licenses. You may choose to be licensed under the terms of the GNU
  9. * General Public License (GPL) Version 2, available from the file
  10. * COPYING in the main directory of this source tree, or the
  11. * OpenIB.org BSD license below:
  12. *
  13. * Redistribution and use in source and binary forms, with or
  14. * without modification, are permitted provided that the following
  15. * conditions are met:
  16. *
  17. * - Redistributions of source code must retain the above
  18. * copyright notice, this list of conditions and the following
  19. * disclaimer.
  20. *
  21. * - Redistributions in binary form must reproduce the above
  22. * copyright notice, this list of conditions and the following
  23. * disclaimer in the documentation and/or other materials
  24. * provided with the distribution.
  25. *
  26. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33. * SOFTWARE.
  34. */
  35. #include <linux/sched.h>
  36. #include <linux/pci.h>
  37. #include <linux/errno.h>
  38. #include <linux/kernel.h>
  39. #include <linux/io.h>
  40. #include <linux/slab.h>
  41. #include <linux/mlx4/cmd.h>
  42. #include <linux/mlx4/qp.h>
  43. #include <linux/if_ether.h>
  44. #include <linux/etherdevice.h>
  45. #include "mlx4.h"
  46. #include "fw.h"
  47. #define MLX4_MAC_VALID (1ull << 63)
  48. struct mac_res {
  49. struct list_head list;
  50. u64 mac;
  51. u8 port;
  52. };
  53. struct res_common {
  54. struct list_head list;
  55. struct rb_node node;
  56. u64 res_id;
  57. int owner;
  58. int state;
  59. int from_state;
  60. int to_state;
  61. int removing;
  62. };
  63. enum {
  64. RES_ANY_BUSY = 1
  65. };
  66. struct res_gid {
  67. struct list_head list;
  68. u8 gid[16];
  69. enum mlx4_protocol prot;
  70. enum mlx4_steer_type steer;
  71. u64 reg_id;
  72. };
  73. enum res_qp_states {
  74. RES_QP_BUSY = RES_ANY_BUSY,
  75. /* QP number was allocated */
  76. RES_QP_RESERVED,
  77. /* ICM memory for QP context was mapped */
  78. RES_QP_MAPPED,
  79. /* QP is in hw ownership */
  80. RES_QP_HW
  81. };
  82. struct res_qp {
  83. struct res_common com;
  84. struct res_mtt *mtt;
  85. struct res_cq *rcq;
  86. struct res_cq *scq;
  87. struct res_srq *srq;
  88. struct list_head mcg_list;
  89. spinlock_t mcg_spl;
  90. int local_qpn;
  91. atomic_t ref_count;
  92. };
  93. enum res_mtt_states {
  94. RES_MTT_BUSY = RES_ANY_BUSY,
  95. RES_MTT_ALLOCATED,
  96. };
  97. static inline const char *mtt_states_str(enum res_mtt_states state)
  98. {
  99. switch (state) {
  100. case RES_MTT_BUSY: return "RES_MTT_BUSY";
  101. case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
  102. default: return "Unknown";
  103. }
  104. }
  105. struct res_mtt {
  106. struct res_common com;
  107. int order;
  108. atomic_t ref_count;
  109. };
  110. enum res_mpt_states {
  111. RES_MPT_BUSY = RES_ANY_BUSY,
  112. RES_MPT_RESERVED,
  113. RES_MPT_MAPPED,
  114. RES_MPT_HW,
  115. };
  116. struct res_mpt {
  117. struct res_common com;
  118. struct res_mtt *mtt;
  119. int key;
  120. };
  121. enum res_eq_states {
  122. RES_EQ_BUSY = RES_ANY_BUSY,
  123. RES_EQ_RESERVED,
  124. RES_EQ_HW,
  125. };
  126. struct res_eq {
  127. struct res_common com;
  128. struct res_mtt *mtt;
  129. };
  130. enum res_cq_states {
  131. RES_CQ_BUSY = RES_ANY_BUSY,
  132. RES_CQ_ALLOCATED,
  133. RES_CQ_HW,
  134. };
  135. struct res_cq {
  136. struct res_common com;
  137. struct res_mtt *mtt;
  138. atomic_t ref_count;
  139. };
  140. enum res_srq_states {
  141. RES_SRQ_BUSY = RES_ANY_BUSY,
  142. RES_SRQ_ALLOCATED,
  143. RES_SRQ_HW,
  144. };
  145. struct res_srq {
  146. struct res_common com;
  147. struct res_mtt *mtt;
  148. struct res_cq *cq;
  149. atomic_t ref_count;
  150. };
  151. enum res_counter_states {
  152. RES_COUNTER_BUSY = RES_ANY_BUSY,
  153. RES_COUNTER_ALLOCATED,
  154. };
  155. struct res_counter {
  156. struct res_common com;
  157. int port;
  158. };
  159. enum res_xrcdn_states {
  160. RES_XRCD_BUSY = RES_ANY_BUSY,
  161. RES_XRCD_ALLOCATED,
  162. };
  163. struct res_xrcdn {
  164. struct res_common com;
  165. int port;
  166. };
  167. enum res_fs_rule_states {
  168. RES_FS_RULE_BUSY = RES_ANY_BUSY,
  169. RES_FS_RULE_ALLOCATED,
  170. };
  171. struct res_fs_rule {
  172. struct res_common com;
  173. int qpn;
  174. };
  175. static void *res_tracker_lookup(struct rb_root *root, u64 res_id)
  176. {
  177. struct rb_node *node = root->rb_node;
  178. while (node) {
  179. struct res_common *res = container_of(node, struct res_common,
  180. node);
  181. if (res_id < res->res_id)
  182. node = node->rb_left;
  183. else if (res_id > res->res_id)
  184. node = node->rb_right;
  185. else
  186. return res;
  187. }
  188. return NULL;
  189. }
  190. static int res_tracker_insert(struct rb_root *root, struct res_common *res)
  191. {
  192. struct rb_node **new = &(root->rb_node), *parent = NULL;
  193. /* Figure out where to put new node */
  194. while (*new) {
  195. struct res_common *this = container_of(*new, struct res_common,
  196. node);
  197. parent = *new;
  198. if (res->res_id < this->res_id)
  199. new = &((*new)->rb_left);
  200. else if (res->res_id > this->res_id)
  201. new = &((*new)->rb_right);
  202. else
  203. return -EEXIST;
  204. }
  205. /* Add new node and rebalance tree. */
  206. rb_link_node(&res->node, parent, new);
  207. rb_insert_color(&res->node, root);
  208. return 0;
  209. }
  210. enum qp_transition {
  211. QP_TRANS_INIT2RTR,
  212. QP_TRANS_RTR2RTS,
  213. QP_TRANS_RTS2RTS,
  214. QP_TRANS_SQERR2RTS,
  215. QP_TRANS_SQD2SQD,
  216. QP_TRANS_SQD2RTS
  217. };
  218. /* For Debug uses */
  219. static const char *ResourceType(enum mlx4_resource rt)
  220. {
  221. switch (rt) {
  222. case RES_QP: return "RES_QP";
  223. case RES_CQ: return "RES_CQ";
  224. case RES_SRQ: return "RES_SRQ";
  225. case RES_MPT: return "RES_MPT";
  226. case RES_MTT: return "RES_MTT";
  227. case RES_MAC: return "RES_MAC";
  228. case RES_EQ: return "RES_EQ";
  229. case RES_COUNTER: return "RES_COUNTER";
  230. case RES_FS_RULE: return "RES_FS_RULE";
  231. case RES_XRCD: return "RES_XRCD";
  232. default: return "Unknown resource type !!!";
  233. };
  234. }
  235. int mlx4_init_resource_tracker(struct mlx4_dev *dev)
  236. {
  237. struct mlx4_priv *priv = mlx4_priv(dev);
  238. int i;
  239. int t;
  240. priv->mfunc.master.res_tracker.slave_list =
  241. kzalloc(dev->num_slaves * sizeof(struct slave_list),
  242. GFP_KERNEL);
  243. if (!priv->mfunc.master.res_tracker.slave_list)
  244. return -ENOMEM;
  245. for (i = 0 ; i < dev->num_slaves; i++) {
  246. for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
  247. INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
  248. slave_list[i].res_list[t]);
  249. mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  250. }
  251. mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
  252. dev->num_slaves);
  253. for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
  254. priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT;
  255. spin_lock_init(&priv->mfunc.master.res_tracker.lock);
  256. return 0 ;
  257. }
  258. void mlx4_free_resource_tracker(struct mlx4_dev *dev,
  259. enum mlx4_res_tracker_free_type type)
  260. {
  261. struct mlx4_priv *priv = mlx4_priv(dev);
  262. int i;
  263. if (priv->mfunc.master.res_tracker.slave_list) {
  264. if (type != RES_TR_FREE_STRUCTS_ONLY)
  265. for (i = 0 ; i < dev->num_slaves; i++)
  266. if (type == RES_TR_FREE_ALL ||
  267. dev->caps.function != i)
  268. mlx4_delete_all_resources_for_slave(dev, i);
  269. if (type != RES_TR_FREE_SLAVES_ONLY) {
  270. kfree(priv->mfunc.master.res_tracker.slave_list);
  271. priv->mfunc.master.res_tracker.slave_list = NULL;
  272. }
  273. }
  274. }
  275. static void update_pkey_index(struct mlx4_dev *dev, int slave,
  276. struct mlx4_cmd_mailbox *inbox)
  277. {
  278. u8 sched = *(u8 *)(inbox->buf + 64);
  279. u8 orig_index = *(u8 *)(inbox->buf + 35);
  280. u8 new_index;
  281. struct mlx4_priv *priv = mlx4_priv(dev);
  282. int port;
  283. port = (sched >> 6 & 1) + 1;
  284. new_index = priv->virt2phys_pkey[slave][port - 1][orig_index];
  285. *(u8 *)(inbox->buf + 35) = new_index;
  286. }
  287. static void update_gid(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *inbox,
  288. u8 slave)
  289. {
  290. struct mlx4_qp_context *qp_ctx = inbox->buf + 8;
  291. enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *) inbox->buf);
  292. u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  293. if (MLX4_QP_ST_UD == ts)
  294. qp_ctx->pri_path.mgid_index = 0x80 | slave;
  295. if (MLX4_QP_ST_RC == ts || MLX4_QP_ST_UC == ts) {
  296. if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH)
  297. qp_ctx->pri_path.mgid_index = slave & 0x7F;
  298. if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH)
  299. qp_ctx->alt_path.mgid_index = slave & 0x7F;
  300. }
  301. }
  302. static int update_vport_qp_param(struct mlx4_dev *dev,
  303. struct mlx4_cmd_mailbox *inbox,
  304. u8 slave)
  305. {
  306. struct mlx4_qp_context *qpc = inbox->buf + 8;
  307. struct mlx4_vport_oper_state *vp_oper;
  308. struct mlx4_priv *priv;
  309. u32 qp_type;
  310. int port;
  311. port = (qpc->pri_path.sched_queue & 0x40) ? 2 : 1;
  312. priv = mlx4_priv(dev);
  313. vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
  314. if (MLX4_VGT != vp_oper->state.default_vlan) {
  315. qp_type = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
  316. if (MLX4_QP_ST_RC == qp_type)
  317. return -EINVAL;
  318. qpc->pri_path.vlan_index = vp_oper->vlan_idx;
  319. qpc->pri_path.fl = (1 << 6) | (1 << 2); /* set cv bit and hide_cqe_vlan bit*/
  320. qpc->pri_path.feup |= 1 << 3; /* set fvl bit */
  321. qpc->pri_path.sched_queue &= 0xC7;
  322. qpc->pri_path.sched_queue |= (vp_oper->state.default_qos) << 3;
  323. mlx4_dbg(dev, "qp %d port %d Q 0x%x set vlan to %d vidx %d feup %x fl %x\n",
  324. be32_to_cpu(qpc->local_qpn) & 0xffffff, port,
  325. (int)(qpc->pri_path.sched_queue), vp_oper->state.default_vlan,
  326. vp_oper->vlan_idx, (int)(qpc->pri_path.feup),
  327. (int)(qpc->pri_path.fl));
  328. }
  329. if (vp_oper->state.spoofchk) {
  330. qpc->pri_path.feup |= 1 << 5; /* set fsm bit */;
  331. qpc->pri_path.grh_mylmc = (0x80 & qpc->pri_path.grh_mylmc) + vp_oper->mac_idx;
  332. mlx4_dbg(dev, "spoof qp %d port %d feup 0x%x, myLmc 0x%x mindx %d\n",
  333. be32_to_cpu(qpc->local_qpn) & 0xffffff, port,
  334. (int)qpc->pri_path.feup, (int)qpc->pri_path.grh_mylmc,
  335. vp_oper->mac_idx);
  336. }
  337. return 0;
  338. }
  339. static int mpt_mask(struct mlx4_dev *dev)
  340. {
  341. return dev->caps.num_mpts - 1;
  342. }
  343. static void *find_res(struct mlx4_dev *dev, u64 res_id,
  344. enum mlx4_resource type)
  345. {
  346. struct mlx4_priv *priv = mlx4_priv(dev);
  347. return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
  348. res_id);
  349. }
  350. static int get_res(struct mlx4_dev *dev, int slave, u64 res_id,
  351. enum mlx4_resource type,
  352. void *res)
  353. {
  354. struct res_common *r;
  355. int err = 0;
  356. spin_lock_irq(mlx4_tlock(dev));
  357. r = find_res(dev, res_id, type);
  358. if (!r) {
  359. err = -ENONET;
  360. goto exit;
  361. }
  362. if (r->state == RES_ANY_BUSY) {
  363. err = -EBUSY;
  364. goto exit;
  365. }
  366. if (r->owner != slave) {
  367. err = -EPERM;
  368. goto exit;
  369. }
  370. r->from_state = r->state;
  371. r->state = RES_ANY_BUSY;
  372. if (res)
  373. *((struct res_common **)res) = r;
  374. exit:
  375. spin_unlock_irq(mlx4_tlock(dev));
  376. return err;
  377. }
  378. int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
  379. enum mlx4_resource type,
  380. u64 res_id, int *slave)
  381. {
  382. struct res_common *r;
  383. int err = -ENOENT;
  384. int id = res_id;
  385. if (type == RES_QP)
  386. id &= 0x7fffff;
  387. spin_lock(mlx4_tlock(dev));
  388. r = find_res(dev, id, type);
  389. if (r) {
  390. *slave = r->owner;
  391. err = 0;
  392. }
  393. spin_unlock(mlx4_tlock(dev));
  394. return err;
  395. }
  396. static void put_res(struct mlx4_dev *dev, int slave, u64 res_id,
  397. enum mlx4_resource type)
  398. {
  399. struct res_common *r;
  400. spin_lock_irq(mlx4_tlock(dev));
  401. r = find_res(dev, res_id, type);
  402. if (r)
  403. r->state = r->from_state;
  404. spin_unlock_irq(mlx4_tlock(dev));
  405. }
  406. static struct res_common *alloc_qp_tr(int id)
  407. {
  408. struct res_qp *ret;
  409. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  410. if (!ret)
  411. return NULL;
  412. ret->com.res_id = id;
  413. ret->com.state = RES_QP_RESERVED;
  414. ret->local_qpn = id;
  415. INIT_LIST_HEAD(&ret->mcg_list);
  416. spin_lock_init(&ret->mcg_spl);
  417. atomic_set(&ret->ref_count, 0);
  418. return &ret->com;
  419. }
  420. static struct res_common *alloc_mtt_tr(int id, int order)
  421. {
  422. struct res_mtt *ret;
  423. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  424. if (!ret)
  425. return NULL;
  426. ret->com.res_id = id;
  427. ret->order = order;
  428. ret->com.state = RES_MTT_ALLOCATED;
  429. atomic_set(&ret->ref_count, 0);
  430. return &ret->com;
  431. }
  432. static struct res_common *alloc_mpt_tr(int id, int key)
  433. {
  434. struct res_mpt *ret;
  435. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  436. if (!ret)
  437. return NULL;
  438. ret->com.res_id = id;
  439. ret->com.state = RES_MPT_RESERVED;
  440. ret->key = key;
  441. return &ret->com;
  442. }
  443. static struct res_common *alloc_eq_tr(int id)
  444. {
  445. struct res_eq *ret;
  446. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  447. if (!ret)
  448. return NULL;
  449. ret->com.res_id = id;
  450. ret->com.state = RES_EQ_RESERVED;
  451. return &ret->com;
  452. }
  453. static struct res_common *alloc_cq_tr(int id)
  454. {
  455. struct res_cq *ret;
  456. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  457. if (!ret)
  458. return NULL;
  459. ret->com.res_id = id;
  460. ret->com.state = RES_CQ_ALLOCATED;
  461. atomic_set(&ret->ref_count, 0);
  462. return &ret->com;
  463. }
  464. static struct res_common *alloc_srq_tr(int id)
  465. {
  466. struct res_srq *ret;
  467. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  468. if (!ret)
  469. return NULL;
  470. ret->com.res_id = id;
  471. ret->com.state = RES_SRQ_ALLOCATED;
  472. atomic_set(&ret->ref_count, 0);
  473. return &ret->com;
  474. }
  475. static struct res_common *alloc_counter_tr(int id)
  476. {
  477. struct res_counter *ret;
  478. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  479. if (!ret)
  480. return NULL;
  481. ret->com.res_id = id;
  482. ret->com.state = RES_COUNTER_ALLOCATED;
  483. return &ret->com;
  484. }
  485. static struct res_common *alloc_xrcdn_tr(int id)
  486. {
  487. struct res_xrcdn *ret;
  488. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  489. if (!ret)
  490. return NULL;
  491. ret->com.res_id = id;
  492. ret->com.state = RES_XRCD_ALLOCATED;
  493. return &ret->com;
  494. }
  495. static struct res_common *alloc_fs_rule_tr(u64 id, int qpn)
  496. {
  497. struct res_fs_rule *ret;
  498. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  499. if (!ret)
  500. return NULL;
  501. ret->com.res_id = id;
  502. ret->com.state = RES_FS_RULE_ALLOCATED;
  503. ret->qpn = qpn;
  504. return &ret->com;
  505. }
  506. static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave,
  507. int extra)
  508. {
  509. struct res_common *ret;
  510. switch (type) {
  511. case RES_QP:
  512. ret = alloc_qp_tr(id);
  513. break;
  514. case RES_MPT:
  515. ret = alloc_mpt_tr(id, extra);
  516. break;
  517. case RES_MTT:
  518. ret = alloc_mtt_tr(id, extra);
  519. break;
  520. case RES_EQ:
  521. ret = alloc_eq_tr(id);
  522. break;
  523. case RES_CQ:
  524. ret = alloc_cq_tr(id);
  525. break;
  526. case RES_SRQ:
  527. ret = alloc_srq_tr(id);
  528. break;
  529. case RES_MAC:
  530. printk(KERN_ERR "implementation missing\n");
  531. return NULL;
  532. case RES_COUNTER:
  533. ret = alloc_counter_tr(id);
  534. break;
  535. case RES_XRCD:
  536. ret = alloc_xrcdn_tr(id);
  537. break;
  538. case RES_FS_RULE:
  539. ret = alloc_fs_rule_tr(id, extra);
  540. break;
  541. default:
  542. return NULL;
  543. }
  544. if (ret)
  545. ret->owner = slave;
  546. return ret;
  547. }
  548. static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
  549. enum mlx4_resource type, int extra)
  550. {
  551. int i;
  552. int err;
  553. struct mlx4_priv *priv = mlx4_priv(dev);
  554. struct res_common **res_arr;
  555. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  556. struct rb_root *root = &tracker->res_tree[type];
  557. res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
  558. if (!res_arr)
  559. return -ENOMEM;
  560. for (i = 0; i < count; ++i) {
  561. res_arr[i] = alloc_tr(base + i, type, slave, extra);
  562. if (!res_arr[i]) {
  563. for (--i; i >= 0; --i)
  564. kfree(res_arr[i]);
  565. kfree(res_arr);
  566. return -ENOMEM;
  567. }
  568. }
  569. spin_lock_irq(mlx4_tlock(dev));
  570. for (i = 0; i < count; ++i) {
  571. if (find_res(dev, base + i, type)) {
  572. err = -EEXIST;
  573. goto undo;
  574. }
  575. err = res_tracker_insert(root, res_arr[i]);
  576. if (err)
  577. goto undo;
  578. list_add_tail(&res_arr[i]->list,
  579. &tracker->slave_list[slave].res_list[type]);
  580. }
  581. spin_unlock_irq(mlx4_tlock(dev));
  582. kfree(res_arr);
  583. return 0;
  584. undo:
  585. for (--i; i >= base; --i)
  586. rb_erase(&res_arr[i]->node, root);
  587. spin_unlock_irq(mlx4_tlock(dev));
  588. for (i = 0; i < count; ++i)
  589. kfree(res_arr[i]);
  590. kfree(res_arr);
  591. return err;
  592. }
  593. static int remove_qp_ok(struct res_qp *res)
  594. {
  595. if (res->com.state == RES_QP_BUSY || atomic_read(&res->ref_count) ||
  596. !list_empty(&res->mcg_list)) {
  597. pr_err("resource tracker: fail to remove qp, state %d, ref_count %d\n",
  598. res->com.state, atomic_read(&res->ref_count));
  599. return -EBUSY;
  600. } else if (res->com.state != RES_QP_RESERVED) {
  601. return -EPERM;
  602. }
  603. return 0;
  604. }
  605. static int remove_mtt_ok(struct res_mtt *res, int order)
  606. {
  607. if (res->com.state == RES_MTT_BUSY ||
  608. atomic_read(&res->ref_count)) {
  609. printk(KERN_DEBUG "%s-%d: state %s, ref_count %d\n",
  610. __func__, __LINE__,
  611. mtt_states_str(res->com.state),
  612. atomic_read(&res->ref_count));
  613. return -EBUSY;
  614. } else if (res->com.state != RES_MTT_ALLOCATED)
  615. return -EPERM;
  616. else if (res->order != order)
  617. return -EINVAL;
  618. return 0;
  619. }
  620. static int remove_mpt_ok(struct res_mpt *res)
  621. {
  622. if (res->com.state == RES_MPT_BUSY)
  623. return -EBUSY;
  624. else if (res->com.state != RES_MPT_RESERVED)
  625. return -EPERM;
  626. return 0;
  627. }
  628. static int remove_eq_ok(struct res_eq *res)
  629. {
  630. if (res->com.state == RES_MPT_BUSY)
  631. return -EBUSY;
  632. else if (res->com.state != RES_MPT_RESERVED)
  633. return -EPERM;
  634. return 0;
  635. }
  636. static int remove_counter_ok(struct res_counter *res)
  637. {
  638. if (res->com.state == RES_COUNTER_BUSY)
  639. return -EBUSY;
  640. else if (res->com.state != RES_COUNTER_ALLOCATED)
  641. return -EPERM;
  642. return 0;
  643. }
  644. static int remove_xrcdn_ok(struct res_xrcdn *res)
  645. {
  646. if (res->com.state == RES_XRCD_BUSY)
  647. return -EBUSY;
  648. else if (res->com.state != RES_XRCD_ALLOCATED)
  649. return -EPERM;
  650. return 0;
  651. }
  652. static int remove_fs_rule_ok(struct res_fs_rule *res)
  653. {
  654. if (res->com.state == RES_FS_RULE_BUSY)
  655. return -EBUSY;
  656. else if (res->com.state != RES_FS_RULE_ALLOCATED)
  657. return -EPERM;
  658. return 0;
  659. }
  660. static int remove_cq_ok(struct res_cq *res)
  661. {
  662. if (res->com.state == RES_CQ_BUSY)
  663. return -EBUSY;
  664. else if (res->com.state != RES_CQ_ALLOCATED)
  665. return -EPERM;
  666. return 0;
  667. }
  668. static int remove_srq_ok(struct res_srq *res)
  669. {
  670. if (res->com.state == RES_SRQ_BUSY)
  671. return -EBUSY;
  672. else if (res->com.state != RES_SRQ_ALLOCATED)
  673. return -EPERM;
  674. return 0;
  675. }
  676. static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
  677. {
  678. switch (type) {
  679. case RES_QP:
  680. return remove_qp_ok((struct res_qp *)res);
  681. case RES_CQ:
  682. return remove_cq_ok((struct res_cq *)res);
  683. case RES_SRQ:
  684. return remove_srq_ok((struct res_srq *)res);
  685. case RES_MPT:
  686. return remove_mpt_ok((struct res_mpt *)res);
  687. case RES_MTT:
  688. return remove_mtt_ok((struct res_mtt *)res, extra);
  689. case RES_MAC:
  690. return -ENOSYS;
  691. case RES_EQ:
  692. return remove_eq_ok((struct res_eq *)res);
  693. case RES_COUNTER:
  694. return remove_counter_ok((struct res_counter *)res);
  695. case RES_XRCD:
  696. return remove_xrcdn_ok((struct res_xrcdn *)res);
  697. case RES_FS_RULE:
  698. return remove_fs_rule_ok((struct res_fs_rule *)res);
  699. default:
  700. return -EINVAL;
  701. }
  702. }
  703. static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
  704. enum mlx4_resource type, int extra)
  705. {
  706. u64 i;
  707. int err;
  708. struct mlx4_priv *priv = mlx4_priv(dev);
  709. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  710. struct res_common *r;
  711. spin_lock_irq(mlx4_tlock(dev));
  712. for (i = base; i < base + count; ++i) {
  713. r = res_tracker_lookup(&tracker->res_tree[type], i);
  714. if (!r) {
  715. err = -ENOENT;
  716. goto out;
  717. }
  718. if (r->owner != slave) {
  719. err = -EPERM;
  720. goto out;
  721. }
  722. err = remove_ok(r, type, extra);
  723. if (err)
  724. goto out;
  725. }
  726. for (i = base; i < base + count; ++i) {
  727. r = res_tracker_lookup(&tracker->res_tree[type], i);
  728. rb_erase(&r->node, &tracker->res_tree[type]);
  729. list_del(&r->list);
  730. kfree(r);
  731. }
  732. err = 0;
  733. out:
  734. spin_unlock_irq(mlx4_tlock(dev));
  735. return err;
  736. }
  737. static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
  738. enum res_qp_states state, struct res_qp **qp,
  739. int alloc)
  740. {
  741. struct mlx4_priv *priv = mlx4_priv(dev);
  742. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  743. struct res_qp *r;
  744. int err = 0;
  745. spin_lock_irq(mlx4_tlock(dev));
  746. r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn);
  747. if (!r)
  748. err = -ENOENT;
  749. else if (r->com.owner != slave)
  750. err = -EPERM;
  751. else {
  752. switch (state) {
  753. case RES_QP_BUSY:
  754. mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n",
  755. __func__, r->com.res_id);
  756. err = -EBUSY;
  757. break;
  758. case RES_QP_RESERVED:
  759. if (r->com.state == RES_QP_MAPPED && !alloc)
  760. break;
  761. mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", r->com.res_id);
  762. err = -EINVAL;
  763. break;
  764. case RES_QP_MAPPED:
  765. if ((r->com.state == RES_QP_RESERVED && alloc) ||
  766. r->com.state == RES_QP_HW)
  767. break;
  768. else {
  769. mlx4_dbg(dev, "failed RES_QP, 0x%llx\n",
  770. r->com.res_id);
  771. err = -EINVAL;
  772. }
  773. break;
  774. case RES_QP_HW:
  775. if (r->com.state != RES_QP_MAPPED)
  776. err = -EINVAL;
  777. break;
  778. default:
  779. err = -EINVAL;
  780. }
  781. if (!err) {
  782. r->com.from_state = r->com.state;
  783. r->com.to_state = state;
  784. r->com.state = RES_QP_BUSY;
  785. if (qp)
  786. *qp = r;
  787. }
  788. }
  789. spin_unlock_irq(mlx4_tlock(dev));
  790. return err;
  791. }
  792. static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  793. enum res_mpt_states state, struct res_mpt **mpt)
  794. {
  795. struct mlx4_priv *priv = mlx4_priv(dev);
  796. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  797. struct res_mpt *r;
  798. int err = 0;
  799. spin_lock_irq(mlx4_tlock(dev));
  800. r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index);
  801. if (!r)
  802. err = -ENOENT;
  803. else if (r->com.owner != slave)
  804. err = -EPERM;
  805. else {
  806. switch (state) {
  807. case RES_MPT_BUSY:
  808. err = -EINVAL;
  809. break;
  810. case RES_MPT_RESERVED:
  811. if (r->com.state != RES_MPT_MAPPED)
  812. err = -EINVAL;
  813. break;
  814. case RES_MPT_MAPPED:
  815. if (r->com.state != RES_MPT_RESERVED &&
  816. r->com.state != RES_MPT_HW)
  817. err = -EINVAL;
  818. break;
  819. case RES_MPT_HW:
  820. if (r->com.state != RES_MPT_MAPPED)
  821. err = -EINVAL;
  822. break;
  823. default:
  824. err = -EINVAL;
  825. }
  826. if (!err) {
  827. r->com.from_state = r->com.state;
  828. r->com.to_state = state;
  829. r->com.state = RES_MPT_BUSY;
  830. if (mpt)
  831. *mpt = r;
  832. }
  833. }
  834. spin_unlock_irq(mlx4_tlock(dev));
  835. return err;
  836. }
  837. static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  838. enum res_eq_states state, struct res_eq **eq)
  839. {
  840. struct mlx4_priv *priv = mlx4_priv(dev);
  841. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  842. struct res_eq *r;
  843. int err = 0;
  844. spin_lock_irq(mlx4_tlock(dev));
  845. r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index);
  846. if (!r)
  847. err = -ENOENT;
  848. else if (r->com.owner != slave)
  849. err = -EPERM;
  850. else {
  851. switch (state) {
  852. case RES_EQ_BUSY:
  853. err = -EINVAL;
  854. break;
  855. case RES_EQ_RESERVED:
  856. if (r->com.state != RES_EQ_HW)
  857. err = -EINVAL;
  858. break;
  859. case RES_EQ_HW:
  860. if (r->com.state != RES_EQ_RESERVED)
  861. err = -EINVAL;
  862. break;
  863. default:
  864. err = -EINVAL;
  865. }
  866. if (!err) {
  867. r->com.from_state = r->com.state;
  868. r->com.to_state = state;
  869. r->com.state = RES_EQ_BUSY;
  870. if (eq)
  871. *eq = r;
  872. }
  873. }
  874. spin_unlock_irq(mlx4_tlock(dev));
  875. return err;
  876. }
  877. static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
  878. enum res_cq_states state, struct res_cq **cq)
  879. {
  880. struct mlx4_priv *priv = mlx4_priv(dev);
  881. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  882. struct res_cq *r;
  883. int err;
  884. spin_lock_irq(mlx4_tlock(dev));
  885. r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn);
  886. if (!r)
  887. err = -ENOENT;
  888. else if (r->com.owner != slave)
  889. err = -EPERM;
  890. else {
  891. switch (state) {
  892. case RES_CQ_BUSY:
  893. err = -EBUSY;
  894. break;
  895. case RES_CQ_ALLOCATED:
  896. if (r->com.state != RES_CQ_HW)
  897. err = -EINVAL;
  898. else if (atomic_read(&r->ref_count))
  899. err = -EBUSY;
  900. else
  901. err = 0;
  902. break;
  903. case RES_CQ_HW:
  904. if (r->com.state != RES_CQ_ALLOCATED)
  905. err = -EINVAL;
  906. else
  907. err = 0;
  908. break;
  909. default:
  910. err = -EINVAL;
  911. }
  912. if (!err) {
  913. r->com.from_state = r->com.state;
  914. r->com.to_state = state;
  915. r->com.state = RES_CQ_BUSY;
  916. if (cq)
  917. *cq = r;
  918. }
  919. }
  920. spin_unlock_irq(mlx4_tlock(dev));
  921. return err;
  922. }
  923. static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  924. enum res_cq_states state, struct res_srq **srq)
  925. {
  926. struct mlx4_priv *priv = mlx4_priv(dev);
  927. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  928. struct res_srq *r;
  929. int err = 0;
  930. spin_lock_irq(mlx4_tlock(dev));
  931. r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index);
  932. if (!r)
  933. err = -ENOENT;
  934. else if (r->com.owner != slave)
  935. err = -EPERM;
  936. else {
  937. switch (state) {
  938. case RES_SRQ_BUSY:
  939. err = -EINVAL;
  940. break;
  941. case RES_SRQ_ALLOCATED:
  942. if (r->com.state != RES_SRQ_HW)
  943. err = -EINVAL;
  944. else if (atomic_read(&r->ref_count))
  945. err = -EBUSY;
  946. break;
  947. case RES_SRQ_HW:
  948. if (r->com.state != RES_SRQ_ALLOCATED)
  949. err = -EINVAL;
  950. break;
  951. default:
  952. err = -EINVAL;
  953. }
  954. if (!err) {
  955. r->com.from_state = r->com.state;
  956. r->com.to_state = state;
  957. r->com.state = RES_SRQ_BUSY;
  958. if (srq)
  959. *srq = r;
  960. }
  961. }
  962. spin_unlock_irq(mlx4_tlock(dev));
  963. return err;
  964. }
  965. static void res_abort_move(struct mlx4_dev *dev, int slave,
  966. enum mlx4_resource type, int id)
  967. {
  968. struct mlx4_priv *priv = mlx4_priv(dev);
  969. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  970. struct res_common *r;
  971. spin_lock_irq(mlx4_tlock(dev));
  972. r = res_tracker_lookup(&tracker->res_tree[type], id);
  973. if (r && (r->owner == slave))
  974. r->state = r->from_state;
  975. spin_unlock_irq(mlx4_tlock(dev));
  976. }
  977. static void res_end_move(struct mlx4_dev *dev, int slave,
  978. enum mlx4_resource type, int id)
  979. {
  980. struct mlx4_priv *priv = mlx4_priv(dev);
  981. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  982. struct res_common *r;
  983. spin_lock_irq(mlx4_tlock(dev));
  984. r = res_tracker_lookup(&tracker->res_tree[type], id);
  985. if (r && (r->owner == slave))
  986. r->state = r->to_state;
  987. spin_unlock_irq(mlx4_tlock(dev));
  988. }
  989. static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
  990. {
  991. return mlx4_is_qp_reserved(dev, qpn) &&
  992. (mlx4_is_master(dev) || mlx4_is_guest_proxy(dev, slave, qpn));
  993. }
  994. static int fw_reserved(struct mlx4_dev *dev, int qpn)
  995. {
  996. return qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
  997. }
  998. static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  999. u64 in_param, u64 *out_param)
  1000. {
  1001. int err;
  1002. int count;
  1003. int align;
  1004. int base;
  1005. int qpn;
  1006. switch (op) {
  1007. case RES_OP_RESERVE:
  1008. count = get_param_l(&in_param);
  1009. align = get_param_h(&in_param);
  1010. err = __mlx4_qp_reserve_range(dev, count, align, &base);
  1011. if (err)
  1012. return err;
  1013. err = add_res_range(dev, slave, base, count, RES_QP, 0);
  1014. if (err) {
  1015. __mlx4_qp_release_range(dev, base, count);
  1016. return err;
  1017. }
  1018. set_param_l(out_param, base);
  1019. break;
  1020. case RES_OP_MAP_ICM:
  1021. qpn = get_param_l(&in_param) & 0x7fffff;
  1022. if (valid_reserved(dev, slave, qpn)) {
  1023. err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
  1024. if (err)
  1025. return err;
  1026. }
  1027. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
  1028. NULL, 1);
  1029. if (err)
  1030. return err;
  1031. if (!fw_reserved(dev, qpn)) {
  1032. err = __mlx4_qp_alloc_icm(dev, qpn);
  1033. if (err) {
  1034. res_abort_move(dev, slave, RES_QP, qpn);
  1035. return err;
  1036. }
  1037. }
  1038. res_end_move(dev, slave, RES_QP, qpn);
  1039. break;
  1040. default:
  1041. err = -EINVAL;
  1042. break;
  1043. }
  1044. return err;
  1045. }
  1046. static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1047. u64 in_param, u64 *out_param)
  1048. {
  1049. int err = -EINVAL;
  1050. int base;
  1051. int order;
  1052. if (op != RES_OP_RESERVE_AND_MAP)
  1053. return err;
  1054. order = get_param_l(&in_param);
  1055. base = __mlx4_alloc_mtt_range(dev, order);
  1056. if (base == -1)
  1057. return -ENOMEM;
  1058. err = add_res_range(dev, slave, base, 1, RES_MTT, order);
  1059. if (err)
  1060. __mlx4_free_mtt_range(dev, base, order);
  1061. else
  1062. set_param_l(out_param, base);
  1063. return err;
  1064. }
  1065. static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1066. u64 in_param, u64 *out_param)
  1067. {
  1068. int err = -EINVAL;
  1069. int index;
  1070. int id;
  1071. struct res_mpt *mpt;
  1072. switch (op) {
  1073. case RES_OP_RESERVE:
  1074. index = __mlx4_mpt_reserve(dev);
  1075. if (index == -1)
  1076. break;
  1077. id = index & mpt_mask(dev);
  1078. err = add_res_range(dev, slave, id, 1, RES_MPT, index);
  1079. if (err) {
  1080. __mlx4_mpt_release(dev, index);
  1081. break;
  1082. }
  1083. set_param_l(out_param, index);
  1084. break;
  1085. case RES_OP_MAP_ICM:
  1086. index = get_param_l(&in_param);
  1087. id = index & mpt_mask(dev);
  1088. err = mr_res_start_move_to(dev, slave, id,
  1089. RES_MPT_MAPPED, &mpt);
  1090. if (err)
  1091. return err;
  1092. err = __mlx4_mpt_alloc_icm(dev, mpt->key);
  1093. if (err) {
  1094. res_abort_move(dev, slave, RES_MPT, id);
  1095. return err;
  1096. }
  1097. res_end_move(dev, slave, RES_MPT, id);
  1098. break;
  1099. }
  1100. return err;
  1101. }
  1102. static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1103. u64 in_param, u64 *out_param)
  1104. {
  1105. int cqn;
  1106. int err;
  1107. switch (op) {
  1108. case RES_OP_RESERVE_AND_MAP:
  1109. err = __mlx4_cq_alloc_icm(dev, &cqn);
  1110. if (err)
  1111. break;
  1112. err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1113. if (err) {
  1114. __mlx4_cq_free_icm(dev, cqn);
  1115. break;
  1116. }
  1117. set_param_l(out_param, cqn);
  1118. break;
  1119. default:
  1120. err = -EINVAL;
  1121. }
  1122. return err;
  1123. }
  1124. static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1125. u64 in_param, u64 *out_param)
  1126. {
  1127. int srqn;
  1128. int err;
  1129. switch (op) {
  1130. case RES_OP_RESERVE_AND_MAP:
  1131. err = __mlx4_srq_alloc_icm(dev, &srqn);
  1132. if (err)
  1133. break;
  1134. err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1135. if (err) {
  1136. __mlx4_srq_free_icm(dev, srqn);
  1137. break;
  1138. }
  1139. set_param_l(out_param, srqn);
  1140. break;
  1141. default:
  1142. err = -EINVAL;
  1143. }
  1144. return err;
  1145. }
  1146. static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port)
  1147. {
  1148. struct mlx4_priv *priv = mlx4_priv(dev);
  1149. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1150. struct mac_res *res;
  1151. res = kzalloc(sizeof *res, GFP_KERNEL);
  1152. if (!res)
  1153. return -ENOMEM;
  1154. res->mac = mac;
  1155. res->port = (u8) port;
  1156. list_add_tail(&res->list,
  1157. &tracker->slave_list[slave].res_list[RES_MAC]);
  1158. return 0;
  1159. }
  1160. static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
  1161. int port)
  1162. {
  1163. struct mlx4_priv *priv = mlx4_priv(dev);
  1164. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1165. struct list_head *mac_list =
  1166. &tracker->slave_list[slave].res_list[RES_MAC];
  1167. struct mac_res *res, *tmp;
  1168. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1169. if (res->mac == mac && res->port == (u8) port) {
  1170. list_del(&res->list);
  1171. kfree(res);
  1172. break;
  1173. }
  1174. }
  1175. }
  1176. static void rem_slave_macs(struct mlx4_dev *dev, int slave)
  1177. {
  1178. struct mlx4_priv *priv = mlx4_priv(dev);
  1179. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1180. struct list_head *mac_list =
  1181. &tracker->slave_list[slave].res_list[RES_MAC];
  1182. struct mac_res *res, *tmp;
  1183. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1184. list_del(&res->list);
  1185. __mlx4_unregister_mac(dev, res->port, res->mac);
  1186. kfree(res);
  1187. }
  1188. }
  1189. static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1190. u64 in_param, u64 *out_param)
  1191. {
  1192. int err = -EINVAL;
  1193. int port;
  1194. u64 mac;
  1195. if (op != RES_OP_RESERVE_AND_MAP)
  1196. return err;
  1197. port = get_param_l(out_param);
  1198. mac = in_param;
  1199. err = __mlx4_register_mac(dev, port, mac);
  1200. if (err >= 0) {
  1201. set_param_l(out_param, err);
  1202. err = 0;
  1203. }
  1204. if (!err) {
  1205. err = mac_add_to_slave(dev, slave, mac, port);
  1206. if (err)
  1207. __mlx4_unregister_mac(dev, port, mac);
  1208. }
  1209. return err;
  1210. }
  1211. static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1212. u64 in_param, u64 *out_param)
  1213. {
  1214. return 0;
  1215. }
  1216. static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1217. u64 in_param, u64 *out_param)
  1218. {
  1219. u32 index;
  1220. int err;
  1221. if (op != RES_OP_RESERVE)
  1222. return -EINVAL;
  1223. err = __mlx4_counter_alloc(dev, &index);
  1224. if (err)
  1225. return err;
  1226. err = add_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  1227. if (err)
  1228. __mlx4_counter_free(dev, index);
  1229. else
  1230. set_param_l(out_param, index);
  1231. return err;
  1232. }
  1233. static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1234. u64 in_param, u64 *out_param)
  1235. {
  1236. u32 xrcdn;
  1237. int err;
  1238. if (op != RES_OP_RESERVE)
  1239. return -EINVAL;
  1240. err = __mlx4_xrcd_alloc(dev, &xrcdn);
  1241. if (err)
  1242. return err;
  1243. err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1244. if (err)
  1245. __mlx4_xrcd_free(dev, xrcdn);
  1246. else
  1247. set_param_l(out_param, xrcdn);
  1248. return err;
  1249. }
  1250. int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
  1251. struct mlx4_vhcr *vhcr,
  1252. struct mlx4_cmd_mailbox *inbox,
  1253. struct mlx4_cmd_mailbox *outbox,
  1254. struct mlx4_cmd_info *cmd)
  1255. {
  1256. int err;
  1257. int alop = vhcr->op_modifier;
  1258. switch (vhcr->in_modifier) {
  1259. case RES_QP:
  1260. err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1261. vhcr->in_param, &vhcr->out_param);
  1262. break;
  1263. case RES_MTT:
  1264. err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1265. vhcr->in_param, &vhcr->out_param);
  1266. break;
  1267. case RES_MPT:
  1268. err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1269. vhcr->in_param, &vhcr->out_param);
  1270. break;
  1271. case RES_CQ:
  1272. err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1273. vhcr->in_param, &vhcr->out_param);
  1274. break;
  1275. case RES_SRQ:
  1276. err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1277. vhcr->in_param, &vhcr->out_param);
  1278. break;
  1279. case RES_MAC:
  1280. err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1281. vhcr->in_param, &vhcr->out_param);
  1282. break;
  1283. case RES_VLAN:
  1284. err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1285. vhcr->in_param, &vhcr->out_param);
  1286. break;
  1287. case RES_COUNTER:
  1288. err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1289. vhcr->in_param, &vhcr->out_param);
  1290. break;
  1291. case RES_XRCD:
  1292. err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1293. vhcr->in_param, &vhcr->out_param);
  1294. break;
  1295. default:
  1296. err = -EINVAL;
  1297. break;
  1298. }
  1299. return err;
  1300. }
  1301. static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1302. u64 in_param)
  1303. {
  1304. int err;
  1305. int count;
  1306. int base;
  1307. int qpn;
  1308. switch (op) {
  1309. case RES_OP_RESERVE:
  1310. base = get_param_l(&in_param) & 0x7fffff;
  1311. count = get_param_h(&in_param);
  1312. err = rem_res_range(dev, slave, base, count, RES_QP, 0);
  1313. if (err)
  1314. break;
  1315. __mlx4_qp_release_range(dev, base, count);
  1316. break;
  1317. case RES_OP_MAP_ICM:
  1318. qpn = get_param_l(&in_param) & 0x7fffff;
  1319. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
  1320. NULL, 0);
  1321. if (err)
  1322. return err;
  1323. if (!fw_reserved(dev, qpn))
  1324. __mlx4_qp_free_icm(dev, qpn);
  1325. res_end_move(dev, slave, RES_QP, qpn);
  1326. if (valid_reserved(dev, slave, qpn))
  1327. err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
  1328. break;
  1329. default:
  1330. err = -EINVAL;
  1331. break;
  1332. }
  1333. return err;
  1334. }
  1335. static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1336. u64 in_param, u64 *out_param)
  1337. {
  1338. int err = -EINVAL;
  1339. int base;
  1340. int order;
  1341. if (op != RES_OP_RESERVE_AND_MAP)
  1342. return err;
  1343. base = get_param_l(&in_param);
  1344. order = get_param_h(&in_param);
  1345. err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
  1346. if (!err)
  1347. __mlx4_free_mtt_range(dev, base, order);
  1348. return err;
  1349. }
  1350. static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1351. u64 in_param)
  1352. {
  1353. int err = -EINVAL;
  1354. int index;
  1355. int id;
  1356. struct res_mpt *mpt;
  1357. switch (op) {
  1358. case RES_OP_RESERVE:
  1359. index = get_param_l(&in_param);
  1360. id = index & mpt_mask(dev);
  1361. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1362. if (err)
  1363. break;
  1364. index = mpt->key;
  1365. put_res(dev, slave, id, RES_MPT);
  1366. err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
  1367. if (err)
  1368. break;
  1369. __mlx4_mpt_release(dev, index);
  1370. break;
  1371. case RES_OP_MAP_ICM:
  1372. index = get_param_l(&in_param);
  1373. id = index & mpt_mask(dev);
  1374. err = mr_res_start_move_to(dev, slave, id,
  1375. RES_MPT_RESERVED, &mpt);
  1376. if (err)
  1377. return err;
  1378. __mlx4_mpt_free_icm(dev, mpt->key);
  1379. res_end_move(dev, slave, RES_MPT, id);
  1380. return err;
  1381. break;
  1382. default:
  1383. err = -EINVAL;
  1384. break;
  1385. }
  1386. return err;
  1387. }
  1388. static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1389. u64 in_param, u64 *out_param)
  1390. {
  1391. int cqn;
  1392. int err;
  1393. switch (op) {
  1394. case RES_OP_RESERVE_AND_MAP:
  1395. cqn = get_param_l(&in_param);
  1396. err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1397. if (err)
  1398. break;
  1399. __mlx4_cq_free_icm(dev, cqn);
  1400. break;
  1401. default:
  1402. err = -EINVAL;
  1403. break;
  1404. }
  1405. return err;
  1406. }
  1407. static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1408. u64 in_param, u64 *out_param)
  1409. {
  1410. int srqn;
  1411. int err;
  1412. switch (op) {
  1413. case RES_OP_RESERVE_AND_MAP:
  1414. srqn = get_param_l(&in_param);
  1415. err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1416. if (err)
  1417. break;
  1418. __mlx4_srq_free_icm(dev, srqn);
  1419. break;
  1420. default:
  1421. err = -EINVAL;
  1422. break;
  1423. }
  1424. return err;
  1425. }
  1426. static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1427. u64 in_param, u64 *out_param)
  1428. {
  1429. int port;
  1430. int err = 0;
  1431. switch (op) {
  1432. case RES_OP_RESERVE_AND_MAP:
  1433. port = get_param_l(out_param);
  1434. mac_del_from_slave(dev, slave, in_param, port);
  1435. __mlx4_unregister_mac(dev, port, in_param);
  1436. break;
  1437. default:
  1438. err = -EINVAL;
  1439. break;
  1440. }
  1441. return err;
  1442. }
  1443. static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1444. u64 in_param, u64 *out_param)
  1445. {
  1446. return 0;
  1447. }
  1448. static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1449. u64 in_param, u64 *out_param)
  1450. {
  1451. int index;
  1452. int err;
  1453. if (op != RES_OP_RESERVE)
  1454. return -EINVAL;
  1455. index = get_param_l(&in_param);
  1456. err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  1457. if (err)
  1458. return err;
  1459. __mlx4_counter_free(dev, index);
  1460. return err;
  1461. }
  1462. static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1463. u64 in_param, u64 *out_param)
  1464. {
  1465. int xrcdn;
  1466. int err;
  1467. if (op != RES_OP_RESERVE)
  1468. return -EINVAL;
  1469. xrcdn = get_param_l(&in_param);
  1470. err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1471. if (err)
  1472. return err;
  1473. __mlx4_xrcd_free(dev, xrcdn);
  1474. return err;
  1475. }
  1476. int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
  1477. struct mlx4_vhcr *vhcr,
  1478. struct mlx4_cmd_mailbox *inbox,
  1479. struct mlx4_cmd_mailbox *outbox,
  1480. struct mlx4_cmd_info *cmd)
  1481. {
  1482. int err = -EINVAL;
  1483. int alop = vhcr->op_modifier;
  1484. switch (vhcr->in_modifier) {
  1485. case RES_QP:
  1486. err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
  1487. vhcr->in_param);
  1488. break;
  1489. case RES_MTT:
  1490. err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
  1491. vhcr->in_param, &vhcr->out_param);
  1492. break;
  1493. case RES_MPT:
  1494. err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
  1495. vhcr->in_param);
  1496. break;
  1497. case RES_CQ:
  1498. err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
  1499. vhcr->in_param, &vhcr->out_param);
  1500. break;
  1501. case RES_SRQ:
  1502. err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
  1503. vhcr->in_param, &vhcr->out_param);
  1504. break;
  1505. case RES_MAC:
  1506. err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
  1507. vhcr->in_param, &vhcr->out_param);
  1508. break;
  1509. case RES_VLAN:
  1510. err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
  1511. vhcr->in_param, &vhcr->out_param);
  1512. break;
  1513. case RES_COUNTER:
  1514. err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
  1515. vhcr->in_param, &vhcr->out_param);
  1516. break;
  1517. case RES_XRCD:
  1518. err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
  1519. vhcr->in_param, &vhcr->out_param);
  1520. default:
  1521. break;
  1522. }
  1523. return err;
  1524. }
  1525. /* ugly but other choices are uglier */
  1526. static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
  1527. {
  1528. return (be32_to_cpu(mpt->flags) >> 9) & 1;
  1529. }
  1530. static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
  1531. {
  1532. return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
  1533. }
  1534. static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
  1535. {
  1536. return be32_to_cpu(mpt->mtt_sz);
  1537. }
  1538. static u32 mr_get_pd(struct mlx4_mpt_entry *mpt)
  1539. {
  1540. return be32_to_cpu(mpt->pd_flags) & 0x00ffffff;
  1541. }
  1542. static int mr_is_fmr(struct mlx4_mpt_entry *mpt)
  1543. {
  1544. return be32_to_cpu(mpt->pd_flags) & MLX4_MPT_PD_FLAG_FAST_REG;
  1545. }
  1546. static int mr_is_bind_enabled(struct mlx4_mpt_entry *mpt)
  1547. {
  1548. return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_BIND_ENABLE;
  1549. }
  1550. static int mr_is_region(struct mlx4_mpt_entry *mpt)
  1551. {
  1552. return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_REGION;
  1553. }
  1554. static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
  1555. {
  1556. return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
  1557. }
  1558. static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
  1559. {
  1560. return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
  1561. }
  1562. static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
  1563. {
  1564. int page_shift = (qpc->log_page_size & 0x3f) + 12;
  1565. int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
  1566. int log_sq_sride = qpc->sq_size_stride & 7;
  1567. int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
  1568. int log_rq_stride = qpc->rq_size_stride & 7;
  1569. int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
  1570. int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
  1571. int xrc = (be32_to_cpu(qpc->local_qpn) >> 23) & 1;
  1572. int sq_size;
  1573. int rq_size;
  1574. int total_pages;
  1575. int total_mem;
  1576. int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
  1577. sq_size = 1 << (log_sq_size + log_sq_sride + 4);
  1578. rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
  1579. total_mem = sq_size + rq_size;
  1580. total_pages =
  1581. roundup_pow_of_two((total_mem + (page_offset << 6)) >>
  1582. page_shift);
  1583. return total_pages;
  1584. }
  1585. static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
  1586. int size, struct res_mtt *mtt)
  1587. {
  1588. int res_start = mtt->com.res_id;
  1589. int res_size = (1 << mtt->order);
  1590. if (start < res_start || start + size > res_start + res_size)
  1591. return -EPERM;
  1592. return 0;
  1593. }
  1594. int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1595. struct mlx4_vhcr *vhcr,
  1596. struct mlx4_cmd_mailbox *inbox,
  1597. struct mlx4_cmd_mailbox *outbox,
  1598. struct mlx4_cmd_info *cmd)
  1599. {
  1600. int err;
  1601. int index = vhcr->in_modifier;
  1602. struct res_mtt *mtt;
  1603. struct res_mpt *mpt;
  1604. int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
  1605. int phys;
  1606. int id;
  1607. u32 pd;
  1608. int pd_slave;
  1609. id = index & mpt_mask(dev);
  1610. err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
  1611. if (err)
  1612. return err;
  1613. /* Disable memory windows for VFs. */
  1614. if (!mr_is_region(inbox->buf)) {
  1615. err = -EPERM;
  1616. goto ex_abort;
  1617. }
  1618. /* Make sure that the PD bits related to the slave id are zeros. */
  1619. pd = mr_get_pd(inbox->buf);
  1620. pd_slave = (pd >> 17) & 0x7f;
  1621. if (pd_slave != 0 && pd_slave != slave) {
  1622. err = -EPERM;
  1623. goto ex_abort;
  1624. }
  1625. if (mr_is_fmr(inbox->buf)) {
  1626. /* FMR and Bind Enable are forbidden in slave devices. */
  1627. if (mr_is_bind_enabled(inbox->buf)) {
  1628. err = -EPERM;
  1629. goto ex_abort;
  1630. }
  1631. /* FMR and Memory Windows are also forbidden. */
  1632. if (!mr_is_region(inbox->buf)) {
  1633. err = -EPERM;
  1634. goto ex_abort;
  1635. }
  1636. }
  1637. phys = mr_phys_mpt(inbox->buf);
  1638. if (!phys) {
  1639. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1640. if (err)
  1641. goto ex_abort;
  1642. err = check_mtt_range(dev, slave, mtt_base,
  1643. mr_get_mtt_size(inbox->buf), mtt);
  1644. if (err)
  1645. goto ex_put;
  1646. mpt->mtt = mtt;
  1647. }
  1648. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1649. if (err)
  1650. goto ex_put;
  1651. if (!phys) {
  1652. atomic_inc(&mtt->ref_count);
  1653. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1654. }
  1655. res_end_move(dev, slave, RES_MPT, id);
  1656. return 0;
  1657. ex_put:
  1658. if (!phys)
  1659. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1660. ex_abort:
  1661. res_abort_move(dev, slave, RES_MPT, id);
  1662. return err;
  1663. }
  1664. int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1665. struct mlx4_vhcr *vhcr,
  1666. struct mlx4_cmd_mailbox *inbox,
  1667. struct mlx4_cmd_mailbox *outbox,
  1668. struct mlx4_cmd_info *cmd)
  1669. {
  1670. int err;
  1671. int index = vhcr->in_modifier;
  1672. struct res_mpt *mpt;
  1673. int id;
  1674. id = index & mpt_mask(dev);
  1675. err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
  1676. if (err)
  1677. return err;
  1678. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1679. if (err)
  1680. goto ex_abort;
  1681. if (mpt->mtt)
  1682. atomic_dec(&mpt->mtt->ref_count);
  1683. res_end_move(dev, slave, RES_MPT, id);
  1684. return 0;
  1685. ex_abort:
  1686. res_abort_move(dev, slave, RES_MPT, id);
  1687. return err;
  1688. }
  1689. int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1690. struct mlx4_vhcr *vhcr,
  1691. struct mlx4_cmd_mailbox *inbox,
  1692. struct mlx4_cmd_mailbox *outbox,
  1693. struct mlx4_cmd_info *cmd)
  1694. {
  1695. int err;
  1696. int index = vhcr->in_modifier;
  1697. struct res_mpt *mpt;
  1698. int id;
  1699. id = index & mpt_mask(dev);
  1700. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1701. if (err)
  1702. return err;
  1703. if (mpt->com.from_state != RES_MPT_HW) {
  1704. err = -EBUSY;
  1705. goto out;
  1706. }
  1707. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1708. out:
  1709. put_res(dev, slave, id, RES_MPT);
  1710. return err;
  1711. }
  1712. static int qp_get_rcqn(struct mlx4_qp_context *qpc)
  1713. {
  1714. return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
  1715. }
  1716. static int qp_get_scqn(struct mlx4_qp_context *qpc)
  1717. {
  1718. return be32_to_cpu(qpc->cqn_send) & 0xffffff;
  1719. }
  1720. static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
  1721. {
  1722. return be32_to_cpu(qpc->srqn) & 0x1ffffff;
  1723. }
  1724. static void adjust_proxy_tun_qkey(struct mlx4_dev *dev, struct mlx4_vhcr *vhcr,
  1725. struct mlx4_qp_context *context)
  1726. {
  1727. u32 qpn = vhcr->in_modifier & 0xffffff;
  1728. u32 qkey = 0;
  1729. if (mlx4_get_parav_qkey(dev, qpn, &qkey))
  1730. return;
  1731. /* adjust qkey in qp context */
  1732. context->qkey = cpu_to_be32(qkey);
  1733. }
  1734. int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  1735. struct mlx4_vhcr *vhcr,
  1736. struct mlx4_cmd_mailbox *inbox,
  1737. struct mlx4_cmd_mailbox *outbox,
  1738. struct mlx4_cmd_info *cmd)
  1739. {
  1740. int err;
  1741. int qpn = vhcr->in_modifier & 0x7fffff;
  1742. struct res_mtt *mtt;
  1743. struct res_qp *qp;
  1744. struct mlx4_qp_context *qpc = inbox->buf + 8;
  1745. int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
  1746. int mtt_size = qp_get_mtt_size(qpc);
  1747. struct res_cq *rcq;
  1748. struct res_cq *scq;
  1749. int rcqn = qp_get_rcqn(qpc);
  1750. int scqn = qp_get_scqn(qpc);
  1751. u32 srqn = qp_get_srqn(qpc) & 0xffffff;
  1752. int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
  1753. struct res_srq *srq;
  1754. int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
  1755. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
  1756. if (err)
  1757. return err;
  1758. qp->local_qpn = local_qpn;
  1759. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1760. if (err)
  1761. goto ex_abort;
  1762. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1763. if (err)
  1764. goto ex_put_mtt;
  1765. err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
  1766. if (err)
  1767. goto ex_put_mtt;
  1768. if (scqn != rcqn) {
  1769. err = get_res(dev, slave, scqn, RES_CQ, &scq);
  1770. if (err)
  1771. goto ex_put_rcq;
  1772. } else
  1773. scq = rcq;
  1774. if (use_srq) {
  1775. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  1776. if (err)
  1777. goto ex_put_scq;
  1778. }
  1779. adjust_proxy_tun_qkey(dev, vhcr, qpc);
  1780. update_pkey_index(dev, slave, inbox);
  1781. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1782. if (err)
  1783. goto ex_put_srq;
  1784. atomic_inc(&mtt->ref_count);
  1785. qp->mtt = mtt;
  1786. atomic_inc(&rcq->ref_count);
  1787. qp->rcq = rcq;
  1788. atomic_inc(&scq->ref_count);
  1789. qp->scq = scq;
  1790. if (scqn != rcqn)
  1791. put_res(dev, slave, scqn, RES_CQ);
  1792. if (use_srq) {
  1793. atomic_inc(&srq->ref_count);
  1794. put_res(dev, slave, srqn, RES_SRQ);
  1795. qp->srq = srq;
  1796. }
  1797. put_res(dev, slave, rcqn, RES_CQ);
  1798. put_res(dev, slave, mtt_base, RES_MTT);
  1799. res_end_move(dev, slave, RES_QP, qpn);
  1800. return 0;
  1801. ex_put_srq:
  1802. if (use_srq)
  1803. put_res(dev, slave, srqn, RES_SRQ);
  1804. ex_put_scq:
  1805. if (scqn != rcqn)
  1806. put_res(dev, slave, scqn, RES_CQ);
  1807. ex_put_rcq:
  1808. put_res(dev, slave, rcqn, RES_CQ);
  1809. ex_put_mtt:
  1810. put_res(dev, slave, mtt_base, RES_MTT);
  1811. ex_abort:
  1812. res_abort_move(dev, slave, RES_QP, qpn);
  1813. return err;
  1814. }
  1815. static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
  1816. {
  1817. return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
  1818. }
  1819. static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
  1820. {
  1821. int log_eq_size = eqc->log_eq_size & 0x1f;
  1822. int page_shift = (eqc->log_page_size & 0x3f) + 12;
  1823. if (log_eq_size + 5 < page_shift)
  1824. return 1;
  1825. return 1 << (log_eq_size + 5 - page_shift);
  1826. }
  1827. static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
  1828. {
  1829. return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
  1830. }
  1831. static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
  1832. {
  1833. int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
  1834. int page_shift = (cqc->log_page_size & 0x3f) + 12;
  1835. if (log_cq_size + 5 < page_shift)
  1836. return 1;
  1837. return 1 << (log_cq_size + 5 - page_shift);
  1838. }
  1839. int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1840. struct mlx4_vhcr *vhcr,
  1841. struct mlx4_cmd_mailbox *inbox,
  1842. struct mlx4_cmd_mailbox *outbox,
  1843. struct mlx4_cmd_info *cmd)
  1844. {
  1845. int err;
  1846. int eqn = vhcr->in_modifier;
  1847. int res_id = (slave << 8) | eqn;
  1848. struct mlx4_eq_context *eqc = inbox->buf;
  1849. int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
  1850. int mtt_size = eq_get_mtt_size(eqc);
  1851. struct res_eq *eq;
  1852. struct res_mtt *mtt;
  1853. err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1854. if (err)
  1855. return err;
  1856. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
  1857. if (err)
  1858. goto out_add;
  1859. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1860. if (err)
  1861. goto out_move;
  1862. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1863. if (err)
  1864. goto out_put;
  1865. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1866. if (err)
  1867. goto out_put;
  1868. atomic_inc(&mtt->ref_count);
  1869. eq->mtt = mtt;
  1870. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1871. res_end_move(dev, slave, RES_EQ, res_id);
  1872. return 0;
  1873. out_put:
  1874. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1875. out_move:
  1876. res_abort_move(dev, slave, RES_EQ, res_id);
  1877. out_add:
  1878. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1879. return err;
  1880. }
  1881. static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
  1882. int len, struct res_mtt **res)
  1883. {
  1884. struct mlx4_priv *priv = mlx4_priv(dev);
  1885. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1886. struct res_mtt *mtt;
  1887. int err = -EINVAL;
  1888. spin_lock_irq(mlx4_tlock(dev));
  1889. list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
  1890. com.list) {
  1891. if (!check_mtt_range(dev, slave, start, len, mtt)) {
  1892. *res = mtt;
  1893. mtt->com.from_state = mtt->com.state;
  1894. mtt->com.state = RES_MTT_BUSY;
  1895. err = 0;
  1896. break;
  1897. }
  1898. }
  1899. spin_unlock_irq(mlx4_tlock(dev));
  1900. return err;
  1901. }
  1902. static int verify_qp_parameters(struct mlx4_dev *dev,
  1903. struct mlx4_cmd_mailbox *inbox,
  1904. enum qp_transition transition, u8 slave)
  1905. {
  1906. u32 qp_type;
  1907. struct mlx4_qp_context *qp_ctx;
  1908. enum mlx4_qp_optpar optpar;
  1909. qp_ctx = inbox->buf + 8;
  1910. qp_type = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  1911. optpar = be32_to_cpu(*(__be32 *) inbox->buf);
  1912. switch (qp_type) {
  1913. case MLX4_QP_ST_RC:
  1914. case MLX4_QP_ST_UC:
  1915. switch (transition) {
  1916. case QP_TRANS_INIT2RTR:
  1917. case QP_TRANS_RTR2RTS:
  1918. case QP_TRANS_RTS2RTS:
  1919. case QP_TRANS_SQD2SQD:
  1920. case QP_TRANS_SQD2RTS:
  1921. if (slave != mlx4_master_func_num(dev))
  1922. /* slaves have only gid index 0 */
  1923. if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH)
  1924. if (qp_ctx->pri_path.mgid_index)
  1925. return -EINVAL;
  1926. if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH)
  1927. if (qp_ctx->alt_path.mgid_index)
  1928. return -EINVAL;
  1929. break;
  1930. default:
  1931. break;
  1932. }
  1933. break;
  1934. default:
  1935. break;
  1936. }
  1937. return 0;
  1938. }
  1939. int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
  1940. struct mlx4_vhcr *vhcr,
  1941. struct mlx4_cmd_mailbox *inbox,
  1942. struct mlx4_cmd_mailbox *outbox,
  1943. struct mlx4_cmd_info *cmd)
  1944. {
  1945. struct mlx4_mtt mtt;
  1946. __be64 *page_list = inbox->buf;
  1947. u64 *pg_list = (u64 *)page_list;
  1948. int i;
  1949. struct res_mtt *rmtt = NULL;
  1950. int start = be64_to_cpu(page_list[0]);
  1951. int npages = vhcr->in_modifier;
  1952. int err;
  1953. err = get_containing_mtt(dev, slave, start, npages, &rmtt);
  1954. if (err)
  1955. return err;
  1956. /* Call the SW implementation of write_mtt:
  1957. * - Prepare a dummy mtt struct
  1958. * - Translate inbox contents to simple addresses in host endianess */
  1959. mtt.offset = 0; /* TBD this is broken but I don't handle it since
  1960. we don't really use it */
  1961. mtt.order = 0;
  1962. mtt.page_shift = 0;
  1963. for (i = 0; i < npages; ++i)
  1964. pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
  1965. err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
  1966. ((u64 *)page_list + 2));
  1967. if (rmtt)
  1968. put_res(dev, slave, rmtt->com.res_id, RES_MTT);
  1969. return err;
  1970. }
  1971. int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1972. struct mlx4_vhcr *vhcr,
  1973. struct mlx4_cmd_mailbox *inbox,
  1974. struct mlx4_cmd_mailbox *outbox,
  1975. struct mlx4_cmd_info *cmd)
  1976. {
  1977. int eqn = vhcr->in_modifier;
  1978. int res_id = eqn | (slave << 8);
  1979. struct res_eq *eq;
  1980. int err;
  1981. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
  1982. if (err)
  1983. return err;
  1984. err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
  1985. if (err)
  1986. goto ex_abort;
  1987. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1988. if (err)
  1989. goto ex_put;
  1990. atomic_dec(&eq->mtt->ref_count);
  1991. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1992. res_end_move(dev, slave, RES_EQ, res_id);
  1993. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1994. return 0;
  1995. ex_put:
  1996. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1997. ex_abort:
  1998. res_abort_move(dev, slave, RES_EQ, res_id);
  1999. return err;
  2000. }
  2001. int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
  2002. {
  2003. struct mlx4_priv *priv = mlx4_priv(dev);
  2004. struct mlx4_slave_event_eq_info *event_eq;
  2005. struct mlx4_cmd_mailbox *mailbox;
  2006. u32 in_modifier = 0;
  2007. int err;
  2008. int res_id;
  2009. struct res_eq *req;
  2010. if (!priv->mfunc.master.slave_state)
  2011. return -EINVAL;
  2012. event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
  2013. /* Create the event only if the slave is registered */
  2014. if (event_eq->eqn < 0)
  2015. return 0;
  2016. mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  2017. res_id = (slave << 8) | event_eq->eqn;
  2018. err = get_res(dev, slave, res_id, RES_EQ, &req);
  2019. if (err)
  2020. goto unlock;
  2021. if (req->com.from_state != RES_EQ_HW) {
  2022. err = -EINVAL;
  2023. goto put;
  2024. }
  2025. mailbox = mlx4_alloc_cmd_mailbox(dev);
  2026. if (IS_ERR(mailbox)) {
  2027. err = PTR_ERR(mailbox);
  2028. goto put;
  2029. }
  2030. if (eqe->type == MLX4_EVENT_TYPE_CMD) {
  2031. ++event_eq->token;
  2032. eqe->event.cmd.token = cpu_to_be16(event_eq->token);
  2033. }
  2034. memcpy(mailbox->buf, (u8 *) eqe, 28);
  2035. in_modifier = (slave & 0xff) | ((event_eq->eqn & 0xff) << 16);
  2036. err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
  2037. MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
  2038. MLX4_CMD_NATIVE);
  2039. put_res(dev, slave, res_id, RES_EQ);
  2040. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  2041. mlx4_free_cmd_mailbox(dev, mailbox);
  2042. return err;
  2043. put:
  2044. put_res(dev, slave, res_id, RES_EQ);
  2045. unlock:
  2046. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  2047. return err;
  2048. }
  2049. int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
  2050. struct mlx4_vhcr *vhcr,
  2051. struct mlx4_cmd_mailbox *inbox,
  2052. struct mlx4_cmd_mailbox *outbox,
  2053. struct mlx4_cmd_info *cmd)
  2054. {
  2055. int eqn = vhcr->in_modifier;
  2056. int res_id = eqn | (slave << 8);
  2057. struct res_eq *eq;
  2058. int err;
  2059. err = get_res(dev, slave, res_id, RES_EQ, &eq);
  2060. if (err)
  2061. return err;
  2062. if (eq->com.from_state != RES_EQ_HW) {
  2063. err = -EINVAL;
  2064. goto ex_put;
  2065. }
  2066. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2067. ex_put:
  2068. put_res(dev, slave, res_id, RES_EQ);
  2069. return err;
  2070. }
  2071. int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2072. struct mlx4_vhcr *vhcr,
  2073. struct mlx4_cmd_mailbox *inbox,
  2074. struct mlx4_cmd_mailbox *outbox,
  2075. struct mlx4_cmd_info *cmd)
  2076. {
  2077. int err;
  2078. int cqn = vhcr->in_modifier;
  2079. struct mlx4_cq_context *cqc = inbox->buf;
  2080. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  2081. struct res_cq *cq;
  2082. struct res_mtt *mtt;
  2083. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
  2084. if (err)
  2085. return err;
  2086. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2087. if (err)
  2088. goto out_move;
  2089. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  2090. if (err)
  2091. goto out_put;
  2092. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2093. if (err)
  2094. goto out_put;
  2095. atomic_inc(&mtt->ref_count);
  2096. cq->mtt = mtt;
  2097. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2098. res_end_move(dev, slave, RES_CQ, cqn);
  2099. return 0;
  2100. out_put:
  2101. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2102. out_move:
  2103. res_abort_move(dev, slave, RES_CQ, cqn);
  2104. return err;
  2105. }
  2106. int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2107. struct mlx4_vhcr *vhcr,
  2108. struct mlx4_cmd_mailbox *inbox,
  2109. struct mlx4_cmd_mailbox *outbox,
  2110. struct mlx4_cmd_info *cmd)
  2111. {
  2112. int err;
  2113. int cqn = vhcr->in_modifier;
  2114. struct res_cq *cq;
  2115. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
  2116. if (err)
  2117. return err;
  2118. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2119. if (err)
  2120. goto out_move;
  2121. atomic_dec(&cq->mtt->ref_count);
  2122. res_end_move(dev, slave, RES_CQ, cqn);
  2123. return 0;
  2124. out_move:
  2125. res_abort_move(dev, slave, RES_CQ, cqn);
  2126. return err;
  2127. }
  2128. int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2129. struct mlx4_vhcr *vhcr,
  2130. struct mlx4_cmd_mailbox *inbox,
  2131. struct mlx4_cmd_mailbox *outbox,
  2132. struct mlx4_cmd_info *cmd)
  2133. {
  2134. int cqn = vhcr->in_modifier;
  2135. struct res_cq *cq;
  2136. int err;
  2137. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  2138. if (err)
  2139. return err;
  2140. if (cq->com.from_state != RES_CQ_HW)
  2141. goto ex_put;
  2142. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2143. ex_put:
  2144. put_res(dev, slave, cqn, RES_CQ);
  2145. return err;
  2146. }
  2147. static int handle_resize(struct mlx4_dev *dev, int slave,
  2148. struct mlx4_vhcr *vhcr,
  2149. struct mlx4_cmd_mailbox *inbox,
  2150. struct mlx4_cmd_mailbox *outbox,
  2151. struct mlx4_cmd_info *cmd,
  2152. struct res_cq *cq)
  2153. {
  2154. int err;
  2155. struct res_mtt *orig_mtt;
  2156. struct res_mtt *mtt;
  2157. struct mlx4_cq_context *cqc = inbox->buf;
  2158. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  2159. err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
  2160. if (err)
  2161. return err;
  2162. if (orig_mtt != cq->mtt) {
  2163. err = -EINVAL;
  2164. goto ex_put;
  2165. }
  2166. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2167. if (err)
  2168. goto ex_put;
  2169. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  2170. if (err)
  2171. goto ex_put1;
  2172. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2173. if (err)
  2174. goto ex_put1;
  2175. atomic_dec(&orig_mtt->ref_count);
  2176. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  2177. atomic_inc(&mtt->ref_count);
  2178. cq->mtt = mtt;
  2179. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2180. return 0;
  2181. ex_put1:
  2182. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2183. ex_put:
  2184. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  2185. return err;
  2186. }
  2187. int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2188. struct mlx4_vhcr *vhcr,
  2189. struct mlx4_cmd_mailbox *inbox,
  2190. struct mlx4_cmd_mailbox *outbox,
  2191. struct mlx4_cmd_info *cmd)
  2192. {
  2193. int cqn = vhcr->in_modifier;
  2194. struct res_cq *cq;
  2195. int err;
  2196. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  2197. if (err)
  2198. return err;
  2199. if (cq->com.from_state != RES_CQ_HW)
  2200. goto ex_put;
  2201. if (vhcr->op_modifier == 0) {
  2202. err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
  2203. goto ex_put;
  2204. }
  2205. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2206. ex_put:
  2207. put_res(dev, slave, cqn, RES_CQ);
  2208. return err;
  2209. }
  2210. static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
  2211. {
  2212. int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
  2213. int log_rq_stride = srqc->logstride & 7;
  2214. int page_shift = (srqc->log_page_size & 0x3f) + 12;
  2215. if (log_srq_size + log_rq_stride + 4 < page_shift)
  2216. return 1;
  2217. return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
  2218. }
  2219. int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2220. struct mlx4_vhcr *vhcr,
  2221. struct mlx4_cmd_mailbox *inbox,
  2222. struct mlx4_cmd_mailbox *outbox,
  2223. struct mlx4_cmd_info *cmd)
  2224. {
  2225. int err;
  2226. int srqn = vhcr->in_modifier;
  2227. struct res_mtt *mtt;
  2228. struct res_srq *srq;
  2229. struct mlx4_srq_context *srqc = inbox->buf;
  2230. int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
  2231. if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
  2232. return -EINVAL;
  2233. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
  2234. if (err)
  2235. return err;
  2236. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2237. if (err)
  2238. goto ex_abort;
  2239. err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
  2240. mtt);
  2241. if (err)
  2242. goto ex_put_mtt;
  2243. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2244. if (err)
  2245. goto ex_put_mtt;
  2246. atomic_inc(&mtt->ref_count);
  2247. srq->mtt = mtt;
  2248. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2249. res_end_move(dev, slave, RES_SRQ, srqn);
  2250. return 0;
  2251. ex_put_mtt:
  2252. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2253. ex_abort:
  2254. res_abort_move(dev, slave, RES_SRQ, srqn);
  2255. return err;
  2256. }
  2257. int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2258. struct mlx4_vhcr *vhcr,
  2259. struct mlx4_cmd_mailbox *inbox,
  2260. struct mlx4_cmd_mailbox *outbox,
  2261. struct mlx4_cmd_info *cmd)
  2262. {
  2263. int err;
  2264. int srqn = vhcr->in_modifier;
  2265. struct res_srq *srq;
  2266. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
  2267. if (err)
  2268. return err;
  2269. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2270. if (err)
  2271. goto ex_abort;
  2272. atomic_dec(&srq->mtt->ref_count);
  2273. if (srq->cq)
  2274. atomic_dec(&srq->cq->ref_count);
  2275. res_end_move(dev, slave, RES_SRQ, srqn);
  2276. return 0;
  2277. ex_abort:
  2278. res_abort_move(dev, slave, RES_SRQ, srqn);
  2279. return err;
  2280. }
  2281. int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2282. struct mlx4_vhcr *vhcr,
  2283. struct mlx4_cmd_mailbox *inbox,
  2284. struct mlx4_cmd_mailbox *outbox,
  2285. struct mlx4_cmd_info *cmd)
  2286. {
  2287. int err;
  2288. int srqn = vhcr->in_modifier;
  2289. struct res_srq *srq;
  2290. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2291. if (err)
  2292. return err;
  2293. if (srq->com.from_state != RES_SRQ_HW) {
  2294. err = -EBUSY;
  2295. goto out;
  2296. }
  2297. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2298. out:
  2299. put_res(dev, slave, srqn, RES_SRQ);
  2300. return err;
  2301. }
  2302. int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2303. struct mlx4_vhcr *vhcr,
  2304. struct mlx4_cmd_mailbox *inbox,
  2305. struct mlx4_cmd_mailbox *outbox,
  2306. struct mlx4_cmd_info *cmd)
  2307. {
  2308. int err;
  2309. int srqn = vhcr->in_modifier;
  2310. struct res_srq *srq;
  2311. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2312. if (err)
  2313. return err;
  2314. if (srq->com.from_state != RES_SRQ_HW) {
  2315. err = -EBUSY;
  2316. goto out;
  2317. }
  2318. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2319. out:
  2320. put_res(dev, slave, srqn, RES_SRQ);
  2321. return err;
  2322. }
  2323. int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
  2324. struct mlx4_vhcr *vhcr,
  2325. struct mlx4_cmd_mailbox *inbox,
  2326. struct mlx4_cmd_mailbox *outbox,
  2327. struct mlx4_cmd_info *cmd)
  2328. {
  2329. int err;
  2330. int qpn = vhcr->in_modifier & 0x7fffff;
  2331. struct res_qp *qp;
  2332. err = get_res(dev, slave, qpn, RES_QP, &qp);
  2333. if (err)
  2334. return err;
  2335. if (qp->com.from_state != RES_QP_HW) {
  2336. err = -EBUSY;
  2337. goto out;
  2338. }
  2339. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2340. out:
  2341. put_res(dev, slave, qpn, RES_QP);
  2342. return err;
  2343. }
  2344. int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  2345. struct mlx4_vhcr *vhcr,
  2346. struct mlx4_cmd_mailbox *inbox,
  2347. struct mlx4_cmd_mailbox *outbox,
  2348. struct mlx4_cmd_info *cmd)
  2349. {
  2350. struct mlx4_qp_context *context = inbox->buf + 8;
  2351. adjust_proxy_tun_qkey(dev, vhcr, context);
  2352. update_pkey_index(dev, slave, inbox);
  2353. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2354. }
  2355. int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
  2356. struct mlx4_vhcr *vhcr,
  2357. struct mlx4_cmd_mailbox *inbox,
  2358. struct mlx4_cmd_mailbox *outbox,
  2359. struct mlx4_cmd_info *cmd)
  2360. {
  2361. int err;
  2362. struct mlx4_qp_context *qpc = inbox->buf + 8;
  2363. err = verify_qp_parameters(dev, inbox, QP_TRANS_INIT2RTR, slave);
  2364. if (err)
  2365. return err;
  2366. update_pkey_index(dev, slave, inbox);
  2367. update_gid(dev, inbox, (u8)slave);
  2368. adjust_proxy_tun_qkey(dev, vhcr, qpc);
  2369. err = update_vport_qp_param(dev, inbox, slave);
  2370. if (err)
  2371. return err;
  2372. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2373. }
  2374. int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2375. struct mlx4_vhcr *vhcr,
  2376. struct mlx4_cmd_mailbox *inbox,
  2377. struct mlx4_cmd_mailbox *outbox,
  2378. struct mlx4_cmd_info *cmd)
  2379. {
  2380. int err;
  2381. struct mlx4_qp_context *context = inbox->buf + 8;
  2382. err = verify_qp_parameters(dev, inbox, QP_TRANS_RTR2RTS, slave);
  2383. if (err)
  2384. return err;
  2385. update_pkey_index(dev, slave, inbox);
  2386. update_gid(dev, inbox, (u8)slave);
  2387. adjust_proxy_tun_qkey(dev, vhcr, context);
  2388. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2389. }
  2390. int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2391. struct mlx4_vhcr *vhcr,
  2392. struct mlx4_cmd_mailbox *inbox,
  2393. struct mlx4_cmd_mailbox *outbox,
  2394. struct mlx4_cmd_info *cmd)
  2395. {
  2396. int err;
  2397. struct mlx4_qp_context *context = inbox->buf + 8;
  2398. err = verify_qp_parameters(dev, inbox, QP_TRANS_RTS2RTS, slave);
  2399. if (err)
  2400. return err;
  2401. update_pkey_index(dev, slave, inbox);
  2402. update_gid(dev, inbox, (u8)slave);
  2403. adjust_proxy_tun_qkey(dev, vhcr, context);
  2404. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2405. }
  2406. int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2407. struct mlx4_vhcr *vhcr,
  2408. struct mlx4_cmd_mailbox *inbox,
  2409. struct mlx4_cmd_mailbox *outbox,
  2410. struct mlx4_cmd_info *cmd)
  2411. {
  2412. struct mlx4_qp_context *context = inbox->buf + 8;
  2413. adjust_proxy_tun_qkey(dev, vhcr, context);
  2414. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2415. }
  2416. int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
  2417. struct mlx4_vhcr *vhcr,
  2418. struct mlx4_cmd_mailbox *inbox,
  2419. struct mlx4_cmd_mailbox *outbox,
  2420. struct mlx4_cmd_info *cmd)
  2421. {
  2422. int err;
  2423. struct mlx4_qp_context *context = inbox->buf + 8;
  2424. err = verify_qp_parameters(dev, inbox, QP_TRANS_SQD2SQD, slave);
  2425. if (err)
  2426. return err;
  2427. adjust_proxy_tun_qkey(dev, vhcr, context);
  2428. update_gid(dev, inbox, (u8)slave);
  2429. update_pkey_index(dev, slave, inbox);
  2430. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2431. }
  2432. int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2433. struct mlx4_vhcr *vhcr,
  2434. struct mlx4_cmd_mailbox *inbox,
  2435. struct mlx4_cmd_mailbox *outbox,
  2436. struct mlx4_cmd_info *cmd)
  2437. {
  2438. int err;
  2439. struct mlx4_qp_context *context = inbox->buf + 8;
  2440. err = verify_qp_parameters(dev, inbox, QP_TRANS_SQD2RTS, slave);
  2441. if (err)
  2442. return err;
  2443. adjust_proxy_tun_qkey(dev, vhcr, context);
  2444. update_gid(dev, inbox, (u8)slave);
  2445. update_pkey_index(dev, slave, inbox);
  2446. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2447. }
  2448. int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
  2449. struct mlx4_vhcr *vhcr,
  2450. struct mlx4_cmd_mailbox *inbox,
  2451. struct mlx4_cmd_mailbox *outbox,
  2452. struct mlx4_cmd_info *cmd)
  2453. {
  2454. int err;
  2455. int qpn = vhcr->in_modifier & 0x7fffff;
  2456. struct res_qp *qp;
  2457. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
  2458. if (err)
  2459. return err;
  2460. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2461. if (err)
  2462. goto ex_abort;
  2463. atomic_dec(&qp->mtt->ref_count);
  2464. atomic_dec(&qp->rcq->ref_count);
  2465. atomic_dec(&qp->scq->ref_count);
  2466. if (qp->srq)
  2467. atomic_dec(&qp->srq->ref_count);
  2468. res_end_move(dev, slave, RES_QP, qpn);
  2469. return 0;
  2470. ex_abort:
  2471. res_abort_move(dev, slave, RES_QP, qpn);
  2472. return err;
  2473. }
  2474. static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
  2475. struct res_qp *rqp, u8 *gid)
  2476. {
  2477. struct res_gid *res;
  2478. list_for_each_entry(res, &rqp->mcg_list, list) {
  2479. if (!memcmp(res->gid, gid, 16))
  2480. return res;
  2481. }
  2482. return NULL;
  2483. }
  2484. static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2485. u8 *gid, enum mlx4_protocol prot,
  2486. enum mlx4_steer_type steer, u64 reg_id)
  2487. {
  2488. struct res_gid *res;
  2489. int err;
  2490. res = kzalloc(sizeof *res, GFP_KERNEL);
  2491. if (!res)
  2492. return -ENOMEM;
  2493. spin_lock_irq(&rqp->mcg_spl);
  2494. if (find_gid(dev, slave, rqp, gid)) {
  2495. kfree(res);
  2496. err = -EEXIST;
  2497. } else {
  2498. memcpy(res->gid, gid, 16);
  2499. res->prot = prot;
  2500. res->steer = steer;
  2501. res->reg_id = reg_id;
  2502. list_add_tail(&res->list, &rqp->mcg_list);
  2503. err = 0;
  2504. }
  2505. spin_unlock_irq(&rqp->mcg_spl);
  2506. return err;
  2507. }
  2508. static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2509. u8 *gid, enum mlx4_protocol prot,
  2510. enum mlx4_steer_type steer, u64 *reg_id)
  2511. {
  2512. struct res_gid *res;
  2513. int err;
  2514. spin_lock_irq(&rqp->mcg_spl);
  2515. res = find_gid(dev, slave, rqp, gid);
  2516. if (!res || res->prot != prot || res->steer != steer)
  2517. err = -EINVAL;
  2518. else {
  2519. *reg_id = res->reg_id;
  2520. list_del(&res->list);
  2521. kfree(res);
  2522. err = 0;
  2523. }
  2524. spin_unlock_irq(&rqp->mcg_spl);
  2525. return err;
  2526. }
  2527. static int qp_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
  2528. int block_loopback, enum mlx4_protocol prot,
  2529. enum mlx4_steer_type type, u64 *reg_id)
  2530. {
  2531. switch (dev->caps.steering_mode) {
  2532. case MLX4_STEERING_MODE_DEVICE_MANAGED:
  2533. return mlx4_trans_to_dmfs_attach(dev, qp, gid, gid[5],
  2534. block_loopback, prot,
  2535. reg_id);
  2536. case MLX4_STEERING_MODE_B0:
  2537. return mlx4_qp_attach_common(dev, qp, gid,
  2538. block_loopback, prot, type);
  2539. default:
  2540. return -EINVAL;
  2541. }
  2542. }
  2543. static int qp_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
  2544. enum mlx4_protocol prot, enum mlx4_steer_type type,
  2545. u64 reg_id)
  2546. {
  2547. switch (dev->caps.steering_mode) {
  2548. case MLX4_STEERING_MODE_DEVICE_MANAGED:
  2549. return mlx4_flow_detach(dev, reg_id);
  2550. case MLX4_STEERING_MODE_B0:
  2551. return mlx4_qp_detach_common(dev, qp, gid, prot, type);
  2552. default:
  2553. return -EINVAL;
  2554. }
  2555. }
  2556. int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2557. struct mlx4_vhcr *vhcr,
  2558. struct mlx4_cmd_mailbox *inbox,
  2559. struct mlx4_cmd_mailbox *outbox,
  2560. struct mlx4_cmd_info *cmd)
  2561. {
  2562. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2563. u8 *gid = inbox->buf;
  2564. enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
  2565. int err;
  2566. int qpn;
  2567. struct res_qp *rqp;
  2568. u64 reg_id = 0;
  2569. int attach = vhcr->op_modifier;
  2570. int block_loopback = vhcr->in_modifier >> 31;
  2571. u8 steer_type_mask = 2;
  2572. enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
  2573. qpn = vhcr->in_modifier & 0xffffff;
  2574. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  2575. if (err)
  2576. return err;
  2577. qp.qpn = qpn;
  2578. if (attach) {
  2579. err = qp_attach(dev, &qp, gid, block_loopback, prot,
  2580. type, &reg_id);
  2581. if (err) {
  2582. pr_err("Fail to attach rule to qp 0x%x\n", qpn);
  2583. goto ex_put;
  2584. }
  2585. err = add_mcg_res(dev, slave, rqp, gid, prot, type, reg_id);
  2586. if (err)
  2587. goto ex_detach;
  2588. } else {
  2589. err = rem_mcg_res(dev, slave, rqp, gid, prot, type, &reg_id);
  2590. if (err)
  2591. goto ex_put;
  2592. err = qp_detach(dev, &qp, gid, prot, type, reg_id);
  2593. if (err)
  2594. pr_err("Fail to detach rule from qp 0x%x reg_id = 0x%llx\n",
  2595. qpn, reg_id);
  2596. }
  2597. put_res(dev, slave, qpn, RES_QP);
  2598. return err;
  2599. ex_detach:
  2600. qp_detach(dev, &qp, gid, prot, type, reg_id);
  2601. ex_put:
  2602. put_res(dev, slave, qpn, RES_QP);
  2603. return err;
  2604. }
  2605. /*
  2606. * MAC validation for Flow Steering rules.
  2607. * VF can attach rules only with a mac address which is assigned to it.
  2608. */
  2609. static int validate_eth_header_mac(int slave, struct _rule_hw *eth_header,
  2610. struct list_head *rlist)
  2611. {
  2612. struct mac_res *res, *tmp;
  2613. __be64 be_mac;
  2614. /* make sure it isn't multicast or broadcast mac*/
  2615. if (!is_multicast_ether_addr(eth_header->eth.dst_mac) &&
  2616. !is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
  2617. list_for_each_entry_safe(res, tmp, rlist, list) {
  2618. be_mac = cpu_to_be64(res->mac << 16);
  2619. if (!memcmp(&be_mac, eth_header->eth.dst_mac, ETH_ALEN))
  2620. return 0;
  2621. }
  2622. pr_err("MAC %pM doesn't belong to VF %d, Steering rule rejected\n",
  2623. eth_header->eth.dst_mac, slave);
  2624. return -EINVAL;
  2625. }
  2626. return 0;
  2627. }
  2628. /*
  2629. * In case of missing eth header, append eth header with a MAC address
  2630. * assigned to the VF.
  2631. */
  2632. static int add_eth_header(struct mlx4_dev *dev, int slave,
  2633. struct mlx4_cmd_mailbox *inbox,
  2634. struct list_head *rlist, int header_id)
  2635. {
  2636. struct mac_res *res, *tmp;
  2637. u8 port;
  2638. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  2639. struct mlx4_net_trans_rule_hw_eth *eth_header;
  2640. struct mlx4_net_trans_rule_hw_ipv4 *ip_header;
  2641. struct mlx4_net_trans_rule_hw_tcp_udp *l4_header;
  2642. __be64 be_mac = 0;
  2643. __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
  2644. ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
  2645. port = ctrl->port;
  2646. eth_header = (struct mlx4_net_trans_rule_hw_eth *)(ctrl + 1);
  2647. /* Clear a space in the inbox for eth header */
  2648. switch (header_id) {
  2649. case MLX4_NET_TRANS_RULE_ID_IPV4:
  2650. ip_header =
  2651. (struct mlx4_net_trans_rule_hw_ipv4 *)(eth_header + 1);
  2652. memmove(ip_header, eth_header,
  2653. sizeof(*ip_header) + sizeof(*l4_header));
  2654. break;
  2655. case MLX4_NET_TRANS_RULE_ID_TCP:
  2656. case MLX4_NET_TRANS_RULE_ID_UDP:
  2657. l4_header = (struct mlx4_net_trans_rule_hw_tcp_udp *)
  2658. (eth_header + 1);
  2659. memmove(l4_header, eth_header, sizeof(*l4_header));
  2660. break;
  2661. default:
  2662. return -EINVAL;
  2663. }
  2664. list_for_each_entry_safe(res, tmp, rlist, list) {
  2665. if (port == res->port) {
  2666. be_mac = cpu_to_be64(res->mac << 16);
  2667. break;
  2668. }
  2669. }
  2670. if (!be_mac) {
  2671. pr_err("Failed adding eth header to FS rule, Can't find matching MAC for port %d .\n",
  2672. port);
  2673. return -EINVAL;
  2674. }
  2675. memset(eth_header, 0, sizeof(*eth_header));
  2676. eth_header->size = sizeof(*eth_header) >> 2;
  2677. eth_header->id = cpu_to_be16(__sw_id_hw[MLX4_NET_TRANS_RULE_ID_ETH]);
  2678. memcpy(eth_header->dst_mac, &be_mac, ETH_ALEN);
  2679. memcpy(eth_header->dst_mac_msk, &mac_msk, ETH_ALEN);
  2680. return 0;
  2681. }
  2682. int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2683. struct mlx4_vhcr *vhcr,
  2684. struct mlx4_cmd_mailbox *inbox,
  2685. struct mlx4_cmd_mailbox *outbox,
  2686. struct mlx4_cmd_info *cmd)
  2687. {
  2688. struct mlx4_priv *priv = mlx4_priv(dev);
  2689. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2690. struct list_head *rlist = &tracker->slave_list[slave].res_list[RES_MAC];
  2691. int err;
  2692. int qpn;
  2693. struct res_qp *rqp;
  2694. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  2695. struct _rule_hw *rule_header;
  2696. int header_id;
  2697. if (dev->caps.steering_mode !=
  2698. MLX4_STEERING_MODE_DEVICE_MANAGED)
  2699. return -EOPNOTSUPP;
  2700. ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
  2701. qpn = be32_to_cpu(ctrl->qpn) & 0xffffff;
  2702. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  2703. if (err) {
  2704. pr_err("Steering rule with qpn 0x%x rejected.\n", qpn);
  2705. return err;
  2706. }
  2707. rule_header = (struct _rule_hw *)(ctrl + 1);
  2708. header_id = map_hw_to_sw_id(be16_to_cpu(rule_header->id));
  2709. switch (header_id) {
  2710. case MLX4_NET_TRANS_RULE_ID_ETH:
  2711. if (validate_eth_header_mac(slave, rule_header, rlist)) {
  2712. err = -EINVAL;
  2713. goto err_put;
  2714. }
  2715. break;
  2716. case MLX4_NET_TRANS_RULE_ID_IB:
  2717. break;
  2718. case MLX4_NET_TRANS_RULE_ID_IPV4:
  2719. case MLX4_NET_TRANS_RULE_ID_TCP:
  2720. case MLX4_NET_TRANS_RULE_ID_UDP:
  2721. pr_warn("Can't attach FS rule without L2 headers, adding L2 header.\n");
  2722. if (add_eth_header(dev, slave, inbox, rlist, header_id)) {
  2723. err = -EINVAL;
  2724. goto err_put;
  2725. }
  2726. vhcr->in_modifier +=
  2727. sizeof(struct mlx4_net_trans_rule_hw_eth) >> 2;
  2728. break;
  2729. default:
  2730. pr_err("Corrupted mailbox.\n");
  2731. err = -EINVAL;
  2732. goto err_put;
  2733. }
  2734. err = mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
  2735. vhcr->in_modifier, 0,
  2736. MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
  2737. MLX4_CMD_NATIVE);
  2738. if (err)
  2739. goto err_put;
  2740. err = add_res_range(dev, slave, vhcr->out_param, 1, RES_FS_RULE, qpn);
  2741. if (err) {
  2742. mlx4_err(dev, "Fail to add flow steering resources.\n ");
  2743. /* detach rule*/
  2744. mlx4_cmd(dev, vhcr->out_param, 0, 0,
  2745. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  2746. MLX4_CMD_NATIVE);
  2747. goto err_put;
  2748. }
  2749. atomic_inc(&rqp->ref_count);
  2750. err_put:
  2751. put_res(dev, slave, qpn, RES_QP);
  2752. return err;
  2753. }
  2754. int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
  2755. struct mlx4_vhcr *vhcr,
  2756. struct mlx4_cmd_mailbox *inbox,
  2757. struct mlx4_cmd_mailbox *outbox,
  2758. struct mlx4_cmd_info *cmd)
  2759. {
  2760. int err;
  2761. struct res_qp *rqp;
  2762. struct res_fs_rule *rrule;
  2763. if (dev->caps.steering_mode !=
  2764. MLX4_STEERING_MODE_DEVICE_MANAGED)
  2765. return -EOPNOTSUPP;
  2766. err = get_res(dev, slave, vhcr->in_param, RES_FS_RULE, &rrule);
  2767. if (err)
  2768. return err;
  2769. /* Release the rule form busy state before removal */
  2770. put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
  2771. err = get_res(dev, slave, rrule->qpn, RES_QP, &rqp);
  2772. if (err)
  2773. return err;
  2774. err = rem_res_range(dev, slave, vhcr->in_param, 1, RES_FS_RULE, 0);
  2775. if (err) {
  2776. mlx4_err(dev, "Fail to remove flow steering resources.\n ");
  2777. goto out;
  2778. }
  2779. err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
  2780. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  2781. MLX4_CMD_NATIVE);
  2782. if (!err)
  2783. atomic_dec(&rqp->ref_count);
  2784. out:
  2785. put_res(dev, slave, rrule->qpn, RES_QP);
  2786. return err;
  2787. }
  2788. enum {
  2789. BUSY_MAX_RETRIES = 10
  2790. };
  2791. int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
  2792. struct mlx4_vhcr *vhcr,
  2793. struct mlx4_cmd_mailbox *inbox,
  2794. struct mlx4_cmd_mailbox *outbox,
  2795. struct mlx4_cmd_info *cmd)
  2796. {
  2797. int err;
  2798. int index = vhcr->in_modifier & 0xffff;
  2799. err = get_res(dev, slave, index, RES_COUNTER, NULL);
  2800. if (err)
  2801. return err;
  2802. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2803. put_res(dev, slave, index, RES_COUNTER);
  2804. return err;
  2805. }
  2806. static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
  2807. {
  2808. struct res_gid *rgid;
  2809. struct res_gid *tmp;
  2810. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2811. list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
  2812. switch (dev->caps.steering_mode) {
  2813. case MLX4_STEERING_MODE_DEVICE_MANAGED:
  2814. mlx4_flow_detach(dev, rgid->reg_id);
  2815. break;
  2816. case MLX4_STEERING_MODE_B0:
  2817. qp.qpn = rqp->local_qpn;
  2818. (void) mlx4_qp_detach_common(dev, &qp, rgid->gid,
  2819. rgid->prot, rgid->steer);
  2820. break;
  2821. }
  2822. list_del(&rgid->list);
  2823. kfree(rgid);
  2824. }
  2825. }
  2826. static int _move_all_busy(struct mlx4_dev *dev, int slave,
  2827. enum mlx4_resource type, int print)
  2828. {
  2829. struct mlx4_priv *priv = mlx4_priv(dev);
  2830. struct mlx4_resource_tracker *tracker =
  2831. &priv->mfunc.master.res_tracker;
  2832. struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
  2833. struct res_common *r;
  2834. struct res_common *tmp;
  2835. int busy;
  2836. busy = 0;
  2837. spin_lock_irq(mlx4_tlock(dev));
  2838. list_for_each_entry_safe(r, tmp, rlist, list) {
  2839. if (r->owner == slave) {
  2840. if (!r->removing) {
  2841. if (r->state == RES_ANY_BUSY) {
  2842. if (print)
  2843. mlx4_dbg(dev,
  2844. "%s id 0x%llx is busy\n",
  2845. ResourceType(type),
  2846. r->res_id);
  2847. ++busy;
  2848. } else {
  2849. r->from_state = r->state;
  2850. r->state = RES_ANY_BUSY;
  2851. r->removing = 1;
  2852. }
  2853. }
  2854. }
  2855. }
  2856. spin_unlock_irq(mlx4_tlock(dev));
  2857. return busy;
  2858. }
  2859. static int move_all_busy(struct mlx4_dev *dev, int slave,
  2860. enum mlx4_resource type)
  2861. {
  2862. unsigned long begin;
  2863. int busy;
  2864. begin = jiffies;
  2865. do {
  2866. busy = _move_all_busy(dev, slave, type, 0);
  2867. if (time_after(jiffies, begin + 5 * HZ))
  2868. break;
  2869. if (busy)
  2870. cond_resched();
  2871. } while (busy);
  2872. if (busy)
  2873. busy = _move_all_busy(dev, slave, type, 1);
  2874. return busy;
  2875. }
  2876. static void rem_slave_qps(struct mlx4_dev *dev, int slave)
  2877. {
  2878. struct mlx4_priv *priv = mlx4_priv(dev);
  2879. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2880. struct list_head *qp_list =
  2881. &tracker->slave_list[slave].res_list[RES_QP];
  2882. struct res_qp *qp;
  2883. struct res_qp *tmp;
  2884. int state;
  2885. u64 in_param;
  2886. int qpn;
  2887. int err;
  2888. err = move_all_busy(dev, slave, RES_QP);
  2889. if (err)
  2890. mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy"
  2891. "for slave %d\n", slave);
  2892. spin_lock_irq(mlx4_tlock(dev));
  2893. list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
  2894. spin_unlock_irq(mlx4_tlock(dev));
  2895. if (qp->com.owner == slave) {
  2896. qpn = qp->com.res_id;
  2897. detach_qp(dev, slave, qp);
  2898. state = qp->com.from_state;
  2899. while (state != 0) {
  2900. switch (state) {
  2901. case RES_QP_RESERVED:
  2902. spin_lock_irq(mlx4_tlock(dev));
  2903. rb_erase(&qp->com.node,
  2904. &tracker->res_tree[RES_QP]);
  2905. list_del(&qp->com.list);
  2906. spin_unlock_irq(mlx4_tlock(dev));
  2907. kfree(qp);
  2908. state = 0;
  2909. break;
  2910. case RES_QP_MAPPED:
  2911. if (!valid_reserved(dev, slave, qpn))
  2912. __mlx4_qp_free_icm(dev, qpn);
  2913. state = RES_QP_RESERVED;
  2914. break;
  2915. case RES_QP_HW:
  2916. in_param = slave;
  2917. err = mlx4_cmd(dev, in_param,
  2918. qp->local_qpn, 2,
  2919. MLX4_CMD_2RST_QP,
  2920. MLX4_CMD_TIME_CLASS_A,
  2921. MLX4_CMD_NATIVE);
  2922. if (err)
  2923. mlx4_dbg(dev, "rem_slave_qps: failed"
  2924. " to move slave %d qpn %d to"
  2925. " reset\n", slave,
  2926. qp->local_qpn);
  2927. atomic_dec(&qp->rcq->ref_count);
  2928. atomic_dec(&qp->scq->ref_count);
  2929. atomic_dec(&qp->mtt->ref_count);
  2930. if (qp->srq)
  2931. atomic_dec(&qp->srq->ref_count);
  2932. state = RES_QP_MAPPED;
  2933. break;
  2934. default:
  2935. state = 0;
  2936. }
  2937. }
  2938. }
  2939. spin_lock_irq(mlx4_tlock(dev));
  2940. }
  2941. spin_unlock_irq(mlx4_tlock(dev));
  2942. }
  2943. static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
  2944. {
  2945. struct mlx4_priv *priv = mlx4_priv(dev);
  2946. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2947. struct list_head *srq_list =
  2948. &tracker->slave_list[slave].res_list[RES_SRQ];
  2949. struct res_srq *srq;
  2950. struct res_srq *tmp;
  2951. int state;
  2952. u64 in_param;
  2953. LIST_HEAD(tlist);
  2954. int srqn;
  2955. int err;
  2956. err = move_all_busy(dev, slave, RES_SRQ);
  2957. if (err)
  2958. mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs to "
  2959. "busy for slave %d\n", slave);
  2960. spin_lock_irq(mlx4_tlock(dev));
  2961. list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
  2962. spin_unlock_irq(mlx4_tlock(dev));
  2963. if (srq->com.owner == slave) {
  2964. srqn = srq->com.res_id;
  2965. state = srq->com.from_state;
  2966. while (state != 0) {
  2967. switch (state) {
  2968. case RES_SRQ_ALLOCATED:
  2969. __mlx4_srq_free_icm(dev, srqn);
  2970. spin_lock_irq(mlx4_tlock(dev));
  2971. rb_erase(&srq->com.node,
  2972. &tracker->res_tree[RES_SRQ]);
  2973. list_del(&srq->com.list);
  2974. spin_unlock_irq(mlx4_tlock(dev));
  2975. kfree(srq);
  2976. state = 0;
  2977. break;
  2978. case RES_SRQ_HW:
  2979. in_param = slave;
  2980. err = mlx4_cmd(dev, in_param, srqn, 1,
  2981. MLX4_CMD_HW2SW_SRQ,
  2982. MLX4_CMD_TIME_CLASS_A,
  2983. MLX4_CMD_NATIVE);
  2984. if (err)
  2985. mlx4_dbg(dev, "rem_slave_srqs: failed"
  2986. " to move slave %d srq %d to"
  2987. " SW ownership\n",
  2988. slave, srqn);
  2989. atomic_dec(&srq->mtt->ref_count);
  2990. if (srq->cq)
  2991. atomic_dec(&srq->cq->ref_count);
  2992. state = RES_SRQ_ALLOCATED;
  2993. break;
  2994. default:
  2995. state = 0;
  2996. }
  2997. }
  2998. }
  2999. spin_lock_irq(mlx4_tlock(dev));
  3000. }
  3001. spin_unlock_irq(mlx4_tlock(dev));
  3002. }
  3003. static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
  3004. {
  3005. struct mlx4_priv *priv = mlx4_priv(dev);
  3006. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3007. struct list_head *cq_list =
  3008. &tracker->slave_list[slave].res_list[RES_CQ];
  3009. struct res_cq *cq;
  3010. struct res_cq *tmp;
  3011. int state;
  3012. u64 in_param;
  3013. LIST_HEAD(tlist);
  3014. int cqn;
  3015. int err;
  3016. err = move_all_busy(dev, slave, RES_CQ);
  3017. if (err)
  3018. mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs to "
  3019. "busy for slave %d\n", slave);
  3020. spin_lock_irq(mlx4_tlock(dev));
  3021. list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
  3022. spin_unlock_irq(mlx4_tlock(dev));
  3023. if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
  3024. cqn = cq->com.res_id;
  3025. state = cq->com.from_state;
  3026. while (state != 0) {
  3027. switch (state) {
  3028. case RES_CQ_ALLOCATED:
  3029. __mlx4_cq_free_icm(dev, cqn);
  3030. spin_lock_irq(mlx4_tlock(dev));
  3031. rb_erase(&cq->com.node,
  3032. &tracker->res_tree[RES_CQ]);
  3033. list_del(&cq->com.list);
  3034. spin_unlock_irq(mlx4_tlock(dev));
  3035. kfree(cq);
  3036. state = 0;
  3037. break;
  3038. case RES_CQ_HW:
  3039. in_param = slave;
  3040. err = mlx4_cmd(dev, in_param, cqn, 1,
  3041. MLX4_CMD_HW2SW_CQ,
  3042. MLX4_CMD_TIME_CLASS_A,
  3043. MLX4_CMD_NATIVE);
  3044. if (err)
  3045. mlx4_dbg(dev, "rem_slave_cqs: failed"
  3046. " to move slave %d cq %d to"
  3047. " SW ownership\n",
  3048. slave, cqn);
  3049. atomic_dec(&cq->mtt->ref_count);
  3050. state = RES_CQ_ALLOCATED;
  3051. break;
  3052. default:
  3053. state = 0;
  3054. }
  3055. }
  3056. }
  3057. spin_lock_irq(mlx4_tlock(dev));
  3058. }
  3059. spin_unlock_irq(mlx4_tlock(dev));
  3060. }
  3061. static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
  3062. {
  3063. struct mlx4_priv *priv = mlx4_priv(dev);
  3064. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3065. struct list_head *mpt_list =
  3066. &tracker->slave_list[slave].res_list[RES_MPT];
  3067. struct res_mpt *mpt;
  3068. struct res_mpt *tmp;
  3069. int state;
  3070. u64 in_param;
  3071. LIST_HEAD(tlist);
  3072. int mptn;
  3073. int err;
  3074. err = move_all_busy(dev, slave, RES_MPT);
  3075. if (err)
  3076. mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts to "
  3077. "busy for slave %d\n", slave);
  3078. spin_lock_irq(mlx4_tlock(dev));
  3079. list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
  3080. spin_unlock_irq(mlx4_tlock(dev));
  3081. if (mpt->com.owner == slave) {
  3082. mptn = mpt->com.res_id;
  3083. state = mpt->com.from_state;
  3084. while (state != 0) {
  3085. switch (state) {
  3086. case RES_MPT_RESERVED:
  3087. __mlx4_mpt_release(dev, mpt->key);
  3088. spin_lock_irq(mlx4_tlock(dev));
  3089. rb_erase(&mpt->com.node,
  3090. &tracker->res_tree[RES_MPT]);
  3091. list_del(&mpt->com.list);
  3092. spin_unlock_irq(mlx4_tlock(dev));
  3093. kfree(mpt);
  3094. state = 0;
  3095. break;
  3096. case RES_MPT_MAPPED:
  3097. __mlx4_mpt_free_icm(dev, mpt->key);
  3098. state = RES_MPT_RESERVED;
  3099. break;
  3100. case RES_MPT_HW:
  3101. in_param = slave;
  3102. err = mlx4_cmd(dev, in_param, mptn, 0,
  3103. MLX4_CMD_HW2SW_MPT,
  3104. MLX4_CMD_TIME_CLASS_A,
  3105. MLX4_CMD_NATIVE);
  3106. if (err)
  3107. mlx4_dbg(dev, "rem_slave_mrs: failed"
  3108. " to move slave %d mpt %d to"
  3109. " SW ownership\n",
  3110. slave, mptn);
  3111. if (mpt->mtt)
  3112. atomic_dec(&mpt->mtt->ref_count);
  3113. state = RES_MPT_MAPPED;
  3114. break;
  3115. default:
  3116. state = 0;
  3117. }
  3118. }
  3119. }
  3120. spin_lock_irq(mlx4_tlock(dev));
  3121. }
  3122. spin_unlock_irq(mlx4_tlock(dev));
  3123. }
  3124. static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
  3125. {
  3126. struct mlx4_priv *priv = mlx4_priv(dev);
  3127. struct mlx4_resource_tracker *tracker =
  3128. &priv->mfunc.master.res_tracker;
  3129. struct list_head *mtt_list =
  3130. &tracker->slave_list[slave].res_list[RES_MTT];
  3131. struct res_mtt *mtt;
  3132. struct res_mtt *tmp;
  3133. int state;
  3134. LIST_HEAD(tlist);
  3135. int base;
  3136. int err;
  3137. err = move_all_busy(dev, slave, RES_MTT);
  3138. if (err)
  3139. mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts to "
  3140. "busy for slave %d\n", slave);
  3141. spin_lock_irq(mlx4_tlock(dev));
  3142. list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
  3143. spin_unlock_irq(mlx4_tlock(dev));
  3144. if (mtt->com.owner == slave) {
  3145. base = mtt->com.res_id;
  3146. state = mtt->com.from_state;
  3147. while (state != 0) {
  3148. switch (state) {
  3149. case RES_MTT_ALLOCATED:
  3150. __mlx4_free_mtt_range(dev, base,
  3151. mtt->order);
  3152. spin_lock_irq(mlx4_tlock(dev));
  3153. rb_erase(&mtt->com.node,
  3154. &tracker->res_tree[RES_MTT]);
  3155. list_del(&mtt->com.list);
  3156. spin_unlock_irq(mlx4_tlock(dev));
  3157. kfree(mtt);
  3158. state = 0;
  3159. break;
  3160. default:
  3161. state = 0;
  3162. }
  3163. }
  3164. }
  3165. spin_lock_irq(mlx4_tlock(dev));
  3166. }
  3167. spin_unlock_irq(mlx4_tlock(dev));
  3168. }
  3169. static void rem_slave_fs_rule(struct mlx4_dev *dev, int slave)
  3170. {
  3171. struct mlx4_priv *priv = mlx4_priv(dev);
  3172. struct mlx4_resource_tracker *tracker =
  3173. &priv->mfunc.master.res_tracker;
  3174. struct list_head *fs_rule_list =
  3175. &tracker->slave_list[slave].res_list[RES_FS_RULE];
  3176. struct res_fs_rule *fs_rule;
  3177. struct res_fs_rule *tmp;
  3178. int state;
  3179. u64 base;
  3180. int err;
  3181. err = move_all_busy(dev, slave, RES_FS_RULE);
  3182. if (err)
  3183. mlx4_warn(dev, "rem_slave_fs_rule: Could not move all mtts to busy for slave %d\n",
  3184. slave);
  3185. spin_lock_irq(mlx4_tlock(dev));
  3186. list_for_each_entry_safe(fs_rule, tmp, fs_rule_list, com.list) {
  3187. spin_unlock_irq(mlx4_tlock(dev));
  3188. if (fs_rule->com.owner == slave) {
  3189. base = fs_rule->com.res_id;
  3190. state = fs_rule->com.from_state;
  3191. while (state != 0) {
  3192. switch (state) {
  3193. case RES_FS_RULE_ALLOCATED:
  3194. /* detach rule */
  3195. err = mlx4_cmd(dev, base, 0, 0,
  3196. MLX4_QP_FLOW_STEERING_DETACH,
  3197. MLX4_CMD_TIME_CLASS_A,
  3198. MLX4_CMD_NATIVE);
  3199. spin_lock_irq(mlx4_tlock(dev));
  3200. rb_erase(&fs_rule->com.node,
  3201. &tracker->res_tree[RES_FS_RULE]);
  3202. list_del(&fs_rule->com.list);
  3203. spin_unlock_irq(mlx4_tlock(dev));
  3204. kfree(fs_rule);
  3205. state = 0;
  3206. break;
  3207. default:
  3208. state = 0;
  3209. }
  3210. }
  3211. }
  3212. spin_lock_irq(mlx4_tlock(dev));
  3213. }
  3214. spin_unlock_irq(mlx4_tlock(dev));
  3215. }
  3216. static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
  3217. {
  3218. struct mlx4_priv *priv = mlx4_priv(dev);
  3219. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3220. struct list_head *eq_list =
  3221. &tracker->slave_list[slave].res_list[RES_EQ];
  3222. struct res_eq *eq;
  3223. struct res_eq *tmp;
  3224. int err;
  3225. int state;
  3226. LIST_HEAD(tlist);
  3227. int eqn;
  3228. struct mlx4_cmd_mailbox *mailbox;
  3229. err = move_all_busy(dev, slave, RES_EQ);
  3230. if (err)
  3231. mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs to "
  3232. "busy for slave %d\n", slave);
  3233. spin_lock_irq(mlx4_tlock(dev));
  3234. list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
  3235. spin_unlock_irq(mlx4_tlock(dev));
  3236. if (eq->com.owner == slave) {
  3237. eqn = eq->com.res_id;
  3238. state = eq->com.from_state;
  3239. while (state != 0) {
  3240. switch (state) {
  3241. case RES_EQ_RESERVED:
  3242. spin_lock_irq(mlx4_tlock(dev));
  3243. rb_erase(&eq->com.node,
  3244. &tracker->res_tree[RES_EQ]);
  3245. list_del(&eq->com.list);
  3246. spin_unlock_irq(mlx4_tlock(dev));
  3247. kfree(eq);
  3248. state = 0;
  3249. break;
  3250. case RES_EQ_HW:
  3251. mailbox = mlx4_alloc_cmd_mailbox(dev);
  3252. if (IS_ERR(mailbox)) {
  3253. cond_resched();
  3254. continue;
  3255. }
  3256. err = mlx4_cmd_box(dev, slave, 0,
  3257. eqn & 0xff, 0,
  3258. MLX4_CMD_HW2SW_EQ,
  3259. MLX4_CMD_TIME_CLASS_A,
  3260. MLX4_CMD_NATIVE);
  3261. if (err)
  3262. mlx4_dbg(dev, "rem_slave_eqs: failed"
  3263. " to move slave %d eqs %d to"
  3264. " SW ownership\n", slave, eqn);
  3265. mlx4_free_cmd_mailbox(dev, mailbox);
  3266. atomic_dec(&eq->mtt->ref_count);
  3267. state = RES_EQ_RESERVED;
  3268. break;
  3269. default:
  3270. state = 0;
  3271. }
  3272. }
  3273. }
  3274. spin_lock_irq(mlx4_tlock(dev));
  3275. }
  3276. spin_unlock_irq(mlx4_tlock(dev));
  3277. }
  3278. static void rem_slave_counters(struct mlx4_dev *dev, int slave)
  3279. {
  3280. struct mlx4_priv *priv = mlx4_priv(dev);
  3281. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3282. struct list_head *counter_list =
  3283. &tracker->slave_list[slave].res_list[RES_COUNTER];
  3284. struct res_counter *counter;
  3285. struct res_counter *tmp;
  3286. int err;
  3287. int index;
  3288. err = move_all_busy(dev, slave, RES_COUNTER);
  3289. if (err)
  3290. mlx4_warn(dev, "rem_slave_counters: Could not move all counters to "
  3291. "busy for slave %d\n", slave);
  3292. spin_lock_irq(mlx4_tlock(dev));
  3293. list_for_each_entry_safe(counter, tmp, counter_list, com.list) {
  3294. if (counter->com.owner == slave) {
  3295. index = counter->com.res_id;
  3296. rb_erase(&counter->com.node,
  3297. &tracker->res_tree[RES_COUNTER]);
  3298. list_del(&counter->com.list);
  3299. kfree(counter);
  3300. __mlx4_counter_free(dev, index);
  3301. }
  3302. }
  3303. spin_unlock_irq(mlx4_tlock(dev));
  3304. }
  3305. static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
  3306. {
  3307. struct mlx4_priv *priv = mlx4_priv(dev);
  3308. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3309. struct list_head *xrcdn_list =
  3310. &tracker->slave_list[slave].res_list[RES_XRCD];
  3311. struct res_xrcdn *xrcd;
  3312. struct res_xrcdn *tmp;
  3313. int err;
  3314. int xrcdn;
  3315. err = move_all_busy(dev, slave, RES_XRCD);
  3316. if (err)
  3317. mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns to "
  3318. "busy for slave %d\n", slave);
  3319. spin_lock_irq(mlx4_tlock(dev));
  3320. list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
  3321. if (xrcd->com.owner == slave) {
  3322. xrcdn = xrcd->com.res_id;
  3323. rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]);
  3324. list_del(&xrcd->com.list);
  3325. kfree(xrcd);
  3326. __mlx4_xrcd_free(dev, xrcdn);
  3327. }
  3328. }
  3329. spin_unlock_irq(mlx4_tlock(dev));
  3330. }
  3331. void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
  3332. {
  3333. struct mlx4_priv *priv = mlx4_priv(dev);
  3334. mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  3335. /*VLAN*/
  3336. rem_slave_macs(dev, slave);
  3337. rem_slave_fs_rule(dev, slave);
  3338. rem_slave_qps(dev, slave);
  3339. rem_slave_srqs(dev, slave);
  3340. rem_slave_cqs(dev, slave);
  3341. rem_slave_mrs(dev, slave);
  3342. rem_slave_eqs(dev, slave);
  3343. rem_slave_mtts(dev, slave);
  3344. rem_slave_counters(dev, slave);
  3345. rem_slave_xrcdns(dev, slave);
  3346. mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  3347. }