be.h 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683
  1. /*
  2. * Copyright (C) 2005 - 2013 Emulex
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Contact Information:
  11. * linux-drivers@emulex.com
  12. *
  13. * Emulex
  14. * 3333 Susan Street
  15. * Costa Mesa, CA 92626
  16. */
  17. #ifndef BE_H
  18. #define BE_H
  19. #include <linux/pci.h>
  20. #include <linux/etherdevice.h>
  21. #include <linux/delay.h>
  22. #include <net/tcp.h>
  23. #include <net/ip.h>
  24. #include <net/ipv6.h>
  25. #include <linux/if_vlan.h>
  26. #include <linux/workqueue.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/firmware.h>
  29. #include <linux/slab.h>
  30. #include <linux/u64_stats_sync.h>
  31. #include "be_hw.h"
  32. #include "be_roce.h"
  33. #define DRV_VER "4.6.62.0u"
  34. #define DRV_NAME "be2net"
  35. #define BE_NAME "Emulex BladeEngine2"
  36. #define BE3_NAME "Emulex BladeEngine3"
  37. #define OC_NAME "Emulex OneConnect"
  38. #define OC_NAME_BE OC_NAME "(be3)"
  39. #define OC_NAME_LANCER OC_NAME "(Lancer)"
  40. #define OC_NAME_SH OC_NAME "(Skyhawk)"
  41. #define DRV_DESC "Emulex OneConnect 10Gbps NIC Driver"
  42. #define BE_VENDOR_ID 0x19a2
  43. #define EMULEX_VENDOR_ID 0x10df
  44. #define BE_DEVICE_ID1 0x211
  45. #define BE_DEVICE_ID2 0x221
  46. #define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */
  47. #define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */
  48. #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */
  49. #define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */
  50. #define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */
  51. #define OC_DEVICE_ID6 0x728 /* Device id for VF in SkyHawk */
  52. #define OC_SUBSYS_DEVICE_ID1 0xE602
  53. #define OC_SUBSYS_DEVICE_ID2 0xE642
  54. #define OC_SUBSYS_DEVICE_ID3 0xE612
  55. #define OC_SUBSYS_DEVICE_ID4 0xE652
  56. static inline char *nic_name(struct pci_dev *pdev)
  57. {
  58. switch (pdev->device) {
  59. case OC_DEVICE_ID1:
  60. return OC_NAME;
  61. case OC_DEVICE_ID2:
  62. return OC_NAME_BE;
  63. case OC_DEVICE_ID3:
  64. case OC_DEVICE_ID4:
  65. return OC_NAME_LANCER;
  66. case BE_DEVICE_ID2:
  67. return BE3_NAME;
  68. case OC_DEVICE_ID5:
  69. case OC_DEVICE_ID6:
  70. return OC_NAME_SH;
  71. default:
  72. return BE_NAME;
  73. }
  74. }
  75. /* Number of bytes of an RX frame that are copied to skb->data */
  76. #define BE_HDR_LEN ((u16) 64)
  77. /* allocate extra space to allow tunneling decapsulation without head reallocation */
  78. #define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64)
  79. #define BE_MAX_JUMBO_FRAME_SIZE 9018
  80. #define BE_MIN_MTU 256
  81. #define BE_NUM_VLANS_SUPPORTED 64
  82. #define BE_MAX_EQD 96u
  83. #define BE_MAX_TX_FRAG_COUNT 30
  84. #define EVNT_Q_LEN 1024
  85. #define TX_Q_LEN 2048
  86. #define TX_CQ_LEN 1024
  87. #define RX_Q_LEN 1024 /* Does not support any other value */
  88. #define RX_CQ_LEN 1024
  89. #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */
  90. #define MCC_CQ_LEN 256
  91. #define BE3_MAX_RSS_QS 8
  92. #define BE2_MAX_RSS_QS 4
  93. #define MAX_RSS_QS BE3_MAX_RSS_QS
  94. #define MAX_RX_QS (MAX_RSS_QS + 1) /* RSS qs + 1 def Rx */
  95. #define MAX_TX_QS 8
  96. #define MAX_ROCE_EQS 5
  97. #define MAX_MSIX_VECTORS (MAX_RSS_QS + MAX_ROCE_EQS) /* RSS qs + RoCE */
  98. #define BE_TX_BUDGET 256
  99. #define BE_NAPI_WEIGHT 64
  100. #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */
  101. #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
  102. #define MAX_VFS 30 /* Max VFs supported by BE3 FW */
  103. #define FW_VER_LEN 32
  104. struct be_dma_mem {
  105. void *va;
  106. dma_addr_t dma;
  107. u32 size;
  108. };
  109. struct be_queue_info {
  110. struct be_dma_mem dma_mem;
  111. u16 len;
  112. u16 entry_size; /* Size of an element in the queue */
  113. u16 id;
  114. u16 tail, head;
  115. bool created;
  116. atomic_t used; /* Number of valid elements in the queue */
  117. };
  118. static inline u32 MODULO(u16 val, u16 limit)
  119. {
  120. BUG_ON(limit & (limit - 1));
  121. return val & (limit - 1);
  122. }
  123. static inline void index_adv(u16 *index, u16 val, u16 limit)
  124. {
  125. *index = MODULO((*index + val), limit);
  126. }
  127. static inline void index_inc(u16 *index, u16 limit)
  128. {
  129. *index = MODULO((*index + 1), limit);
  130. }
  131. static inline void *queue_head_node(struct be_queue_info *q)
  132. {
  133. return q->dma_mem.va + q->head * q->entry_size;
  134. }
  135. static inline void *queue_tail_node(struct be_queue_info *q)
  136. {
  137. return q->dma_mem.va + q->tail * q->entry_size;
  138. }
  139. static inline void *queue_index_node(struct be_queue_info *q, u16 index)
  140. {
  141. return q->dma_mem.va + index * q->entry_size;
  142. }
  143. static inline void queue_head_inc(struct be_queue_info *q)
  144. {
  145. index_inc(&q->head, q->len);
  146. }
  147. static inline void index_dec(u16 *index, u16 limit)
  148. {
  149. *index = MODULO((*index - 1), limit);
  150. }
  151. static inline void queue_tail_inc(struct be_queue_info *q)
  152. {
  153. index_inc(&q->tail, q->len);
  154. }
  155. struct be_eq_obj {
  156. struct be_queue_info q;
  157. char desc[32];
  158. /* Adaptive interrupt coalescing (AIC) info */
  159. bool enable_aic;
  160. u32 min_eqd; /* in usecs */
  161. u32 max_eqd; /* in usecs */
  162. u32 eqd; /* configured val when aic is off */
  163. u32 cur_eqd; /* in usecs */
  164. u8 idx; /* array index */
  165. u16 tx_budget;
  166. u16 spurious_intr;
  167. struct napi_struct napi;
  168. struct be_adapter *adapter;
  169. } ____cacheline_aligned_in_smp;
  170. struct be_mcc_obj {
  171. struct be_queue_info q;
  172. struct be_queue_info cq;
  173. bool rearm_cq;
  174. };
  175. struct be_tx_stats {
  176. u64 tx_bytes;
  177. u64 tx_pkts;
  178. u64 tx_reqs;
  179. u64 tx_wrbs;
  180. u64 tx_compl;
  181. ulong tx_jiffies;
  182. u32 tx_stops;
  183. struct u64_stats_sync sync;
  184. struct u64_stats_sync sync_compl;
  185. };
  186. struct be_tx_obj {
  187. u32 db_offset;
  188. struct be_queue_info q;
  189. struct be_queue_info cq;
  190. /* Remember the skbs that were transmitted */
  191. struct sk_buff *sent_skb_list[TX_Q_LEN];
  192. struct be_tx_stats stats;
  193. } ____cacheline_aligned_in_smp;
  194. /* Struct to remember the pages posted for rx frags */
  195. struct be_rx_page_info {
  196. struct page *page;
  197. DEFINE_DMA_UNMAP_ADDR(bus);
  198. u16 page_offset;
  199. bool last_page_user;
  200. };
  201. struct be_rx_stats {
  202. u64 rx_bytes;
  203. u64 rx_pkts;
  204. u64 rx_pkts_prev;
  205. ulong rx_jiffies;
  206. u32 rx_drops_no_skbs; /* skb allocation errors */
  207. u32 rx_drops_no_frags; /* HW has no fetched frags */
  208. u32 rx_post_fail; /* page post alloc failures */
  209. u32 rx_compl;
  210. u32 rx_mcast_pkts;
  211. u32 rx_compl_err; /* completions with err set */
  212. u32 rx_pps; /* pkts per second */
  213. struct u64_stats_sync sync;
  214. };
  215. struct be_rx_compl_info {
  216. u32 rss_hash;
  217. u16 vlan_tag;
  218. u16 pkt_size;
  219. u16 rxq_idx;
  220. u16 port;
  221. u8 vlanf;
  222. u8 num_rcvd;
  223. u8 err;
  224. u8 ipf;
  225. u8 tcpf;
  226. u8 udpf;
  227. u8 ip_csum;
  228. u8 l4_csum;
  229. u8 ipv6;
  230. u8 vtm;
  231. u8 pkt_type;
  232. };
  233. struct be_rx_obj {
  234. struct be_adapter *adapter;
  235. struct be_queue_info q;
  236. struct be_queue_info cq;
  237. struct be_rx_compl_info rxcp;
  238. struct be_rx_page_info page_info_tbl[RX_Q_LEN];
  239. struct be_rx_stats stats;
  240. u8 rss_id;
  241. bool rx_post_starved; /* Zero rx frags have been posted to BE */
  242. } ____cacheline_aligned_in_smp;
  243. struct be_drv_stats {
  244. u32 be_on_die_temperature;
  245. u32 eth_red_drops;
  246. u32 rx_drops_no_pbuf;
  247. u32 rx_drops_no_txpb;
  248. u32 rx_drops_no_erx_descr;
  249. u32 rx_drops_no_tpre_descr;
  250. u32 rx_drops_too_many_frags;
  251. u32 forwarded_packets;
  252. u32 rx_drops_mtu;
  253. u32 rx_crc_errors;
  254. u32 rx_alignment_symbol_errors;
  255. u32 rx_pause_frames;
  256. u32 rx_priority_pause_frames;
  257. u32 rx_control_frames;
  258. u32 rx_in_range_errors;
  259. u32 rx_out_range_errors;
  260. u32 rx_frame_too_long;
  261. u32 rx_address_filtered;
  262. u32 rx_dropped_too_small;
  263. u32 rx_dropped_too_short;
  264. u32 rx_dropped_header_too_small;
  265. u32 rx_dropped_tcp_length;
  266. u32 rx_dropped_runt;
  267. u32 rx_ip_checksum_errs;
  268. u32 rx_tcp_checksum_errs;
  269. u32 rx_udp_checksum_errs;
  270. u32 tx_pauseframes;
  271. u32 tx_priority_pauseframes;
  272. u32 tx_controlframes;
  273. u32 rxpp_fifo_overflow_drop;
  274. u32 rx_input_fifo_overflow_drop;
  275. u32 pmem_fifo_overflow_drop;
  276. u32 jabber_events;
  277. };
  278. struct be_vf_cfg {
  279. unsigned char mac_addr[ETH_ALEN];
  280. int if_handle;
  281. int pmac_id;
  282. u16 def_vid;
  283. u16 vlan_tag;
  284. u32 tx_rate;
  285. };
  286. enum vf_state {
  287. ENABLED = 0,
  288. ASSIGNED = 1
  289. };
  290. #define BE_FLAGS_LINK_STATUS_INIT 1
  291. #define BE_FLAGS_WORKER_SCHEDULED (1 << 3)
  292. #define BE_FLAGS_NAPI_ENABLED (1 << 9)
  293. #define BE_UC_PMAC_COUNT 30
  294. #define BE_VF_UC_PMAC_COUNT 2
  295. #define BE_FLAGS_QNQ_ASYNC_EVT_RCVD (1 << 11)
  296. struct phy_info {
  297. u8 transceiver;
  298. u8 autoneg;
  299. u8 fc_autoneg;
  300. u8 port_type;
  301. u16 phy_type;
  302. u16 interface_type;
  303. u32 misc_params;
  304. u16 auto_speeds_supported;
  305. u16 fixed_speeds_supported;
  306. int link_speed;
  307. u32 dac_cable_len;
  308. u32 advertising;
  309. u32 supported;
  310. };
  311. struct be_adapter {
  312. struct pci_dev *pdev;
  313. struct net_device *netdev;
  314. u8 __iomem *csr; /* CSR BAR used only for BE2/3 */
  315. u8 __iomem *db; /* Door Bell */
  316. struct mutex mbox_lock; /* For serializing mbox cmds to BE card */
  317. struct be_dma_mem mbox_mem;
  318. /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
  319. * is stored for freeing purpose */
  320. struct be_dma_mem mbox_mem_alloced;
  321. struct be_mcc_obj mcc_obj;
  322. spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */
  323. spinlock_t mcc_cq_lock;
  324. u32 num_msix_vec;
  325. u32 num_evt_qs;
  326. struct be_eq_obj eq_obj[MAX_MSIX_VECTORS];
  327. struct msix_entry msix_entries[MAX_MSIX_VECTORS];
  328. bool isr_registered;
  329. /* TX Rings */
  330. u32 num_tx_qs;
  331. struct be_tx_obj tx_obj[MAX_TX_QS];
  332. /* Rx rings */
  333. u32 num_rx_qs;
  334. struct be_rx_obj rx_obj[MAX_RX_QS];
  335. u32 big_page_size; /* Compounded page size shared by rx wrbs */
  336. struct be_drv_stats drv_stats;
  337. u16 vlans_added;
  338. u8 vlan_tag[VLAN_N_VID];
  339. u8 vlan_prio_bmap; /* Available Priority BitMap */
  340. u16 recommended_prio; /* Recommended Priority */
  341. struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */
  342. struct be_dma_mem stats_cmd;
  343. /* Work queue used to perform periodic tasks like getting statistics */
  344. struct delayed_work work;
  345. u16 work_counter;
  346. struct delayed_work func_recovery_work;
  347. u32 flags;
  348. u32 cmd_privileges;
  349. /* Ethtool knobs and info */
  350. char fw_ver[FW_VER_LEN];
  351. int if_handle; /* Used to configure filtering */
  352. u32 *pmac_id; /* MAC addr handle used by BE card */
  353. u32 beacon_state; /* for set_phys_id */
  354. bool eeh_error;
  355. bool fw_timeout;
  356. bool hw_error;
  357. u32 port_num;
  358. bool promiscuous;
  359. u32 function_mode;
  360. u32 function_caps;
  361. u32 rx_fc; /* Rx flow control */
  362. u32 tx_fc; /* Tx flow control */
  363. bool stats_cmd_sent;
  364. u32 if_type;
  365. struct {
  366. u32 size;
  367. u32 total_size;
  368. u64 io_addr;
  369. } roce_db;
  370. u32 num_msix_roce_vec;
  371. struct ocrdma_dev *ocrdma_dev;
  372. struct list_head entry;
  373. u32 flash_status;
  374. struct completion flash_compl;
  375. u32 num_vfs; /* Number of VFs provisioned by PF driver */
  376. u32 dev_num_vfs; /* Number of VFs supported by HW */
  377. u8 virtfn;
  378. struct be_vf_cfg *vf_cfg;
  379. bool be3_native;
  380. u32 sli_family;
  381. u8 hba_port_num;
  382. u16 pvid;
  383. struct phy_info phy;
  384. u8 wol_cap;
  385. bool wol;
  386. u32 uc_macs; /* Count of secondary UC MAC programmed */
  387. u16 asic_rev;
  388. u16 qnq_vid;
  389. u32 msg_enable;
  390. int be_get_temp_freq;
  391. u16 max_mcast_mac;
  392. u16 max_tx_queues;
  393. u16 max_rss_queues;
  394. u16 max_rx_queues;
  395. u16 max_pmac_cnt;
  396. u16 max_vlans;
  397. u16 max_event_queues;
  398. u32 if_cap_flags;
  399. u8 pf_number;
  400. u64 rss_flags;
  401. };
  402. #define be_physfn(adapter) (!adapter->virtfn)
  403. #define sriov_enabled(adapter) (adapter->num_vfs > 0)
  404. #define sriov_want(adapter) (adapter->dev_num_vfs && num_vfs && \
  405. be_physfn(adapter))
  406. #define for_all_vfs(adapter, vf_cfg, i) \
  407. for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \
  408. i++, vf_cfg++)
  409. #define ON 1
  410. #define OFF 0
  411. #define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3 || \
  412. adapter->pdev->device == OC_DEVICE_ID4)
  413. #define skyhawk_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID5 || \
  414. adapter->pdev->device == OC_DEVICE_ID6)
  415. #define BE3_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID2 || \
  416. adapter->pdev->device == OC_DEVICE_ID2)
  417. #define BE2_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID1 || \
  418. adapter->pdev->device == OC_DEVICE_ID1)
  419. #define BEx_chip(adapter) (BE3_chip(adapter) || BE2_chip(adapter))
  420. #define be_roce_supported(adapter) (skyhawk_chip(adapter) && \
  421. (adapter->function_mode & RDMA_ENABLED))
  422. extern const struct ethtool_ops be_ethtool_ops;
  423. #define msix_enabled(adapter) (adapter->num_msix_vec > 0)
  424. #define num_irqs(adapter) (msix_enabled(adapter) ? \
  425. adapter->num_msix_vec : 1)
  426. #define tx_stats(txo) (&(txo)->stats)
  427. #define rx_stats(rxo) (&(rxo)->stats)
  428. /* The default RXQ is the last RXQ */
  429. #define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1])
  430. #define for_all_rx_queues(adapter, rxo, i) \
  431. for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \
  432. i++, rxo++)
  433. /* Skip the default non-rss queue (last one)*/
  434. #define for_all_rss_queues(adapter, rxo, i) \
  435. for (i = 0, rxo = &adapter->rx_obj[i]; i < (adapter->num_rx_qs - 1);\
  436. i++, rxo++)
  437. #define for_all_tx_queues(adapter, txo, i) \
  438. for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \
  439. i++, txo++)
  440. #define for_all_evt_queues(adapter, eqo, i) \
  441. for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \
  442. i++, eqo++)
  443. #define is_mcc_eqo(eqo) (eqo->idx == 0)
  444. #define mcc_eqo(adapter) (&adapter->eq_obj[0])
  445. #define PAGE_SHIFT_4K 12
  446. #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
  447. /* Returns number of pages spanned by the data starting at the given addr */
  448. #define PAGES_4K_SPANNED(_address, size) \
  449. ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
  450. (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
  451. /* Returns bit offset within a DWORD of a bitfield */
  452. #define AMAP_BIT_OFFSET(_struct, field) \
  453. (((size_t)&(((_struct *)0)->field))%32)
  454. /* Returns the bit mask of the field that is NOT shifted into location. */
  455. static inline u32 amap_mask(u32 bitsize)
  456. {
  457. return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
  458. }
  459. static inline void
  460. amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
  461. {
  462. u32 *dw = (u32 *) ptr + dw_offset;
  463. *dw &= ~(mask << offset);
  464. *dw |= (mask & value) << offset;
  465. }
  466. #define AMAP_SET_BITS(_struct, field, ptr, val) \
  467. amap_set(ptr, \
  468. offsetof(_struct, field)/32, \
  469. amap_mask(sizeof(((_struct *)0)->field)), \
  470. AMAP_BIT_OFFSET(_struct, field), \
  471. val)
  472. static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
  473. {
  474. u32 *dw = (u32 *) ptr;
  475. return mask & (*(dw + dw_offset) >> offset);
  476. }
  477. #define AMAP_GET_BITS(_struct, field, ptr) \
  478. amap_get(ptr, \
  479. offsetof(_struct, field)/32, \
  480. amap_mask(sizeof(((_struct *)0)->field)), \
  481. AMAP_BIT_OFFSET(_struct, field))
  482. #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
  483. #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
  484. static inline void swap_dws(void *wrb, int len)
  485. {
  486. #ifdef __BIG_ENDIAN
  487. u32 *dw = wrb;
  488. BUG_ON(len % 4);
  489. do {
  490. *dw = cpu_to_le32(*dw);
  491. dw++;
  492. len -= 4;
  493. } while (len);
  494. #endif /* __BIG_ENDIAN */
  495. }
  496. static inline u8 is_tcp_pkt(struct sk_buff *skb)
  497. {
  498. u8 val = 0;
  499. if (ip_hdr(skb)->version == 4)
  500. val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
  501. else if (ip_hdr(skb)->version == 6)
  502. val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
  503. return val;
  504. }
  505. static inline u8 is_udp_pkt(struct sk_buff *skb)
  506. {
  507. u8 val = 0;
  508. if (ip_hdr(skb)->version == 4)
  509. val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
  510. else if (ip_hdr(skb)->version == 6)
  511. val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
  512. return val;
  513. }
  514. static inline bool is_ipv4_pkt(struct sk_buff *skb)
  515. {
  516. return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
  517. }
  518. static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac)
  519. {
  520. u32 addr;
  521. addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0);
  522. mac[5] = (u8)(addr & 0xFF);
  523. mac[4] = (u8)((addr >> 8) & 0xFF);
  524. mac[3] = (u8)((addr >> 16) & 0xFF);
  525. /* Use the OUI from the current MAC address */
  526. memcpy(mac, adapter->netdev->dev_addr, 3);
  527. }
  528. static inline bool be_multi_rxq(const struct be_adapter *adapter)
  529. {
  530. return adapter->num_rx_qs > 1;
  531. }
  532. static inline bool be_error(struct be_adapter *adapter)
  533. {
  534. return adapter->eeh_error || adapter->hw_error || adapter->fw_timeout;
  535. }
  536. static inline bool be_hw_error(struct be_adapter *adapter)
  537. {
  538. return adapter->eeh_error || adapter->hw_error;
  539. }
  540. static inline void be_clear_all_error(struct be_adapter *adapter)
  541. {
  542. adapter->eeh_error = false;
  543. adapter->hw_error = false;
  544. adapter->fw_timeout = false;
  545. }
  546. static inline bool be_is_wol_excluded(struct be_adapter *adapter)
  547. {
  548. struct pci_dev *pdev = adapter->pdev;
  549. if (!be_physfn(adapter))
  550. return true;
  551. switch (pdev->subsystem_device) {
  552. case OC_SUBSYS_DEVICE_ID1:
  553. case OC_SUBSYS_DEVICE_ID2:
  554. case OC_SUBSYS_DEVICE_ID3:
  555. case OC_SUBSYS_DEVICE_ID4:
  556. return true;
  557. default:
  558. return false;
  559. }
  560. }
  561. static inline int qnq_async_evt_rcvd(struct be_adapter *adapter)
  562. {
  563. return adapter->flags & BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
  564. }
  565. extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
  566. u16 num_popped);
  567. extern void be_link_status_update(struct be_adapter *adapter, u8 link_status);
  568. extern void be_parse_stats(struct be_adapter *adapter);
  569. extern int be_load_fw(struct be_adapter *adapter, u8 *func);
  570. extern bool be_is_wol_supported(struct be_adapter *adapter);
  571. extern bool be_pause_supported(struct be_adapter *adapter);
  572. extern u32 be_get_fw_log_level(struct be_adapter *adapter);
  573. /*
  574. * internal function to initialize-cleanup roce device.
  575. */
  576. extern void be_roce_dev_add(struct be_adapter *);
  577. extern void be_roce_dev_remove(struct be_adapter *);
  578. /*
  579. * internal function to open-close roce device during ifup-ifdown.
  580. */
  581. extern void be_roce_dev_open(struct be_adapter *);
  582. extern void be_roce_dev_close(struct be_adapter *);
  583. #endif /* BE_H */