db8500-prcmu.c 82 KB

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  1. /*
  2. * Copyright (C) STMicroelectronics 2009
  3. * Copyright (C) ST-Ericsson SA 2010
  4. *
  5. * License Terms: GNU General Public License v2
  6. * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
  7. * Author: Sundar Iyer <sundar.iyer@stericsson.com>
  8. * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
  9. *
  10. * U8500 PRCM Unit interface driver
  11. *
  12. */
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/delay.h>
  16. #include <linux/errno.h>
  17. #include <linux/err.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/io.h>
  20. #include <linux/slab.h>
  21. #include <linux/mutex.h>
  22. #include <linux/completion.h>
  23. #include <linux/irq.h>
  24. #include <linux/jiffies.h>
  25. #include <linux/bitops.h>
  26. #include <linux/fs.h>
  27. #include <linux/of.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/uaccess.h>
  30. #include <linux/mfd/core.h>
  31. #include <linux/mfd/dbx500-prcmu.h>
  32. #include <linux/mfd/abx500/ab8500.h>
  33. #include <linux/regulator/db8500-prcmu.h>
  34. #include <linux/regulator/machine.h>
  35. #include <linux/cpufreq.h>
  36. #include <linux/platform_data/ux500_wdt.h>
  37. #include <linux/platform_data/db8500_thermal.h>
  38. #include "dbx500-prcmu-regs.h"
  39. /* Index of different voltages to be used when accessing AVSData */
  40. #define PRCM_AVS_BASE 0x2FC
  41. #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0)
  42. #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1)
  43. #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2)
  44. #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3)
  45. #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4)
  46. #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5)
  47. #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6)
  48. #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7)
  49. #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8)
  50. #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9)
  51. #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA)
  52. #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB)
  53. #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC)
  54. #define PRCM_AVS_VOLTAGE 0
  55. #define PRCM_AVS_VOLTAGE_MASK 0x3f
  56. #define PRCM_AVS_ISSLOWSTARTUP 6
  57. #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP)
  58. #define PRCM_AVS_ISMODEENABLE 7
  59. #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE)
  60. #define PRCM_BOOT_STATUS 0xFFF
  61. #define PRCM_ROMCODE_A2P 0xFFE
  62. #define PRCM_ROMCODE_P2A 0xFFD
  63. #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */
  64. #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
  65. #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */
  66. #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0)
  67. #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1)
  68. #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2)
  69. #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3)
  70. #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4)
  71. #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5)
  72. #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8)
  73. /* Req Mailboxes */
  74. #define PRCM_REQ_MB0 0xFDC /* 12 bytes */
  75. #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */
  76. #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */
  77. #define PRCM_REQ_MB3 0xE4C /* 372 bytes */
  78. #define PRCM_REQ_MB4 0xE48 /* 4 bytes */
  79. #define PRCM_REQ_MB5 0xE44 /* 4 bytes */
  80. /* Ack Mailboxes */
  81. #define PRCM_ACK_MB0 0xE08 /* 52 bytes */
  82. #define PRCM_ACK_MB1 0xE04 /* 4 bytes */
  83. #define PRCM_ACK_MB2 0xE00 /* 4 bytes */
  84. #define PRCM_ACK_MB3 0xDFC /* 4 bytes */
  85. #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
  86. #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
  87. /* Mailbox 0 headers */
  88. #define MB0H_POWER_STATE_TRANS 0
  89. #define MB0H_CONFIG_WAKEUPS_EXE 1
  90. #define MB0H_READ_WAKEUP_ACK 3
  91. #define MB0H_CONFIG_WAKEUPS_SLEEP 4
  92. #define MB0H_WAKEUP_EXE 2
  93. #define MB0H_WAKEUP_SLEEP 5
  94. /* Mailbox 0 REQs */
  95. #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0)
  96. #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1)
  97. #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2)
  98. #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3)
  99. #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4)
  100. #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8)
  101. /* Mailbox 0 ACKs */
  102. #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0)
  103. #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1)
  104. #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4)
  105. #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8)
  106. #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C)
  107. #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20)
  108. #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
  109. /* Mailbox 1 headers */
  110. #define MB1H_ARM_APE_OPP 0x0
  111. #define MB1H_RESET_MODEM 0x2
  112. #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
  113. #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
  114. #define MB1H_RELEASE_USB_WAKEUP 0x5
  115. #define MB1H_PLL_ON_OFF 0x6
  116. /* Mailbox 1 Requests */
  117. #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0)
  118. #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1)
  119. #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4)
  120. #define PLL_SOC0_OFF 0x1
  121. #define PLL_SOC0_ON 0x2
  122. #define PLL_SOC1_OFF 0x4
  123. #define PLL_SOC1_ON 0x8
  124. /* Mailbox 1 ACKs */
  125. #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0)
  126. #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1)
  127. #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
  128. #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3)
  129. /* Mailbox 2 headers */
  130. #define MB2H_DPS 0x0
  131. #define MB2H_AUTO_PWR 0x1
  132. /* Mailbox 2 REQs */
  133. #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0)
  134. #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1)
  135. #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2)
  136. #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3)
  137. #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4)
  138. #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5)
  139. #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6)
  140. #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7)
  141. #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8)
  142. #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC)
  143. /* Mailbox 2 ACKs */
  144. #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
  145. #define HWACC_PWR_ST_OK 0xFE
  146. /* Mailbox 3 headers */
  147. #define MB3H_ANC 0x0
  148. #define MB3H_SIDETONE 0x1
  149. #define MB3H_SYSCLK 0xE
  150. /* Mailbox 3 Requests */
  151. #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0)
  152. #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20)
  153. #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60)
  154. #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64)
  155. #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68)
  156. #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
  157. #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C)
  158. /* Mailbox 4 headers */
  159. #define MB4H_DDR_INIT 0x0
  160. #define MB4H_MEM_ST 0x1
  161. #define MB4H_HOTDOG 0x12
  162. #define MB4H_HOTMON 0x13
  163. #define MB4H_HOT_PERIOD 0x14
  164. #define MB4H_A9WDOG_CONF 0x16
  165. #define MB4H_A9WDOG_EN 0x17
  166. #define MB4H_A9WDOG_DIS 0x18
  167. #define MB4H_A9WDOG_LOAD 0x19
  168. #define MB4H_A9WDOG_KICK 0x20
  169. /* Mailbox 4 Requests */
  170. #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0)
  171. #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1)
  172. #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3)
  173. #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0)
  174. #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0)
  175. #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1)
  176. #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2)
  177. #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0)
  178. #define HOTMON_CONFIG_LOW BIT(0)
  179. #define HOTMON_CONFIG_HIGH BIT(1)
  180. #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0)
  181. #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1)
  182. #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2)
  183. #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3)
  184. #define A9WDOG_AUTO_OFF_EN BIT(7)
  185. #define A9WDOG_AUTO_OFF_DIS 0
  186. #define A9WDOG_ID_MASK 0xf
  187. /* Mailbox 5 Requests */
  188. #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0)
  189. #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
  190. #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
  191. #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
  192. #define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6))
  193. #define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6))
  194. #define PRCMU_I2C_STOP_EN BIT(3)
  195. /* Mailbox 5 ACKs */
  196. #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
  197. #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3)
  198. #define I2C_WR_OK 0x1
  199. #define I2C_RD_OK 0x2
  200. #define NUM_MB 8
  201. #define MBOX_BIT BIT
  202. #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
  203. /*
  204. * Wakeups/IRQs
  205. */
  206. #define WAKEUP_BIT_RTC BIT(0)
  207. #define WAKEUP_BIT_RTT0 BIT(1)
  208. #define WAKEUP_BIT_RTT1 BIT(2)
  209. #define WAKEUP_BIT_HSI0 BIT(3)
  210. #define WAKEUP_BIT_HSI1 BIT(4)
  211. #define WAKEUP_BIT_CA_WAKE BIT(5)
  212. #define WAKEUP_BIT_USB BIT(6)
  213. #define WAKEUP_BIT_ABB BIT(7)
  214. #define WAKEUP_BIT_ABB_FIFO BIT(8)
  215. #define WAKEUP_BIT_SYSCLK_OK BIT(9)
  216. #define WAKEUP_BIT_CA_SLEEP BIT(10)
  217. #define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
  218. #define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
  219. #define WAKEUP_BIT_ANC_OK BIT(13)
  220. #define WAKEUP_BIT_SW_ERROR BIT(14)
  221. #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
  222. #define WAKEUP_BIT_ARM BIT(17)
  223. #define WAKEUP_BIT_HOTMON_LOW BIT(18)
  224. #define WAKEUP_BIT_HOTMON_HIGH BIT(19)
  225. #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
  226. #define WAKEUP_BIT_GPIO0 BIT(23)
  227. #define WAKEUP_BIT_GPIO1 BIT(24)
  228. #define WAKEUP_BIT_GPIO2 BIT(25)
  229. #define WAKEUP_BIT_GPIO3 BIT(26)
  230. #define WAKEUP_BIT_GPIO4 BIT(27)
  231. #define WAKEUP_BIT_GPIO5 BIT(28)
  232. #define WAKEUP_BIT_GPIO6 BIT(29)
  233. #define WAKEUP_BIT_GPIO7 BIT(30)
  234. #define WAKEUP_BIT_GPIO8 BIT(31)
  235. static struct {
  236. bool valid;
  237. struct prcmu_fw_version version;
  238. } fw_info;
  239. static struct irq_domain *db8500_irq_domain;
  240. /*
  241. * This vector maps irq numbers to the bits in the bit field used in
  242. * communication with the PRCMU firmware.
  243. *
  244. * The reason for having this is to keep the irq numbers contiguous even though
  245. * the bits in the bit field are not. (The bits also have a tendency to move
  246. * around, to further complicate matters.)
  247. */
  248. #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name))
  249. #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
  250. #define IRQ_PRCMU_RTC 0
  251. #define IRQ_PRCMU_RTT0 1
  252. #define IRQ_PRCMU_RTT1 2
  253. #define IRQ_PRCMU_HSI0 3
  254. #define IRQ_PRCMU_HSI1 4
  255. #define IRQ_PRCMU_CA_WAKE 5
  256. #define IRQ_PRCMU_USB 6
  257. #define IRQ_PRCMU_ABB 7
  258. #define IRQ_PRCMU_ABB_FIFO 8
  259. #define IRQ_PRCMU_ARM 9
  260. #define IRQ_PRCMU_MODEM_SW_RESET_REQ 10
  261. #define IRQ_PRCMU_GPIO0 11
  262. #define IRQ_PRCMU_GPIO1 12
  263. #define IRQ_PRCMU_GPIO2 13
  264. #define IRQ_PRCMU_GPIO3 14
  265. #define IRQ_PRCMU_GPIO4 15
  266. #define IRQ_PRCMU_GPIO5 16
  267. #define IRQ_PRCMU_GPIO6 17
  268. #define IRQ_PRCMU_GPIO7 18
  269. #define IRQ_PRCMU_GPIO8 19
  270. #define IRQ_PRCMU_CA_SLEEP 20
  271. #define IRQ_PRCMU_HOTMON_LOW 21
  272. #define IRQ_PRCMU_HOTMON_HIGH 22
  273. #define NUM_PRCMU_WAKEUPS 23
  274. static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
  275. IRQ_ENTRY(RTC),
  276. IRQ_ENTRY(RTT0),
  277. IRQ_ENTRY(RTT1),
  278. IRQ_ENTRY(HSI0),
  279. IRQ_ENTRY(HSI1),
  280. IRQ_ENTRY(CA_WAKE),
  281. IRQ_ENTRY(USB),
  282. IRQ_ENTRY(ABB),
  283. IRQ_ENTRY(ABB_FIFO),
  284. IRQ_ENTRY(CA_SLEEP),
  285. IRQ_ENTRY(ARM),
  286. IRQ_ENTRY(HOTMON_LOW),
  287. IRQ_ENTRY(HOTMON_HIGH),
  288. IRQ_ENTRY(MODEM_SW_RESET_REQ),
  289. IRQ_ENTRY(GPIO0),
  290. IRQ_ENTRY(GPIO1),
  291. IRQ_ENTRY(GPIO2),
  292. IRQ_ENTRY(GPIO3),
  293. IRQ_ENTRY(GPIO4),
  294. IRQ_ENTRY(GPIO5),
  295. IRQ_ENTRY(GPIO6),
  296. IRQ_ENTRY(GPIO7),
  297. IRQ_ENTRY(GPIO8)
  298. };
  299. #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
  300. #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
  301. static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
  302. WAKEUP_ENTRY(RTC),
  303. WAKEUP_ENTRY(RTT0),
  304. WAKEUP_ENTRY(RTT1),
  305. WAKEUP_ENTRY(HSI0),
  306. WAKEUP_ENTRY(HSI1),
  307. WAKEUP_ENTRY(USB),
  308. WAKEUP_ENTRY(ABB),
  309. WAKEUP_ENTRY(ABB_FIFO),
  310. WAKEUP_ENTRY(ARM)
  311. };
  312. /*
  313. * mb0_transfer - state needed for mailbox 0 communication.
  314. * @lock: The transaction lock.
  315. * @dbb_events_lock: A lock used to handle concurrent access to (parts of)
  316. * the request data.
  317. * @mask_work: Work structure used for (un)masking wakeup interrupts.
  318. * @req: Request data that need to persist between requests.
  319. */
  320. static struct {
  321. spinlock_t lock;
  322. spinlock_t dbb_irqs_lock;
  323. struct work_struct mask_work;
  324. struct mutex ac_wake_lock;
  325. struct completion ac_wake_work;
  326. struct {
  327. u32 dbb_irqs;
  328. u32 dbb_wakeups;
  329. u32 abb_events;
  330. } req;
  331. } mb0_transfer;
  332. /*
  333. * mb1_transfer - state needed for mailbox 1 communication.
  334. * @lock: The transaction lock.
  335. * @work: The transaction completion structure.
  336. * @ape_opp: The current APE OPP.
  337. * @ack: Reply ("acknowledge") data.
  338. */
  339. static struct {
  340. struct mutex lock;
  341. struct completion work;
  342. u8 ape_opp;
  343. struct {
  344. u8 header;
  345. u8 arm_opp;
  346. u8 ape_opp;
  347. u8 ape_voltage_status;
  348. } ack;
  349. } mb1_transfer;
  350. /*
  351. * mb2_transfer - state needed for mailbox 2 communication.
  352. * @lock: The transaction lock.
  353. * @work: The transaction completion structure.
  354. * @auto_pm_lock: The autonomous power management configuration lock.
  355. * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
  356. * @req: Request data that need to persist between requests.
  357. * @ack: Reply ("acknowledge") data.
  358. */
  359. static struct {
  360. struct mutex lock;
  361. struct completion work;
  362. spinlock_t auto_pm_lock;
  363. bool auto_pm_enabled;
  364. struct {
  365. u8 status;
  366. } ack;
  367. } mb2_transfer;
  368. /*
  369. * mb3_transfer - state needed for mailbox 3 communication.
  370. * @lock: The request lock.
  371. * @sysclk_lock: A lock used to handle concurrent sysclk requests.
  372. * @sysclk_work: Work structure used for sysclk requests.
  373. */
  374. static struct {
  375. spinlock_t lock;
  376. struct mutex sysclk_lock;
  377. struct completion sysclk_work;
  378. } mb3_transfer;
  379. /*
  380. * mb4_transfer - state needed for mailbox 4 communication.
  381. * @lock: The transaction lock.
  382. * @work: The transaction completion structure.
  383. */
  384. static struct {
  385. struct mutex lock;
  386. struct completion work;
  387. } mb4_transfer;
  388. /*
  389. * mb5_transfer - state needed for mailbox 5 communication.
  390. * @lock: The transaction lock.
  391. * @work: The transaction completion structure.
  392. * @ack: Reply ("acknowledge") data.
  393. */
  394. static struct {
  395. struct mutex lock;
  396. struct completion work;
  397. struct {
  398. u8 status;
  399. u8 value;
  400. } ack;
  401. } mb5_transfer;
  402. static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
  403. /* Spinlocks */
  404. static DEFINE_SPINLOCK(prcmu_lock);
  405. static DEFINE_SPINLOCK(clkout_lock);
  406. /* Global var to runtime determine TCDM base for v2 or v1 */
  407. static __iomem void *tcdm_base;
  408. static __iomem void *prcmu_base;
  409. struct clk_mgt {
  410. u32 offset;
  411. u32 pllsw;
  412. int branch;
  413. bool clk38div;
  414. };
  415. enum {
  416. PLL_RAW,
  417. PLL_FIX,
  418. PLL_DIV
  419. };
  420. static DEFINE_SPINLOCK(clk_mgt_lock);
  421. #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
  422. { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
  423. struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
  424. CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
  425. CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
  426. CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
  427. CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
  428. CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
  429. CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
  430. CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
  431. CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
  432. CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
  433. CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
  434. CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
  435. CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
  436. CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
  437. CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
  438. CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
  439. CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
  440. CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
  441. CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
  442. CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
  443. CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
  444. CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
  445. CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
  446. CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
  447. CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
  448. CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
  449. CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
  450. CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
  451. CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
  452. CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
  453. };
  454. struct dsiclk {
  455. u32 divsel_mask;
  456. u32 divsel_shift;
  457. u32 divsel;
  458. };
  459. static struct dsiclk dsiclk[2] = {
  460. {
  461. .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
  462. .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
  463. .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
  464. },
  465. {
  466. .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
  467. .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
  468. .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
  469. }
  470. };
  471. struct dsiescclk {
  472. u32 en;
  473. u32 div_mask;
  474. u32 div_shift;
  475. };
  476. static struct dsiescclk dsiescclk[3] = {
  477. {
  478. .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
  479. .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
  480. .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
  481. },
  482. {
  483. .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
  484. .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
  485. .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
  486. },
  487. {
  488. .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
  489. .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
  490. .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
  491. }
  492. };
  493. /*
  494. * Used by MCDE to setup all necessary PRCMU registers
  495. */
  496. #define PRCMU_RESET_DSIPLL 0x00004000
  497. #define PRCMU_UNCLAMP_DSIPLL 0x00400800
  498. #define PRCMU_CLK_PLL_DIV_SHIFT 0
  499. #define PRCMU_CLK_PLL_SW_SHIFT 5
  500. #define PRCMU_CLK_38 (1 << 9)
  501. #define PRCMU_CLK_38_SRC (1 << 10)
  502. #define PRCMU_CLK_38_DIV (1 << 11)
  503. /* PLLDIV=12, PLLSW=4 (PLLDDR) */
  504. #define PRCMU_DSI_CLOCK_SETTING 0x0000008C
  505. /* DPI 50000000 Hz */
  506. #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
  507. (16 << PRCMU_CLK_PLL_DIV_SHIFT))
  508. #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00
  509. /* D=101, N=1, R=4, SELDIV2=0 */
  510. #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165
  511. #define PRCMU_ENABLE_PLLDSI 0x00000001
  512. #define PRCMU_DISABLE_PLLDSI 0x00000000
  513. #define PRCMU_RELEASE_RESET_DSS 0x0000400C
  514. #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202
  515. /* ESC clk, div0=1, div1=1, div2=3 */
  516. #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101
  517. #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101
  518. #define PRCMU_DSI_RESET_SW 0x00000007
  519. #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3
  520. int db8500_prcmu_enable_dsipll(void)
  521. {
  522. int i;
  523. /* Clear DSIPLL_RESETN */
  524. writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
  525. /* Unclamp DSIPLL in/out */
  526. writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
  527. /* Set DSI PLL FREQ */
  528. writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
  529. writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
  530. /* Enable Escape clocks */
  531. writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
  532. /* Start DSI PLL */
  533. writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
  534. /* Reset DSI PLL */
  535. writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
  536. for (i = 0; i < 10; i++) {
  537. if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)
  538. == PRCMU_PLLDSI_LOCKP_LOCKED)
  539. break;
  540. udelay(100);
  541. }
  542. /* Set DSIPLL_RESETN */
  543. writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
  544. return 0;
  545. }
  546. int db8500_prcmu_disable_dsipll(void)
  547. {
  548. /* Disable dsi pll */
  549. writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
  550. /* Disable escapeclock */
  551. writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
  552. return 0;
  553. }
  554. int db8500_prcmu_set_display_clocks(void)
  555. {
  556. unsigned long flags;
  557. spin_lock_irqsave(&clk_mgt_lock, flags);
  558. /* Grab the HW semaphore. */
  559. while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
  560. cpu_relax();
  561. writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT);
  562. writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT);
  563. writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT);
  564. /* Release the HW semaphore. */
  565. writel(0, PRCM_SEM);
  566. spin_unlock_irqrestore(&clk_mgt_lock, flags);
  567. return 0;
  568. }
  569. u32 db8500_prcmu_read(unsigned int reg)
  570. {
  571. return readl(prcmu_base + reg);
  572. }
  573. void db8500_prcmu_write(unsigned int reg, u32 value)
  574. {
  575. unsigned long flags;
  576. spin_lock_irqsave(&prcmu_lock, flags);
  577. writel(value, (prcmu_base + reg));
  578. spin_unlock_irqrestore(&prcmu_lock, flags);
  579. }
  580. void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
  581. {
  582. u32 val;
  583. unsigned long flags;
  584. spin_lock_irqsave(&prcmu_lock, flags);
  585. val = readl(prcmu_base + reg);
  586. val = ((val & ~mask) | (value & mask));
  587. writel(val, (prcmu_base + reg));
  588. spin_unlock_irqrestore(&prcmu_lock, flags);
  589. }
  590. struct prcmu_fw_version *prcmu_get_fw_version(void)
  591. {
  592. return fw_info.valid ? &fw_info.version : NULL;
  593. }
  594. bool prcmu_has_arm_maxopp(void)
  595. {
  596. return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
  597. PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
  598. }
  599. /**
  600. * prcmu_get_boot_status - PRCMU boot status checking
  601. * Returns: the current PRCMU boot status
  602. */
  603. int prcmu_get_boot_status(void)
  604. {
  605. return readb(tcdm_base + PRCM_BOOT_STATUS);
  606. }
  607. /**
  608. * prcmu_set_rc_a2p - This function is used to run few power state sequences
  609. * @val: Value to be set, i.e. transition requested
  610. * Returns: 0 on success, -EINVAL on invalid argument
  611. *
  612. * This function is used to run the following power state sequences -
  613. * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
  614. */
  615. int prcmu_set_rc_a2p(enum romcode_write val)
  616. {
  617. if (val < RDY_2_DS || val > RDY_2_XP70_RST)
  618. return -EINVAL;
  619. writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
  620. return 0;
  621. }
  622. /**
  623. * prcmu_get_rc_p2a - This function is used to get power state sequences
  624. * Returns: the power transition that has last happened
  625. *
  626. * This function can return the following transitions-
  627. * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
  628. */
  629. enum romcode_read prcmu_get_rc_p2a(void)
  630. {
  631. return readb(tcdm_base + PRCM_ROMCODE_P2A);
  632. }
  633. /**
  634. * prcmu_get_current_mode - Return the current XP70 power mode
  635. * Returns: Returns the current AP(ARM) power mode: init,
  636. * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
  637. */
  638. enum ap_pwrst prcmu_get_xp70_current_state(void)
  639. {
  640. return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
  641. }
  642. /**
  643. * prcmu_config_clkout - Configure one of the programmable clock outputs.
  644. * @clkout: The CLKOUT number (0 or 1).
  645. * @source: The clock to be used (one of the PRCMU_CLKSRC_*).
  646. * @div: The divider to be applied.
  647. *
  648. * Configures one of the programmable clock outputs (CLKOUTs).
  649. * @div should be in the range [1,63] to request a configuration, or 0 to
  650. * inform that the configuration is no longer requested.
  651. */
  652. int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
  653. {
  654. static int requests[2];
  655. int r = 0;
  656. unsigned long flags;
  657. u32 val;
  658. u32 bits;
  659. u32 mask;
  660. u32 div_mask;
  661. BUG_ON(clkout > 1);
  662. BUG_ON(div > 63);
  663. BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
  664. if (!div && !requests[clkout])
  665. return -EINVAL;
  666. switch (clkout) {
  667. case 0:
  668. div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
  669. mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
  670. bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
  671. (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
  672. break;
  673. case 1:
  674. div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
  675. mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
  676. PRCM_CLKOCR_CLK1TYPE);
  677. bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
  678. (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
  679. break;
  680. }
  681. bits &= mask;
  682. spin_lock_irqsave(&clkout_lock, flags);
  683. val = readl(PRCM_CLKOCR);
  684. if (val & div_mask) {
  685. if (div) {
  686. if ((val & mask) != bits) {
  687. r = -EBUSY;
  688. goto unlock_and_return;
  689. }
  690. } else {
  691. if ((val & mask & ~div_mask) != bits) {
  692. r = -EINVAL;
  693. goto unlock_and_return;
  694. }
  695. }
  696. }
  697. writel((bits | (val & ~mask)), PRCM_CLKOCR);
  698. requests[clkout] += (div ? 1 : -1);
  699. unlock_and_return:
  700. spin_unlock_irqrestore(&clkout_lock, flags);
  701. return r;
  702. }
  703. int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
  704. {
  705. unsigned long flags;
  706. BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
  707. spin_lock_irqsave(&mb0_transfer.lock, flags);
  708. while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
  709. cpu_relax();
  710. writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
  711. writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
  712. writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
  713. writeb((keep_ulp_clk ? 1 : 0),
  714. (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
  715. writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
  716. writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
  717. spin_unlock_irqrestore(&mb0_transfer.lock, flags);
  718. return 0;
  719. }
  720. u8 db8500_prcmu_get_power_state_result(void)
  721. {
  722. return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
  723. }
  724. /* This function should only be called while mb0_transfer.lock is held. */
  725. static void config_wakeups(void)
  726. {
  727. const u8 header[2] = {
  728. MB0H_CONFIG_WAKEUPS_EXE,
  729. MB0H_CONFIG_WAKEUPS_SLEEP
  730. };
  731. static u32 last_dbb_events;
  732. static u32 last_abb_events;
  733. u32 dbb_events;
  734. u32 abb_events;
  735. unsigned int i;
  736. dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
  737. dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
  738. abb_events = mb0_transfer.req.abb_events;
  739. if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
  740. return;
  741. for (i = 0; i < 2; i++) {
  742. while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
  743. cpu_relax();
  744. writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
  745. writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
  746. writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
  747. writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
  748. }
  749. last_dbb_events = dbb_events;
  750. last_abb_events = abb_events;
  751. }
  752. void db8500_prcmu_enable_wakeups(u32 wakeups)
  753. {
  754. unsigned long flags;
  755. u32 bits;
  756. int i;
  757. BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
  758. for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
  759. if (wakeups & BIT(i))
  760. bits |= prcmu_wakeup_bit[i];
  761. }
  762. spin_lock_irqsave(&mb0_transfer.lock, flags);
  763. mb0_transfer.req.dbb_wakeups = bits;
  764. config_wakeups();
  765. spin_unlock_irqrestore(&mb0_transfer.lock, flags);
  766. }
  767. void db8500_prcmu_config_abb_event_readout(u32 abb_events)
  768. {
  769. unsigned long flags;
  770. spin_lock_irqsave(&mb0_transfer.lock, flags);
  771. mb0_transfer.req.abb_events = abb_events;
  772. config_wakeups();
  773. spin_unlock_irqrestore(&mb0_transfer.lock, flags);
  774. }
  775. void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
  776. {
  777. if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
  778. *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
  779. else
  780. *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
  781. }
  782. /**
  783. * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
  784. * @opp: The new ARM operating point to which transition is to be made
  785. * Returns: 0 on success, non-zero on failure
  786. *
  787. * This function sets the the operating point of the ARM.
  788. */
  789. int db8500_prcmu_set_arm_opp(u8 opp)
  790. {
  791. int r;
  792. if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
  793. return -EINVAL;
  794. r = 0;
  795. mutex_lock(&mb1_transfer.lock);
  796. while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
  797. cpu_relax();
  798. writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
  799. writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
  800. writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
  801. writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
  802. wait_for_completion(&mb1_transfer.work);
  803. if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
  804. (mb1_transfer.ack.arm_opp != opp))
  805. r = -EIO;
  806. mutex_unlock(&mb1_transfer.lock);
  807. return r;
  808. }
  809. /**
  810. * db8500_prcmu_get_arm_opp - get the current ARM OPP
  811. *
  812. * Returns: the current ARM OPP
  813. */
  814. int db8500_prcmu_get_arm_opp(void)
  815. {
  816. return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
  817. }
  818. /**
  819. * db8500_prcmu_get_ddr_opp - get the current DDR OPP
  820. *
  821. * Returns: the current DDR OPP
  822. */
  823. int db8500_prcmu_get_ddr_opp(void)
  824. {
  825. return readb(PRCM_DDR_SUBSYS_APE_MINBW);
  826. }
  827. /**
  828. * db8500_set_ddr_opp - set the appropriate DDR OPP
  829. * @opp: The new DDR operating point to which transition is to be made
  830. * Returns: 0 on success, non-zero on failure
  831. *
  832. * This function sets the operating point of the DDR.
  833. */
  834. static bool enable_set_ddr_opp;
  835. int db8500_prcmu_set_ddr_opp(u8 opp)
  836. {
  837. if (opp < DDR_100_OPP || opp > DDR_25_OPP)
  838. return -EINVAL;
  839. /* Changing the DDR OPP can hang the hardware pre-v21 */
  840. if (enable_set_ddr_opp)
  841. writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW);
  842. return 0;
  843. }
  844. /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
  845. static void request_even_slower_clocks(bool enable)
  846. {
  847. u32 clock_reg[] = {
  848. PRCM_ACLK_MGT,
  849. PRCM_DMACLK_MGT
  850. };
  851. unsigned long flags;
  852. unsigned int i;
  853. spin_lock_irqsave(&clk_mgt_lock, flags);
  854. /* Grab the HW semaphore. */
  855. while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
  856. cpu_relax();
  857. for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
  858. u32 val;
  859. u32 div;
  860. val = readl(prcmu_base + clock_reg[i]);
  861. div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
  862. if (enable) {
  863. if ((div <= 1) || (div > 15)) {
  864. pr_err("prcmu: Bad clock divider %d in %s\n",
  865. div, __func__);
  866. goto unlock_and_return;
  867. }
  868. div <<= 1;
  869. } else {
  870. if (div <= 2)
  871. goto unlock_and_return;
  872. div >>= 1;
  873. }
  874. val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
  875. (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
  876. writel(val, prcmu_base + clock_reg[i]);
  877. }
  878. unlock_and_return:
  879. /* Release the HW semaphore. */
  880. writel(0, PRCM_SEM);
  881. spin_unlock_irqrestore(&clk_mgt_lock, flags);
  882. }
  883. /**
  884. * db8500_set_ape_opp - set the appropriate APE OPP
  885. * @opp: The new APE operating point to which transition is to be made
  886. * Returns: 0 on success, non-zero on failure
  887. *
  888. * This function sets the operating point of the APE.
  889. */
  890. int db8500_prcmu_set_ape_opp(u8 opp)
  891. {
  892. int r = 0;
  893. if (opp == mb1_transfer.ape_opp)
  894. return 0;
  895. mutex_lock(&mb1_transfer.lock);
  896. if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
  897. request_even_slower_clocks(false);
  898. if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
  899. goto skip_message;
  900. while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
  901. cpu_relax();
  902. writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
  903. writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
  904. writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
  905. (tcdm_base + PRCM_REQ_MB1_APE_OPP));
  906. writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
  907. wait_for_completion(&mb1_transfer.work);
  908. if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
  909. (mb1_transfer.ack.ape_opp != opp))
  910. r = -EIO;
  911. skip_message:
  912. if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
  913. (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
  914. request_even_slower_clocks(true);
  915. if (!r)
  916. mb1_transfer.ape_opp = opp;
  917. mutex_unlock(&mb1_transfer.lock);
  918. return r;
  919. }
  920. /**
  921. * db8500_prcmu_get_ape_opp - get the current APE OPP
  922. *
  923. * Returns: the current APE OPP
  924. */
  925. int db8500_prcmu_get_ape_opp(void)
  926. {
  927. return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
  928. }
  929. /**
  930. * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
  931. * @enable: true to request the higher voltage, false to drop a request.
  932. *
  933. * Calls to this function to enable and disable requests must be balanced.
  934. */
  935. int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
  936. {
  937. int r = 0;
  938. u8 header;
  939. static unsigned int requests;
  940. mutex_lock(&mb1_transfer.lock);
  941. if (enable) {
  942. if (0 != requests++)
  943. goto unlock_and_return;
  944. header = MB1H_REQUEST_APE_OPP_100_VOLT;
  945. } else {
  946. if (requests == 0) {
  947. r = -EIO;
  948. goto unlock_and_return;
  949. } else if (1 != requests--) {
  950. goto unlock_and_return;
  951. }
  952. header = MB1H_RELEASE_APE_OPP_100_VOLT;
  953. }
  954. while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
  955. cpu_relax();
  956. writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
  957. writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
  958. wait_for_completion(&mb1_transfer.work);
  959. if ((mb1_transfer.ack.header != header) ||
  960. ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
  961. r = -EIO;
  962. unlock_and_return:
  963. mutex_unlock(&mb1_transfer.lock);
  964. return r;
  965. }
  966. /**
  967. * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
  968. *
  969. * This function releases the power state requirements of a USB wakeup.
  970. */
  971. int prcmu_release_usb_wakeup_state(void)
  972. {
  973. int r = 0;
  974. mutex_lock(&mb1_transfer.lock);
  975. while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
  976. cpu_relax();
  977. writeb(MB1H_RELEASE_USB_WAKEUP,
  978. (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
  979. writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
  980. wait_for_completion(&mb1_transfer.work);
  981. if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
  982. ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
  983. r = -EIO;
  984. mutex_unlock(&mb1_transfer.lock);
  985. return r;
  986. }
  987. static int request_pll(u8 clock, bool enable)
  988. {
  989. int r = 0;
  990. if (clock == PRCMU_PLLSOC0)
  991. clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
  992. else if (clock == PRCMU_PLLSOC1)
  993. clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
  994. else
  995. return -EINVAL;
  996. mutex_lock(&mb1_transfer.lock);
  997. while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
  998. cpu_relax();
  999. writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
  1000. writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
  1001. writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
  1002. wait_for_completion(&mb1_transfer.work);
  1003. if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
  1004. r = -EIO;
  1005. mutex_unlock(&mb1_transfer.lock);
  1006. return r;
  1007. }
  1008. /**
  1009. * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
  1010. * @epod_id: The EPOD to set
  1011. * @epod_state: The new EPOD state
  1012. *
  1013. * This function sets the state of a EPOD (power domain). It may not be called
  1014. * from interrupt context.
  1015. */
  1016. int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
  1017. {
  1018. int r = 0;
  1019. bool ram_retention = false;
  1020. int i;
  1021. /* check argument */
  1022. BUG_ON(epod_id >= NUM_EPOD_ID);
  1023. /* set flag if retention is possible */
  1024. switch (epod_id) {
  1025. case EPOD_ID_SVAMMDSP:
  1026. case EPOD_ID_SIAMMDSP:
  1027. case EPOD_ID_ESRAM12:
  1028. case EPOD_ID_ESRAM34:
  1029. ram_retention = true;
  1030. break;
  1031. }
  1032. /* check argument */
  1033. BUG_ON(epod_state > EPOD_STATE_ON);
  1034. BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
  1035. /* get lock */
  1036. mutex_lock(&mb2_transfer.lock);
  1037. /* wait for mailbox */
  1038. while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
  1039. cpu_relax();
  1040. /* fill in mailbox */
  1041. for (i = 0; i < NUM_EPOD_ID; i++)
  1042. writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
  1043. writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
  1044. writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
  1045. writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
  1046. /*
  1047. * The current firmware version does not handle errors correctly,
  1048. * and we cannot recover if there is an error.
  1049. * This is expected to change when the firmware is updated.
  1050. */
  1051. if (!wait_for_completion_timeout(&mb2_transfer.work,
  1052. msecs_to_jiffies(20000))) {
  1053. pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
  1054. __func__);
  1055. r = -EIO;
  1056. goto unlock_and_return;
  1057. }
  1058. if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
  1059. r = -EIO;
  1060. unlock_and_return:
  1061. mutex_unlock(&mb2_transfer.lock);
  1062. return r;
  1063. }
  1064. /**
  1065. * prcmu_configure_auto_pm - Configure autonomous power management.
  1066. * @sleep: Configuration for ApSleep.
  1067. * @idle: Configuration for ApIdle.
  1068. */
  1069. void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
  1070. struct prcmu_auto_pm_config *idle)
  1071. {
  1072. u32 sleep_cfg;
  1073. u32 idle_cfg;
  1074. unsigned long flags;
  1075. BUG_ON((sleep == NULL) || (idle == NULL));
  1076. sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
  1077. sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
  1078. sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
  1079. sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
  1080. sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
  1081. sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
  1082. idle_cfg = (idle->sva_auto_pm_enable & 0xF);
  1083. idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
  1084. idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
  1085. idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
  1086. idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
  1087. idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
  1088. spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
  1089. /*
  1090. * The autonomous power management configuration is done through
  1091. * fields in mailbox 2, but these fields are only used as shared
  1092. * variables - i.e. there is no need to send a message.
  1093. */
  1094. writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
  1095. writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
  1096. mb2_transfer.auto_pm_enabled =
  1097. ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
  1098. (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
  1099. (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
  1100. (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
  1101. spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
  1102. }
  1103. EXPORT_SYMBOL(prcmu_configure_auto_pm);
  1104. bool prcmu_is_auto_pm_enabled(void)
  1105. {
  1106. return mb2_transfer.auto_pm_enabled;
  1107. }
  1108. static int request_sysclk(bool enable)
  1109. {
  1110. int r;
  1111. unsigned long flags;
  1112. r = 0;
  1113. mutex_lock(&mb3_transfer.sysclk_lock);
  1114. spin_lock_irqsave(&mb3_transfer.lock, flags);
  1115. while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
  1116. cpu_relax();
  1117. writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
  1118. writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
  1119. writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
  1120. spin_unlock_irqrestore(&mb3_transfer.lock, flags);
  1121. /*
  1122. * The firmware only sends an ACK if we want to enable the
  1123. * SysClk, and it succeeds.
  1124. */
  1125. if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
  1126. msecs_to_jiffies(20000))) {
  1127. pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
  1128. __func__);
  1129. r = -EIO;
  1130. }
  1131. mutex_unlock(&mb3_transfer.sysclk_lock);
  1132. return r;
  1133. }
  1134. static int request_timclk(bool enable)
  1135. {
  1136. u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
  1137. if (!enable)
  1138. val |= PRCM_TCR_STOP_TIMERS;
  1139. writel(val, PRCM_TCR);
  1140. return 0;
  1141. }
  1142. static int request_clock(u8 clock, bool enable)
  1143. {
  1144. u32 val;
  1145. unsigned long flags;
  1146. spin_lock_irqsave(&clk_mgt_lock, flags);
  1147. /* Grab the HW semaphore. */
  1148. while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
  1149. cpu_relax();
  1150. val = readl(prcmu_base + clk_mgt[clock].offset);
  1151. if (enable) {
  1152. val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
  1153. } else {
  1154. clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
  1155. val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
  1156. }
  1157. writel(val, prcmu_base + clk_mgt[clock].offset);
  1158. /* Release the HW semaphore. */
  1159. writel(0, PRCM_SEM);
  1160. spin_unlock_irqrestore(&clk_mgt_lock, flags);
  1161. return 0;
  1162. }
  1163. static int request_sga_clock(u8 clock, bool enable)
  1164. {
  1165. u32 val;
  1166. int ret;
  1167. if (enable) {
  1168. val = readl(PRCM_CGATING_BYPASS);
  1169. writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
  1170. }
  1171. ret = request_clock(clock, enable);
  1172. if (!ret && !enable) {
  1173. val = readl(PRCM_CGATING_BYPASS);
  1174. writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
  1175. }
  1176. return ret;
  1177. }
  1178. static inline bool plldsi_locked(void)
  1179. {
  1180. return (readl(PRCM_PLLDSI_LOCKP) &
  1181. (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
  1182. PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
  1183. (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
  1184. PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
  1185. }
  1186. static int request_plldsi(bool enable)
  1187. {
  1188. int r = 0;
  1189. u32 val;
  1190. writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
  1191. PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
  1192. PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
  1193. val = readl(PRCM_PLLDSI_ENABLE);
  1194. if (enable)
  1195. val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
  1196. else
  1197. val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
  1198. writel(val, PRCM_PLLDSI_ENABLE);
  1199. if (enable) {
  1200. unsigned int i;
  1201. bool locked = plldsi_locked();
  1202. for (i = 10; !locked && (i > 0); --i) {
  1203. udelay(100);
  1204. locked = plldsi_locked();
  1205. }
  1206. if (locked) {
  1207. writel(PRCM_APE_RESETN_DSIPLL_RESETN,
  1208. PRCM_APE_RESETN_SET);
  1209. } else {
  1210. writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
  1211. PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
  1212. PRCM_MMIP_LS_CLAMP_SET);
  1213. val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
  1214. writel(val, PRCM_PLLDSI_ENABLE);
  1215. r = -EAGAIN;
  1216. }
  1217. } else {
  1218. writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
  1219. }
  1220. return r;
  1221. }
  1222. static int request_dsiclk(u8 n, bool enable)
  1223. {
  1224. u32 val;
  1225. val = readl(PRCM_DSI_PLLOUT_SEL);
  1226. val &= ~dsiclk[n].divsel_mask;
  1227. val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
  1228. dsiclk[n].divsel_shift);
  1229. writel(val, PRCM_DSI_PLLOUT_SEL);
  1230. return 0;
  1231. }
  1232. static int request_dsiescclk(u8 n, bool enable)
  1233. {
  1234. u32 val;
  1235. val = readl(PRCM_DSITVCLK_DIV);
  1236. enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
  1237. writel(val, PRCM_DSITVCLK_DIV);
  1238. return 0;
  1239. }
  1240. /**
  1241. * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
  1242. * @clock: The clock for which the request is made.
  1243. * @enable: Whether the clock should be enabled (true) or disabled (false).
  1244. *
  1245. * This function should only be used by the clock implementation.
  1246. * Do not use it from any other place!
  1247. */
  1248. int db8500_prcmu_request_clock(u8 clock, bool enable)
  1249. {
  1250. if (clock == PRCMU_SGACLK)
  1251. return request_sga_clock(clock, enable);
  1252. else if (clock < PRCMU_NUM_REG_CLOCKS)
  1253. return request_clock(clock, enable);
  1254. else if (clock == PRCMU_TIMCLK)
  1255. return request_timclk(enable);
  1256. else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
  1257. return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
  1258. else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
  1259. return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
  1260. else if (clock == PRCMU_PLLDSI)
  1261. return request_plldsi(enable);
  1262. else if (clock == PRCMU_SYSCLK)
  1263. return request_sysclk(enable);
  1264. else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
  1265. return request_pll(clock, enable);
  1266. else
  1267. return -EINVAL;
  1268. }
  1269. static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
  1270. int branch)
  1271. {
  1272. u64 rate;
  1273. u32 val;
  1274. u32 d;
  1275. u32 div = 1;
  1276. val = readl(reg);
  1277. rate = src_rate;
  1278. rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
  1279. d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
  1280. if (d > 1)
  1281. div *= d;
  1282. d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
  1283. if (d > 1)
  1284. div *= d;
  1285. if (val & PRCM_PLL_FREQ_SELDIV2)
  1286. div *= 2;
  1287. if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
  1288. (val & PRCM_PLL_FREQ_DIV2EN) &&
  1289. ((reg == PRCM_PLLSOC0_FREQ) ||
  1290. (reg == PRCM_PLLARM_FREQ) ||
  1291. (reg == PRCM_PLLDDR_FREQ))))
  1292. div *= 2;
  1293. (void)do_div(rate, div);
  1294. return (unsigned long)rate;
  1295. }
  1296. #define ROOT_CLOCK_RATE 38400000
  1297. static unsigned long clock_rate(u8 clock)
  1298. {
  1299. u32 val;
  1300. u32 pllsw;
  1301. unsigned long rate = ROOT_CLOCK_RATE;
  1302. val = readl(prcmu_base + clk_mgt[clock].offset);
  1303. if (val & PRCM_CLK_MGT_CLK38) {
  1304. if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
  1305. rate /= 2;
  1306. return rate;
  1307. }
  1308. val |= clk_mgt[clock].pllsw;
  1309. pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
  1310. if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
  1311. rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
  1312. else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
  1313. rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
  1314. else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
  1315. rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
  1316. else
  1317. return 0;
  1318. if ((clock == PRCMU_SGACLK) &&
  1319. (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
  1320. u64 r = (rate * 10);
  1321. (void)do_div(r, 25);
  1322. return (unsigned long)r;
  1323. }
  1324. val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
  1325. if (val)
  1326. return rate / val;
  1327. else
  1328. return 0;
  1329. }
  1330. static unsigned long armss_rate(void)
  1331. {
  1332. u32 r;
  1333. unsigned long rate;
  1334. r = readl(PRCM_ARM_CHGCLKREQ);
  1335. if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) {
  1336. /* External ARMCLKFIX clock */
  1337. rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
  1338. /* Check PRCM_ARM_CHGCLKREQ divider */
  1339. if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL))
  1340. rate /= 2;
  1341. /* Check PRCM_ARMCLKFIX_MGT divider */
  1342. r = readl(PRCM_ARMCLKFIX_MGT);
  1343. r &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
  1344. rate /= r;
  1345. } else {/* ARM PLL */
  1346. rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
  1347. }
  1348. return rate;
  1349. }
  1350. static unsigned long dsiclk_rate(u8 n)
  1351. {
  1352. u32 divsel;
  1353. u32 div = 1;
  1354. divsel = readl(PRCM_DSI_PLLOUT_SEL);
  1355. divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
  1356. if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
  1357. divsel = dsiclk[n].divsel;
  1358. switch (divsel) {
  1359. case PRCM_DSI_PLLOUT_SEL_PHI_4:
  1360. div *= 2;
  1361. case PRCM_DSI_PLLOUT_SEL_PHI_2:
  1362. div *= 2;
  1363. case PRCM_DSI_PLLOUT_SEL_PHI:
  1364. return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
  1365. PLL_RAW) / div;
  1366. default:
  1367. return 0;
  1368. }
  1369. }
  1370. static unsigned long dsiescclk_rate(u8 n)
  1371. {
  1372. u32 div;
  1373. div = readl(PRCM_DSITVCLK_DIV);
  1374. div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
  1375. return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
  1376. }
  1377. unsigned long prcmu_clock_rate(u8 clock)
  1378. {
  1379. if (clock < PRCMU_NUM_REG_CLOCKS)
  1380. return clock_rate(clock);
  1381. else if (clock == PRCMU_TIMCLK)
  1382. return ROOT_CLOCK_RATE / 16;
  1383. else if (clock == PRCMU_SYSCLK)
  1384. return ROOT_CLOCK_RATE;
  1385. else if (clock == PRCMU_PLLSOC0)
  1386. return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
  1387. else if (clock == PRCMU_PLLSOC1)
  1388. return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
  1389. else if (clock == PRCMU_ARMSS)
  1390. return armss_rate();
  1391. else if (clock == PRCMU_PLLDDR)
  1392. return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
  1393. else if (clock == PRCMU_PLLDSI)
  1394. return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
  1395. PLL_RAW);
  1396. else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
  1397. return dsiclk_rate(clock - PRCMU_DSI0CLK);
  1398. else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
  1399. return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
  1400. else
  1401. return 0;
  1402. }
  1403. static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
  1404. {
  1405. if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
  1406. return ROOT_CLOCK_RATE;
  1407. clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
  1408. if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
  1409. return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
  1410. else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
  1411. return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
  1412. else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
  1413. return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
  1414. else
  1415. return 0;
  1416. }
  1417. static u32 clock_divider(unsigned long src_rate, unsigned long rate)
  1418. {
  1419. u32 div;
  1420. div = (src_rate / rate);
  1421. if (div == 0)
  1422. return 1;
  1423. if (rate < (src_rate / div))
  1424. div++;
  1425. return div;
  1426. }
  1427. static long round_clock_rate(u8 clock, unsigned long rate)
  1428. {
  1429. u32 val;
  1430. u32 div;
  1431. unsigned long src_rate;
  1432. long rounded_rate;
  1433. val = readl(prcmu_base + clk_mgt[clock].offset);
  1434. src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
  1435. clk_mgt[clock].branch);
  1436. div = clock_divider(src_rate, rate);
  1437. if (val & PRCM_CLK_MGT_CLK38) {
  1438. if (clk_mgt[clock].clk38div) {
  1439. if (div > 2)
  1440. div = 2;
  1441. } else {
  1442. div = 1;
  1443. }
  1444. } else if ((clock == PRCMU_SGACLK) && (div == 3)) {
  1445. u64 r = (src_rate * 10);
  1446. (void)do_div(r, 25);
  1447. if (r <= rate)
  1448. return (unsigned long)r;
  1449. }
  1450. rounded_rate = (src_rate / min(div, (u32)31));
  1451. return rounded_rate;
  1452. }
  1453. /* CPU FREQ table, may be changed due to if MAX_OPP is supported. */
  1454. static struct cpufreq_frequency_table db8500_cpufreq_table[] = {
  1455. { .frequency = 200000, .index = ARM_EXTCLK,},
  1456. { .frequency = 400000, .index = ARM_50_OPP,},
  1457. { .frequency = 800000, .index = ARM_100_OPP,},
  1458. { .frequency = CPUFREQ_TABLE_END,}, /* To be used for MAX_OPP. */
  1459. { .frequency = CPUFREQ_TABLE_END,},
  1460. };
  1461. static long round_armss_rate(unsigned long rate)
  1462. {
  1463. long freq = 0;
  1464. int i = 0;
  1465. /* cpufreq table frequencies is in KHz. */
  1466. rate = rate / 1000;
  1467. /* Find the corresponding arm opp from the cpufreq table. */
  1468. while (db8500_cpufreq_table[i].frequency != CPUFREQ_TABLE_END) {
  1469. freq = db8500_cpufreq_table[i].frequency;
  1470. if (freq == rate)
  1471. break;
  1472. i++;
  1473. }
  1474. /* Return the last valid value, even if a match was not found. */
  1475. return freq * 1000;
  1476. }
  1477. #define MIN_PLL_VCO_RATE 600000000ULL
  1478. #define MAX_PLL_VCO_RATE 1680640000ULL
  1479. static long round_plldsi_rate(unsigned long rate)
  1480. {
  1481. long rounded_rate = 0;
  1482. unsigned long src_rate;
  1483. unsigned long rem;
  1484. u32 r;
  1485. src_rate = clock_rate(PRCMU_HDMICLK);
  1486. rem = rate;
  1487. for (r = 7; (rem > 0) && (r > 0); r--) {
  1488. u64 d;
  1489. d = (r * rate);
  1490. (void)do_div(d, src_rate);
  1491. if (d < 6)
  1492. d = 6;
  1493. else if (d > 255)
  1494. d = 255;
  1495. d *= src_rate;
  1496. if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
  1497. ((r * MAX_PLL_VCO_RATE) < (2 * d)))
  1498. continue;
  1499. (void)do_div(d, r);
  1500. if (rate < d) {
  1501. if (rounded_rate == 0)
  1502. rounded_rate = (long)d;
  1503. break;
  1504. }
  1505. if ((rate - d) < rem) {
  1506. rem = (rate - d);
  1507. rounded_rate = (long)d;
  1508. }
  1509. }
  1510. return rounded_rate;
  1511. }
  1512. static long round_dsiclk_rate(unsigned long rate)
  1513. {
  1514. u32 div;
  1515. unsigned long src_rate;
  1516. long rounded_rate;
  1517. src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
  1518. PLL_RAW);
  1519. div = clock_divider(src_rate, rate);
  1520. rounded_rate = (src_rate / ((div > 2) ? 4 : div));
  1521. return rounded_rate;
  1522. }
  1523. static long round_dsiescclk_rate(unsigned long rate)
  1524. {
  1525. u32 div;
  1526. unsigned long src_rate;
  1527. long rounded_rate;
  1528. src_rate = clock_rate(PRCMU_TVCLK);
  1529. div = clock_divider(src_rate, rate);
  1530. rounded_rate = (src_rate / min(div, (u32)255));
  1531. return rounded_rate;
  1532. }
  1533. long prcmu_round_clock_rate(u8 clock, unsigned long rate)
  1534. {
  1535. if (clock < PRCMU_NUM_REG_CLOCKS)
  1536. return round_clock_rate(clock, rate);
  1537. else if (clock == PRCMU_ARMSS)
  1538. return round_armss_rate(rate);
  1539. else if (clock == PRCMU_PLLDSI)
  1540. return round_plldsi_rate(rate);
  1541. else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
  1542. return round_dsiclk_rate(rate);
  1543. else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
  1544. return round_dsiescclk_rate(rate);
  1545. else
  1546. return (long)prcmu_clock_rate(clock);
  1547. }
  1548. static void set_clock_rate(u8 clock, unsigned long rate)
  1549. {
  1550. u32 val;
  1551. u32 div;
  1552. unsigned long src_rate;
  1553. unsigned long flags;
  1554. spin_lock_irqsave(&clk_mgt_lock, flags);
  1555. /* Grab the HW semaphore. */
  1556. while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
  1557. cpu_relax();
  1558. val = readl(prcmu_base + clk_mgt[clock].offset);
  1559. src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
  1560. clk_mgt[clock].branch);
  1561. div = clock_divider(src_rate, rate);
  1562. if (val & PRCM_CLK_MGT_CLK38) {
  1563. if (clk_mgt[clock].clk38div) {
  1564. if (div > 1)
  1565. val |= PRCM_CLK_MGT_CLK38DIV;
  1566. else
  1567. val &= ~PRCM_CLK_MGT_CLK38DIV;
  1568. }
  1569. } else if (clock == PRCMU_SGACLK) {
  1570. val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
  1571. PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
  1572. if (div == 3) {
  1573. u64 r = (src_rate * 10);
  1574. (void)do_div(r, 25);
  1575. if (r <= rate) {
  1576. val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
  1577. div = 0;
  1578. }
  1579. }
  1580. val |= min(div, (u32)31);
  1581. } else {
  1582. val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
  1583. val |= min(div, (u32)31);
  1584. }
  1585. writel(val, prcmu_base + clk_mgt[clock].offset);
  1586. /* Release the HW semaphore. */
  1587. writel(0, PRCM_SEM);
  1588. spin_unlock_irqrestore(&clk_mgt_lock, flags);
  1589. }
  1590. static int set_armss_rate(unsigned long rate)
  1591. {
  1592. int i = 0;
  1593. /* cpufreq table frequencies is in KHz. */
  1594. rate = rate / 1000;
  1595. /* Find the corresponding arm opp from the cpufreq table. */
  1596. while (db8500_cpufreq_table[i].frequency != CPUFREQ_TABLE_END) {
  1597. if (db8500_cpufreq_table[i].frequency == rate)
  1598. break;
  1599. i++;
  1600. }
  1601. if (db8500_cpufreq_table[i].frequency != rate)
  1602. return -EINVAL;
  1603. /* Set the new arm opp. */
  1604. return db8500_prcmu_set_arm_opp(db8500_cpufreq_table[i].index);
  1605. }
  1606. static int set_plldsi_rate(unsigned long rate)
  1607. {
  1608. unsigned long src_rate;
  1609. unsigned long rem;
  1610. u32 pll_freq = 0;
  1611. u32 r;
  1612. src_rate = clock_rate(PRCMU_HDMICLK);
  1613. rem = rate;
  1614. for (r = 7; (rem > 0) && (r > 0); r--) {
  1615. u64 d;
  1616. u64 hwrate;
  1617. d = (r * rate);
  1618. (void)do_div(d, src_rate);
  1619. if (d < 6)
  1620. d = 6;
  1621. else if (d > 255)
  1622. d = 255;
  1623. hwrate = (d * src_rate);
  1624. if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
  1625. ((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
  1626. continue;
  1627. (void)do_div(hwrate, r);
  1628. if (rate < hwrate) {
  1629. if (pll_freq == 0)
  1630. pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
  1631. (r << PRCM_PLL_FREQ_R_SHIFT));
  1632. break;
  1633. }
  1634. if ((rate - hwrate) < rem) {
  1635. rem = (rate - hwrate);
  1636. pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
  1637. (r << PRCM_PLL_FREQ_R_SHIFT));
  1638. }
  1639. }
  1640. if (pll_freq == 0)
  1641. return -EINVAL;
  1642. pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
  1643. writel(pll_freq, PRCM_PLLDSI_FREQ);
  1644. return 0;
  1645. }
  1646. static void set_dsiclk_rate(u8 n, unsigned long rate)
  1647. {
  1648. u32 val;
  1649. u32 div;
  1650. div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
  1651. clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
  1652. dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
  1653. (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
  1654. /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4;
  1655. val = readl(PRCM_DSI_PLLOUT_SEL);
  1656. val &= ~dsiclk[n].divsel_mask;
  1657. val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
  1658. writel(val, PRCM_DSI_PLLOUT_SEL);
  1659. }
  1660. static void set_dsiescclk_rate(u8 n, unsigned long rate)
  1661. {
  1662. u32 val;
  1663. u32 div;
  1664. div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
  1665. val = readl(PRCM_DSITVCLK_DIV);
  1666. val &= ~dsiescclk[n].div_mask;
  1667. val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
  1668. writel(val, PRCM_DSITVCLK_DIV);
  1669. }
  1670. int prcmu_set_clock_rate(u8 clock, unsigned long rate)
  1671. {
  1672. if (clock < PRCMU_NUM_REG_CLOCKS)
  1673. set_clock_rate(clock, rate);
  1674. else if (clock == PRCMU_ARMSS)
  1675. return set_armss_rate(rate);
  1676. else if (clock == PRCMU_PLLDSI)
  1677. return set_plldsi_rate(rate);
  1678. else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
  1679. set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
  1680. else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
  1681. set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
  1682. return 0;
  1683. }
  1684. int db8500_prcmu_config_esram0_deep_sleep(u8 state)
  1685. {
  1686. if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
  1687. (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
  1688. return -EINVAL;
  1689. mutex_lock(&mb4_transfer.lock);
  1690. while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
  1691. cpu_relax();
  1692. writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
  1693. writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
  1694. (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
  1695. writeb(DDR_PWR_STATE_ON,
  1696. (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
  1697. writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
  1698. writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
  1699. wait_for_completion(&mb4_transfer.work);
  1700. mutex_unlock(&mb4_transfer.lock);
  1701. return 0;
  1702. }
  1703. int db8500_prcmu_config_hotdog(u8 threshold)
  1704. {
  1705. mutex_lock(&mb4_transfer.lock);
  1706. while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
  1707. cpu_relax();
  1708. writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
  1709. writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
  1710. writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
  1711. wait_for_completion(&mb4_transfer.work);
  1712. mutex_unlock(&mb4_transfer.lock);
  1713. return 0;
  1714. }
  1715. int db8500_prcmu_config_hotmon(u8 low, u8 high)
  1716. {
  1717. mutex_lock(&mb4_transfer.lock);
  1718. while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
  1719. cpu_relax();
  1720. writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
  1721. writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
  1722. writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
  1723. (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
  1724. writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
  1725. writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
  1726. wait_for_completion(&mb4_transfer.work);
  1727. mutex_unlock(&mb4_transfer.lock);
  1728. return 0;
  1729. }
  1730. static int config_hot_period(u16 val)
  1731. {
  1732. mutex_lock(&mb4_transfer.lock);
  1733. while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
  1734. cpu_relax();
  1735. writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
  1736. writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
  1737. writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
  1738. wait_for_completion(&mb4_transfer.work);
  1739. mutex_unlock(&mb4_transfer.lock);
  1740. return 0;
  1741. }
  1742. int db8500_prcmu_start_temp_sense(u16 cycles32k)
  1743. {
  1744. if (cycles32k == 0xFFFF)
  1745. return -EINVAL;
  1746. return config_hot_period(cycles32k);
  1747. }
  1748. int db8500_prcmu_stop_temp_sense(void)
  1749. {
  1750. return config_hot_period(0xFFFF);
  1751. }
  1752. static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
  1753. {
  1754. mutex_lock(&mb4_transfer.lock);
  1755. while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
  1756. cpu_relax();
  1757. writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
  1758. writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
  1759. writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
  1760. writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
  1761. writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
  1762. writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
  1763. wait_for_completion(&mb4_transfer.work);
  1764. mutex_unlock(&mb4_transfer.lock);
  1765. return 0;
  1766. }
  1767. int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
  1768. {
  1769. BUG_ON(num == 0 || num > 0xf);
  1770. return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
  1771. sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
  1772. A9WDOG_AUTO_OFF_DIS);
  1773. }
  1774. EXPORT_SYMBOL(db8500_prcmu_config_a9wdog);
  1775. int db8500_prcmu_enable_a9wdog(u8 id)
  1776. {
  1777. return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
  1778. }
  1779. EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog);
  1780. int db8500_prcmu_disable_a9wdog(u8 id)
  1781. {
  1782. return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
  1783. }
  1784. EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog);
  1785. int db8500_prcmu_kick_a9wdog(u8 id)
  1786. {
  1787. return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
  1788. }
  1789. EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog);
  1790. /*
  1791. * timeout is 28 bit, in ms.
  1792. */
  1793. int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
  1794. {
  1795. return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
  1796. (id & A9WDOG_ID_MASK) |
  1797. /*
  1798. * Put the lowest 28 bits of timeout at
  1799. * offset 4. Four first bits are used for id.
  1800. */
  1801. (u8)((timeout << 4) & 0xf0),
  1802. (u8)((timeout >> 4) & 0xff),
  1803. (u8)((timeout >> 12) & 0xff),
  1804. (u8)((timeout >> 20) & 0xff));
  1805. }
  1806. EXPORT_SYMBOL(db8500_prcmu_load_a9wdog);
  1807. /**
  1808. * prcmu_abb_read() - Read register value(s) from the ABB.
  1809. * @slave: The I2C slave address.
  1810. * @reg: The (start) register address.
  1811. * @value: The read out value(s).
  1812. * @size: The number of registers to read.
  1813. *
  1814. * Reads register value(s) from the ABB.
  1815. * @size has to be 1 for the current firmware version.
  1816. */
  1817. int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
  1818. {
  1819. int r;
  1820. if (size != 1)
  1821. return -EINVAL;
  1822. mutex_lock(&mb5_transfer.lock);
  1823. while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
  1824. cpu_relax();
  1825. writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
  1826. writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
  1827. writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
  1828. writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
  1829. writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
  1830. writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
  1831. if (!wait_for_completion_timeout(&mb5_transfer.work,
  1832. msecs_to_jiffies(20000))) {
  1833. pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
  1834. __func__);
  1835. r = -EIO;
  1836. } else {
  1837. r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
  1838. }
  1839. if (!r)
  1840. *value = mb5_transfer.ack.value;
  1841. mutex_unlock(&mb5_transfer.lock);
  1842. return r;
  1843. }
  1844. /**
  1845. * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
  1846. * @slave: The I2C slave address.
  1847. * @reg: The (start) register address.
  1848. * @value: The value(s) to write.
  1849. * @mask: The mask(s) to use.
  1850. * @size: The number of registers to write.
  1851. *
  1852. * Writes masked register value(s) to the ABB.
  1853. * For each @value, only the bits set to 1 in the corresponding @mask
  1854. * will be written. The other bits are not changed.
  1855. * @size has to be 1 for the current firmware version.
  1856. */
  1857. int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size)
  1858. {
  1859. int r;
  1860. if (size != 1)
  1861. return -EINVAL;
  1862. mutex_lock(&mb5_transfer.lock);
  1863. while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
  1864. cpu_relax();
  1865. writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
  1866. writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
  1867. writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
  1868. writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
  1869. writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
  1870. writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
  1871. if (!wait_for_completion_timeout(&mb5_transfer.work,
  1872. msecs_to_jiffies(20000))) {
  1873. pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
  1874. __func__);
  1875. r = -EIO;
  1876. } else {
  1877. r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
  1878. }
  1879. mutex_unlock(&mb5_transfer.lock);
  1880. return r;
  1881. }
  1882. /**
  1883. * prcmu_abb_write() - Write register value(s) to the ABB.
  1884. * @slave: The I2C slave address.
  1885. * @reg: The (start) register address.
  1886. * @value: The value(s) to write.
  1887. * @size: The number of registers to write.
  1888. *
  1889. * Writes register value(s) to the ABB.
  1890. * @size has to be 1 for the current firmware version.
  1891. */
  1892. int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
  1893. {
  1894. u8 mask = ~0;
  1895. return prcmu_abb_write_masked(slave, reg, value, &mask, size);
  1896. }
  1897. /**
  1898. * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
  1899. */
  1900. int prcmu_ac_wake_req(void)
  1901. {
  1902. u32 val;
  1903. int ret = 0;
  1904. mutex_lock(&mb0_transfer.ac_wake_lock);
  1905. val = readl(PRCM_HOSTACCESS_REQ);
  1906. if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
  1907. goto unlock_and_return;
  1908. atomic_set(&ac_wake_req_state, 1);
  1909. /*
  1910. * Force Modem Wake-up before hostaccess_req ping-pong.
  1911. * It prevents Modem to enter in Sleep while acking the hostaccess
  1912. * request. The 31us delay has been calculated by HWI.
  1913. */
  1914. val |= PRCM_HOSTACCESS_REQ_WAKE_REQ;
  1915. writel(val, PRCM_HOSTACCESS_REQ);
  1916. udelay(31);
  1917. val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ;
  1918. writel(val, PRCM_HOSTACCESS_REQ);
  1919. if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
  1920. msecs_to_jiffies(5000))) {
  1921. #if defined(CONFIG_DBX500_PRCMU_DEBUG)
  1922. db8500_prcmu_debug_dump(__func__, true, true);
  1923. #endif
  1924. pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
  1925. __func__);
  1926. ret = -EFAULT;
  1927. }
  1928. unlock_and_return:
  1929. mutex_unlock(&mb0_transfer.ac_wake_lock);
  1930. return ret;
  1931. }
  1932. /**
  1933. * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
  1934. */
  1935. void prcmu_ac_sleep_req()
  1936. {
  1937. u32 val;
  1938. mutex_lock(&mb0_transfer.ac_wake_lock);
  1939. val = readl(PRCM_HOSTACCESS_REQ);
  1940. if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
  1941. goto unlock_and_return;
  1942. writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
  1943. PRCM_HOSTACCESS_REQ);
  1944. if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
  1945. msecs_to_jiffies(5000))) {
  1946. pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
  1947. __func__);
  1948. }
  1949. atomic_set(&ac_wake_req_state, 0);
  1950. unlock_and_return:
  1951. mutex_unlock(&mb0_transfer.ac_wake_lock);
  1952. }
  1953. bool db8500_prcmu_is_ac_wake_requested(void)
  1954. {
  1955. return (atomic_read(&ac_wake_req_state) != 0);
  1956. }
  1957. /**
  1958. * db8500_prcmu_system_reset - System reset
  1959. *
  1960. * Saves the reset reason code and then sets the APE_SOFTRST register which
  1961. * fires interrupt to fw
  1962. */
  1963. void db8500_prcmu_system_reset(u16 reset_code)
  1964. {
  1965. writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
  1966. writel(1, PRCM_APE_SOFTRST);
  1967. }
  1968. /**
  1969. * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
  1970. *
  1971. * Retrieves the reset reason code stored by prcmu_system_reset() before
  1972. * last restart.
  1973. */
  1974. u16 db8500_prcmu_get_reset_code(void)
  1975. {
  1976. return readw(tcdm_base + PRCM_SW_RST_REASON);
  1977. }
  1978. /**
  1979. * db8500_prcmu_reset_modem - ask the PRCMU to reset modem
  1980. */
  1981. void db8500_prcmu_modem_reset(void)
  1982. {
  1983. mutex_lock(&mb1_transfer.lock);
  1984. while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
  1985. cpu_relax();
  1986. writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
  1987. writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
  1988. wait_for_completion(&mb1_transfer.work);
  1989. /*
  1990. * No need to check return from PRCMU as modem should go in reset state
  1991. * This state is already managed by upper layer
  1992. */
  1993. mutex_unlock(&mb1_transfer.lock);
  1994. }
  1995. static void ack_dbb_wakeup(void)
  1996. {
  1997. unsigned long flags;
  1998. spin_lock_irqsave(&mb0_transfer.lock, flags);
  1999. while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
  2000. cpu_relax();
  2001. writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
  2002. writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
  2003. spin_unlock_irqrestore(&mb0_transfer.lock, flags);
  2004. }
  2005. static inline void print_unknown_header_warning(u8 n, u8 header)
  2006. {
  2007. pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
  2008. header, n);
  2009. }
  2010. static bool read_mailbox_0(void)
  2011. {
  2012. bool r;
  2013. u32 ev;
  2014. unsigned int n;
  2015. u8 header;
  2016. header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
  2017. switch (header) {
  2018. case MB0H_WAKEUP_EXE:
  2019. case MB0H_WAKEUP_SLEEP:
  2020. if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
  2021. ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
  2022. else
  2023. ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
  2024. if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
  2025. complete(&mb0_transfer.ac_wake_work);
  2026. if (ev & WAKEUP_BIT_SYSCLK_OK)
  2027. complete(&mb3_transfer.sysclk_work);
  2028. ev &= mb0_transfer.req.dbb_irqs;
  2029. for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
  2030. if (ev & prcmu_irq_bit[n])
  2031. generic_handle_irq(irq_find_mapping(db8500_irq_domain, n));
  2032. }
  2033. r = true;
  2034. break;
  2035. default:
  2036. print_unknown_header_warning(0, header);
  2037. r = false;
  2038. break;
  2039. }
  2040. writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
  2041. return r;
  2042. }
  2043. static bool read_mailbox_1(void)
  2044. {
  2045. mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
  2046. mb1_transfer.ack.arm_opp = readb(tcdm_base +
  2047. PRCM_ACK_MB1_CURRENT_ARM_OPP);
  2048. mb1_transfer.ack.ape_opp = readb(tcdm_base +
  2049. PRCM_ACK_MB1_CURRENT_APE_OPP);
  2050. mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
  2051. PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
  2052. writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
  2053. complete(&mb1_transfer.work);
  2054. return false;
  2055. }
  2056. static bool read_mailbox_2(void)
  2057. {
  2058. mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
  2059. writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
  2060. complete(&mb2_transfer.work);
  2061. return false;
  2062. }
  2063. static bool read_mailbox_3(void)
  2064. {
  2065. writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
  2066. return false;
  2067. }
  2068. static bool read_mailbox_4(void)
  2069. {
  2070. u8 header;
  2071. bool do_complete = true;
  2072. header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
  2073. switch (header) {
  2074. case MB4H_MEM_ST:
  2075. case MB4H_HOTDOG:
  2076. case MB4H_HOTMON:
  2077. case MB4H_HOT_PERIOD:
  2078. case MB4H_A9WDOG_CONF:
  2079. case MB4H_A9WDOG_EN:
  2080. case MB4H_A9WDOG_DIS:
  2081. case MB4H_A9WDOG_LOAD:
  2082. case MB4H_A9WDOG_KICK:
  2083. break;
  2084. default:
  2085. print_unknown_header_warning(4, header);
  2086. do_complete = false;
  2087. break;
  2088. }
  2089. writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
  2090. if (do_complete)
  2091. complete(&mb4_transfer.work);
  2092. return false;
  2093. }
  2094. static bool read_mailbox_5(void)
  2095. {
  2096. mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
  2097. mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
  2098. writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
  2099. complete(&mb5_transfer.work);
  2100. return false;
  2101. }
  2102. static bool read_mailbox_6(void)
  2103. {
  2104. writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
  2105. return false;
  2106. }
  2107. static bool read_mailbox_7(void)
  2108. {
  2109. writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
  2110. return false;
  2111. }
  2112. static bool (* const read_mailbox[NUM_MB])(void) = {
  2113. read_mailbox_0,
  2114. read_mailbox_1,
  2115. read_mailbox_2,
  2116. read_mailbox_3,
  2117. read_mailbox_4,
  2118. read_mailbox_5,
  2119. read_mailbox_6,
  2120. read_mailbox_7
  2121. };
  2122. static irqreturn_t prcmu_irq_handler(int irq, void *data)
  2123. {
  2124. u32 bits;
  2125. u8 n;
  2126. irqreturn_t r;
  2127. bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
  2128. if (unlikely(!bits))
  2129. return IRQ_NONE;
  2130. r = IRQ_HANDLED;
  2131. for (n = 0; bits; n++) {
  2132. if (bits & MBOX_BIT(n)) {
  2133. bits -= MBOX_BIT(n);
  2134. if (read_mailbox[n]())
  2135. r = IRQ_WAKE_THREAD;
  2136. }
  2137. }
  2138. return r;
  2139. }
  2140. static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
  2141. {
  2142. ack_dbb_wakeup();
  2143. return IRQ_HANDLED;
  2144. }
  2145. static void prcmu_mask_work(struct work_struct *work)
  2146. {
  2147. unsigned long flags;
  2148. spin_lock_irqsave(&mb0_transfer.lock, flags);
  2149. config_wakeups();
  2150. spin_unlock_irqrestore(&mb0_transfer.lock, flags);
  2151. }
  2152. static void prcmu_irq_mask(struct irq_data *d)
  2153. {
  2154. unsigned long flags;
  2155. spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
  2156. mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq];
  2157. spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
  2158. if (d->irq != IRQ_PRCMU_CA_SLEEP)
  2159. schedule_work(&mb0_transfer.mask_work);
  2160. }
  2161. static void prcmu_irq_unmask(struct irq_data *d)
  2162. {
  2163. unsigned long flags;
  2164. spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
  2165. mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq];
  2166. spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
  2167. if (d->irq != IRQ_PRCMU_CA_SLEEP)
  2168. schedule_work(&mb0_transfer.mask_work);
  2169. }
  2170. static void noop(struct irq_data *d)
  2171. {
  2172. }
  2173. static struct irq_chip prcmu_irq_chip = {
  2174. .name = "prcmu",
  2175. .irq_disable = prcmu_irq_mask,
  2176. .irq_ack = noop,
  2177. .irq_mask = prcmu_irq_mask,
  2178. .irq_unmask = prcmu_irq_unmask,
  2179. };
  2180. static __init char *fw_project_name(u32 project)
  2181. {
  2182. switch (project) {
  2183. case PRCMU_FW_PROJECT_U8500:
  2184. return "U8500";
  2185. case PRCMU_FW_PROJECT_U8400:
  2186. return "U8400";
  2187. case PRCMU_FW_PROJECT_U9500:
  2188. return "U9500";
  2189. case PRCMU_FW_PROJECT_U8500_MBB:
  2190. return "U8500 MBB";
  2191. case PRCMU_FW_PROJECT_U8500_C1:
  2192. return "U8500 C1";
  2193. case PRCMU_FW_PROJECT_U8500_C2:
  2194. return "U8500 C2";
  2195. case PRCMU_FW_PROJECT_U8500_C3:
  2196. return "U8500 C3";
  2197. case PRCMU_FW_PROJECT_U8500_C4:
  2198. return "U8500 C4";
  2199. case PRCMU_FW_PROJECT_U9500_MBL:
  2200. return "U9500 MBL";
  2201. case PRCMU_FW_PROJECT_U8500_MBL:
  2202. return "U8500 MBL";
  2203. case PRCMU_FW_PROJECT_U8500_MBL2:
  2204. return "U8500 MBL2";
  2205. case PRCMU_FW_PROJECT_U8520:
  2206. return "U8520 MBL";
  2207. case PRCMU_FW_PROJECT_U8420:
  2208. return "U8420";
  2209. case PRCMU_FW_PROJECT_U9540:
  2210. return "U9540";
  2211. case PRCMU_FW_PROJECT_A9420:
  2212. return "A9420";
  2213. case PRCMU_FW_PROJECT_L8540:
  2214. return "L8540";
  2215. case PRCMU_FW_PROJECT_L8580:
  2216. return "L8580";
  2217. default:
  2218. return "Unknown";
  2219. }
  2220. }
  2221. static int db8500_irq_map(struct irq_domain *d, unsigned int virq,
  2222. irq_hw_number_t hwirq)
  2223. {
  2224. irq_set_chip_and_handler(virq, &prcmu_irq_chip,
  2225. handle_simple_irq);
  2226. set_irq_flags(virq, IRQF_VALID);
  2227. return 0;
  2228. }
  2229. static struct irq_domain_ops db8500_irq_ops = {
  2230. .map = db8500_irq_map,
  2231. .xlate = irq_domain_xlate_twocell,
  2232. };
  2233. static int db8500_irq_init(struct device_node *np, int irq_base)
  2234. {
  2235. int i;
  2236. /* In the device tree case, just take some IRQs */
  2237. if (np)
  2238. irq_base = 0;
  2239. db8500_irq_domain = irq_domain_add_simple(
  2240. np, NUM_PRCMU_WAKEUPS, irq_base,
  2241. &db8500_irq_ops, NULL);
  2242. if (!db8500_irq_domain) {
  2243. pr_err("Failed to create irqdomain\n");
  2244. return -ENOSYS;
  2245. }
  2246. /* All wakeups will be used, so create mappings for all */
  2247. for (i = 0; i < NUM_PRCMU_WAKEUPS; i++)
  2248. irq_create_mapping(db8500_irq_domain, i);
  2249. return 0;
  2250. }
  2251. static void dbx500_fw_version_init(struct platform_device *pdev,
  2252. u32 version_offset)
  2253. {
  2254. struct resource *res;
  2255. void __iomem *tcpm_base;
  2256. u32 version;
  2257. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  2258. "prcmu-tcpm");
  2259. if (!res) {
  2260. dev_err(&pdev->dev,
  2261. "Error: no prcmu tcpm memory region provided\n");
  2262. return;
  2263. }
  2264. tcpm_base = ioremap(res->start, resource_size(res));
  2265. if (!tcpm_base) {
  2266. dev_err(&pdev->dev, "no prcmu tcpm mem region provided\n");
  2267. return;
  2268. }
  2269. version = readl(tcpm_base + version_offset);
  2270. fw_info.version.project = (version & 0xFF);
  2271. fw_info.version.api_version = (version >> 8) & 0xFF;
  2272. fw_info.version.func_version = (version >> 16) & 0xFF;
  2273. fw_info.version.errata = (version >> 24) & 0xFF;
  2274. strncpy(fw_info.version.project_name,
  2275. fw_project_name(fw_info.version.project),
  2276. PRCMU_FW_PROJECT_NAME_LEN);
  2277. fw_info.valid = true;
  2278. pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n",
  2279. fw_info.version.project_name,
  2280. fw_info.version.project,
  2281. fw_info.version.api_version,
  2282. fw_info.version.func_version,
  2283. fw_info.version.errata);
  2284. iounmap(tcpm_base);
  2285. }
  2286. void __init db8500_prcmu_early_init(u32 phy_base, u32 size)
  2287. {
  2288. /*
  2289. * This is a temporary remap to bring up the clocks. It is
  2290. * subsequently replaces with a real remap. After the merge of
  2291. * the mailbox subsystem all of this early code goes away, and the
  2292. * clock driver can probe independently. An early initcall will
  2293. * still be needed, but it can be diverted into drivers/clk/ux500.
  2294. */
  2295. prcmu_base = ioremap(phy_base, size);
  2296. if (!prcmu_base)
  2297. pr_err("%s: ioremap() of prcmu registers failed!\n", __func__);
  2298. spin_lock_init(&mb0_transfer.lock);
  2299. spin_lock_init(&mb0_transfer.dbb_irqs_lock);
  2300. mutex_init(&mb0_transfer.ac_wake_lock);
  2301. init_completion(&mb0_transfer.ac_wake_work);
  2302. mutex_init(&mb1_transfer.lock);
  2303. init_completion(&mb1_transfer.work);
  2304. mb1_transfer.ape_opp = APE_NO_CHANGE;
  2305. mutex_init(&mb2_transfer.lock);
  2306. init_completion(&mb2_transfer.work);
  2307. spin_lock_init(&mb2_transfer.auto_pm_lock);
  2308. spin_lock_init(&mb3_transfer.lock);
  2309. mutex_init(&mb3_transfer.sysclk_lock);
  2310. init_completion(&mb3_transfer.sysclk_work);
  2311. mutex_init(&mb4_transfer.lock);
  2312. init_completion(&mb4_transfer.work);
  2313. mutex_init(&mb5_transfer.lock);
  2314. init_completion(&mb5_transfer.work);
  2315. INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
  2316. }
  2317. static void __init init_prcm_registers(void)
  2318. {
  2319. u32 val;
  2320. val = readl(PRCM_A9PL_FORCE_CLKEN);
  2321. val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
  2322. PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
  2323. writel(val, (PRCM_A9PL_FORCE_CLKEN));
  2324. }
  2325. /*
  2326. * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
  2327. */
  2328. static struct regulator_consumer_supply db8500_vape_consumers[] = {
  2329. REGULATOR_SUPPLY("v-ape", NULL),
  2330. REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
  2331. REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
  2332. REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
  2333. REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
  2334. REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"),
  2335. /* "v-mmc" changed to "vcore" in the mainline kernel */
  2336. REGULATOR_SUPPLY("vcore", "sdi0"),
  2337. REGULATOR_SUPPLY("vcore", "sdi1"),
  2338. REGULATOR_SUPPLY("vcore", "sdi2"),
  2339. REGULATOR_SUPPLY("vcore", "sdi3"),
  2340. REGULATOR_SUPPLY("vcore", "sdi4"),
  2341. REGULATOR_SUPPLY("v-dma", "dma40.0"),
  2342. REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
  2343. /* "v-uart" changed to "vcore" in the mainline kernel */
  2344. REGULATOR_SUPPLY("vcore", "uart0"),
  2345. REGULATOR_SUPPLY("vcore", "uart1"),
  2346. REGULATOR_SUPPLY("vcore", "uart2"),
  2347. REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
  2348. REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
  2349. REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
  2350. };
  2351. static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
  2352. REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
  2353. /* AV8100 regulator */
  2354. REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
  2355. };
  2356. static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
  2357. REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
  2358. REGULATOR_SUPPLY("vsupply", "mcde"),
  2359. };
  2360. /* SVA MMDSP regulator switch */
  2361. static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
  2362. REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
  2363. };
  2364. /* SVA pipe regulator switch */
  2365. static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
  2366. REGULATOR_SUPPLY("sva-pipe", "cm_control"),
  2367. };
  2368. /* SIA MMDSP regulator switch */
  2369. static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
  2370. REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
  2371. };
  2372. /* SIA pipe regulator switch */
  2373. static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
  2374. REGULATOR_SUPPLY("sia-pipe", "cm_control"),
  2375. };
  2376. static struct regulator_consumer_supply db8500_sga_consumers[] = {
  2377. REGULATOR_SUPPLY("v-mali", NULL),
  2378. };
  2379. /* ESRAM1 and 2 regulator switch */
  2380. static struct regulator_consumer_supply db8500_esram12_consumers[] = {
  2381. REGULATOR_SUPPLY("esram12", "cm_control"),
  2382. };
  2383. /* ESRAM3 and 4 regulator switch */
  2384. static struct regulator_consumer_supply db8500_esram34_consumers[] = {
  2385. REGULATOR_SUPPLY("v-esram34", "mcde"),
  2386. REGULATOR_SUPPLY("esram34", "cm_control"),
  2387. REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
  2388. };
  2389. static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
  2390. [DB8500_REGULATOR_VAPE] = {
  2391. .constraints = {
  2392. .name = "db8500-vape",
  2393. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  2394. .always_on = true,
  2395. },
  2396. .consumer_supplies = db8500_vape_consumers,
  2397. .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
  2398. },
  2399. [DB8500_REGULATOR_VARM] = {
  2400. .constraints = {
  2401. .name = "db8500-varm",
  2402. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  2403. },
  2404. },
  2405. [DB8500_REGULATOR_VMODEM] = {
  2406. .constraints = {
  2407. .name = "db8500-vmodem",
  2408. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  2409. },
  2410. },
  2411. [DB8500_REGULATOR_VPLL] = {
  2412. .constraints = {
  2413. .name = "db8500-vpll",
  2414. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  2415. },
  2416. },
  2417. [DB8500_REGULATOR_VSMPS1] = {
  2418. .constraints = {
  2419. .name = "db8500-vsmps1",
  2420. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  2421. },
  2422. },
  2423. [DB8500_REGULATOR_VSMPS2] = {
  2424. .constraints = {
  2425. .name = "db8500-vsmps2",
  2426. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  2427. },
  2428. .consumer_supplies = db8500_vsmps2_consumers,
  2429. .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
  2430. },
  2431. [DB8500_REGULATOR_VSMPS3] = {
  2432. .constraints = {
  2433. .name = "db8500-vsmps3",
  2434. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  2435. },
  2436. },
  2437. [DB8500_REGULATOR_VRF1] = {
  2438. .constraints = {
  2439. .name = "db8500-vrf1",
  2440. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  2441. },
  2442. },
  2443. [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
  2444. /* dependency to u8500-vape is handled outside regulator framework */
  2445. .constraints = {
  2446. .name = "db8500-sva-mmdsp",
  2447. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  2448. },
  2449. .consumer_supplies = db8500_svammdsp_consumers,
  2450. .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
  2451. },
  2452. [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
  2453. .constraints = {
  2454. /* "ret" means "retention" */
  2455. .name = "db8500-sva-mmdsp-ret",
  2456. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  2457. },
  2458. },
  2459. [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
  2460. /* dependency to u8500-vape is handled outside regulator framework */
  2461. .constraints = {
  2462. .name = "db8500-sva-pipe",
  2463. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  2464. },
  2465. .consumer_supplies = db8500_svapipe_consumers,
  2466. .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
  2467. },
  2468. [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
  2469. /* dependency to u8500-vape is handled outside regulator framework */
  2470. .constraints = {
  2471. .name = "db8500-sia-mmdsp",
  2472. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  2473. },
  2474. .consumer_supplies = db8500_siammdsp_consumers,
  2475. .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
  2476. },
  2477. [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
  2478. .constraints = {
  2479. .name = "db8500-sia-mmdsp-ret",
  2480. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  2481. },
  2482. },
  2483. [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
  2484. /* dependency to u8500-vape is handled outside regulator framework */
  2485. .constraints = {
  2486. .name = "db8500-sia-pipe",
  2487. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  2488. },
  2489. .consumer_supplies = db8500_siapipe_consumers,
  2490. .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
  2491. },
  2492. [DB8500_REGULATOR_SWITCH_SGA] = {
  2493. .supply_regulator = "db8500-vape",
  2494. .constraints = {
  2495. .name = "db8500-sga",
  2496. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  2497. },
  2498. .consumer_supplies = db8500_sga_consumers,
  2499. .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
  2500. },
  2501. [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
  2502. .supply_regulator = "db8500-vape",
  2503. .constraints = {
  2504. .name = "db8500-b2r2-mcde",
  2505. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  2506. },
  2507. .consumer_supplies = db8500_b2r2_mcde_consumers,
  2508. .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
  2509. },
  2510. [DB8500_REGULATOR_SWITCH_ESRAM12] = {
  2511. /*
  2512. * esram12 is set in retention and supplied by Vsafe when Vape is off,
  2513. * no need to hold Vape
  2514. */
  2515. .constraints = {
  2516. .name = "db8500-esram12",
  2517. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  2518. },
  2519. .consumer_supplies = db8500_esram12_consumers,
  2520. .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
  2521. },
  2522. [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
  2523. .constraints = {
  2524. .name = "db8500-esram12-ret",
  2525. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  2526. },
  2527. },
  2528. [DB8500_REGULATOR_SWITCH_ESRAM34] = {
  2529. /*
  2530. * esram34 is set in retention and supplied by Vsafe when Vape is off,
  2531. * no need to hold Vape
  2532. */
  2533. .constraints = {
  2534. .name = "db8500-esram34",
  2535. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  2536. },
  2537. .consumer_supplies = db8500_esram34_consumers,
  2538. .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
  2539. },
  2540. [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
  2541. .constraints = {
  2542. .name = "db8500-esram34-ret",
  2543. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  2544. },
  2545. },
  2546. };
  2547. static struct ux500_wdt_data db8500_wdt_pdata = {
  2548. .timeout = 600, /* 10 minutes */
  2549. .has_28_bits_resolution = true,
  2550. };
  2551. /*
  2552. * Thermal Sensor
  2553. */
  2554. static struct resource db8500_thsens_resources[] = {
  2555. {
  2556. .name = "IRQ_HOTMON_LOW",
  2557. .start = IRQ_PRCMU_HOTMON_LOW,
  2558. .end = IRQ_PRCMU_HOTMON_LOW,
  2559. .flags = IORESOURCE_IRQ,
  2560. },
  2561. {
  2562. .name = "IRQ_HOTMON_HIGH",
  2563. .start = IRQ_PRCMU_HOTMON_HIGH,
  2564. .end = IRQ_PRCMU_HOTMON_HIGH,
  2565. .flags = IORESOURCE_IRQ,
  2566. },
  2567. };
  2568. static struct db8500_thsens_platform_data db8500_thsens_data = {
  2569. .trip_points[0] = {
  2570. .temp = 70000,
  2571. .type = THERMAL_TRIP_ACTIVE,
  2572. .cdev_name = {
  2573. [0] = "thermal-cpufreq-0",
  2574. },
  2575. },
  2576. .trip_points[1] = {
  2577. .temp = 75000,
  2578. .type = THERMAL_TRIP_ACTIVE,
  2579. .cdev_name = {
  2580. [0] = "thermal-cpufreq-0",
  2581. },
  2582. },
  2583. .trip_points[2] = {
  2584. .temp = 80000,
  2585. .type = THERMAL_TRIP_ACTIVE,
  2586. .cdev_name = {
  2587. [0] = "thermal-cpufreq-0",
  2588. },
  2589. },
  2590. .trip_points[3] = {
  2591. .temp = 85000,
  2592. .type = THERMAL_TRIP_CRITICAL,
  2593. },
  2594. .num_trips = 4,
  2595. };
  2596. static struct mfd_cell common_prcmu_devs[] = {
  2597. {
  2598. .name = "ux500_wdt",
  2599. .platform_data = &db8500_wdt_pdata,
  2600. .pdata_size = sizeof(db8500_wdt_pdata),
  2601. .id = -1,
  2602. },
  2603. };
  2604. static struct mfd_cell db8500_prcmu_devs[] = {
  2605. {
  2606. .name = "db8500-prcmu-regulators",
  2607. .of_compatible = "stericsson,db8500-prcmu-regulator",
  2608. .platform_data = &db8500_regulators,
  2609. .pdata_size = sizeof(db8500_regulators),
  2610. },
  2611. {
  2612. .name = "cpufreq-ux500",
  2613. .of_compatible = "stericsson,cpufreq-ux500",
  2614. .platform_data = &db8500_cpufreq_table,
  2615. .pdata_size = sizeof(db8500_cpufreq_table),
  2616. },
  2617. {
  2618. .name = "db8500-thermal",
  2619. .num_resources = ARRAY_SIZE(db8500_thsens_resources),
  2620. .resources = db8500_thsens_resources,
  2621. .platform_data = &db8500_thsens_data,
  2622. },
  2623. };
  2624. static void db8500_prcmu_update_cpufreq(void)
  2625. {
  2626. if (prcmu_has_arm_maxopp()) {
  2627. db8500_cpufreq_table[3].frequency = 1000000;
  2628. db8500_cpufreq_table[3].index = ARM_MAX_OPP;
  2629. }
  2630. }
  2631. static int db8500_prcmu_register_ab8500(struct device *parent,
  2632. struct ab8500_platform_data *pdata,
  2633. int irq)
  2634. {
  2635. struct resource ab8500_resource = DEFINE_RES_IRQ(irq);
  2636. struct mfd_cell ab8500_cell = {
  2637. .name = "ab8500-core",
  2638. .of_compatible = "stericsson,ab8500",
  2639. .id = AB8500_VERSION_AB8500,
  2640. .platform_data = pdata,
  2641. .pdata_size = sizeof(struct ab8500_platform_data),
  2642. .resources = &ab8500_resource,
  2643. .num_resources = 1,
  2644. };
  2645. return mfd_add_devices(parent, 0, &ab8500_cell, 1, NULL, 0, NULL);
  2646. }
  2647. /**
  2648. * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
  2649. *
  2650. */
  2651. static int db8500_prcmu_probe(struct platform_device *pdev)
  2652. {
  2653. struct device_node *np = pdev->dev.of_node;
  2654. struct prcmu_pdata *pdata = dev_get_platdata(&pdev->dev);
  2655. int irq = 0, err = 0;
  2656. struct resource *res;
  2657. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu");
  2658. if (!res) {
  2659. dev_err(&pdev->dev, "no prcmu memory region provided\n");
  2660. return -ENOENT;
  2661. }
  2662. prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
  2663. if (!prcmu_base) {
  2664. dev_err(&pdev->dev,
  2665. "failed to ioremap prcmu register memory\n");
  2666. return -ENOENT;
  2667. }
  2668. init_prcm_registers();
  2669. dbx500_fw_version_init(pdev, pdata->version_offset);
  2670. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm");
  2671. if (!res) {
  2672. dev_err(&pdev->dev, "no prcmu tcdm region provided\n");
  2673. return -ENOENT;
  2674. }
  2675. tcdm_base = devm_ioremap(&pdev->dev, res->start,
  2676. resource_size(res));
  2677. /* Clean up the mailbox interrupts after pre-kernel code. */
  2678. writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
  2679. irq = platform_get_irq(pdev, 0);
  2680. if (irq <= 0) {
  2681. dev_err(&pdev->dev, "no prcmu irq provided\n");
  2682. return -ENOENT;
  2683. }
  2684. err = request_threaded_irq(irq, prcmu_irq_handler,
  2685. prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
  2686. if (err < 0) {
  2687. pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
  2688. err = -EBUSY;
  2689. goto no_irq_return;
  2690. }
  2691. db8500_irq_init(np, pdata->irq_base);
  2692. prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
  2693. db8500_prcmu_update_cpufreq();
  2694. err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs,
  2695. ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain);
  2696. if (err) {
  2697. pr_err("prcmu: Failed to add subdevices\n");
  2698. return err;
  2699. }
  2700. /* TODO: Remove restriction when clk definitions are available. */
  2701. if (!of_machine_is_compatible("st-ericsson,u8540")) {
  2702. err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
  2703. ARRAY_SIZE(db8500_prcmu_devs), NULL, 0,
  2704. db8500_irq_domain);
  2705. if (err) {
  2706. mfd_remove_devices(&pdev->dev);
  2707. pr_err("prcmu: Failed to add subdevices\n");
  2708. goto no_irq_return;
  2709. }
  2710. }
  2711. err = db8500_prcmu_register_ab8500(&pdev->dev, pdata->ab_platdata,
  2712. pdata->ab_irq);
  2713. if (err) {
  2714. mfd_remove_devices(&pdev->dev);
  2715. pr_err("prcmu: Failed to add ab8500 subdevice\n");
  2716. goto no_irq_return;
  2717. }
  2718. pr_info("DB8500 PRCMU initialized\n");
  2719. no_irq_return:
  2720. return err;
  2721. }
  2722. static const struct of_device_id db8500_prcmu_match[] = {
  2723. { .compatible = "stericsson,db8500-prcmu"},
  2724. { },
  2725. };
  2726. static struct platform_driver db8500_prcmu_driver = {
  2727. .driver = {
  2728. .name = "db8500-prcmu",
  2729. .owner = THIS_MODULE,
  2730. .of_match_table = db8500_prcmu_match,
  2731. },
  2732. .probe = db8500_prcmu_probe,
  2733. };
  2734. static int __init db8500_prcmu_init(void)
  2735. {
  2736. return platform_driver_register(&db8500_prcmu_driver);
  2737. }
  2738. core_initcall(db8500_prcmu_init);
  2739. MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>");
  2740. MODULE_DESCRIPTION("DB8500 PRCM Unit driver");
  2741. MODULE_LICENSE("GPL v2");