arizona-core.c 20 KB

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  1. /*
  2. * Arizona core driver
  3. *
  4. * Copyright 2012 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/err.h>
  14. #include <linux/gpio.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/mfd/core.h>
  17. #include <linux/module.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/regmap.h>
  20. #include <linux/regulator/consumer.h>
  21. #include <linux/slab.h>
  22. #include <linux/mfd/arizona/core.h>
  23. #include <linux/mfd/arizona/registers.h>
  24. #include "arizona.h"
  25. static const char *wm5102_core_supplies[] = {
  26. "AVDD",
  27. "DBVDD1",
  28. };
  29. int arizona_clk32k_enable(struct arizona *arizona)
  30. {
  31. int ret = 0;
  32. mutex_lock(&arizona->clk_lock);
  33. arizona->clk32k_ref++;
  34. if (arizona->clk32k_ref == 1) {
  35. switch (arizona->pdata.clk32k_src) {
  36. case ARIZONA_32KZ_MCLK1:
  37. ret = pm_runtime_get_sync(arizona->dev);
  38. if (ret != 0)
  39. goto out;
  40. break;
  41. }
  42. ret = regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  43. ARIZONA_CLK_32K_ENA,
  44. ARIZONA_CLK_32K_ENA);
  45. }
  46. out:
  47. if (ret != 0)
  48. arizona->clk32k_ref--;
  49. mutex_unlock(&arizona->clk_lock);
  50. return ret;
  51. }
  52. EXPORT_SYMBOL_GPL(arizona_clk32k_enable);
  53. int arizona_clk32k_disable(struct arizona *arizona)
  54. {
  55. int ret = 0;
  56. mutex_lock(&arizona->clk_lock);
  57. BUG_ON(arizona->clk32k_ref <= 0);
  58. arizona->clk32k_ref--;
  59. if (arizona->clk32k_ref == 0) {
  60. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  61. ARIZONA_CLK_32K_ENA, 0);
  62. switch (arizona->pdata.clk32k_src) {
  63. case ARIZONA_32KZ_MCLK1:
  64. pm_runtime_put_sync(arizona->dev);
  65. break;
  66. }
  67. }
  68. mutex_unlock(&arizona->clk_lock);
  69. return ret;
  70. }
  71. EXPORT_SYMBOL_GPL(arizona_clk32k_disable);
  72. static irqreturn_t arizona_clkgen_err(int irq, void *data)
  73. {
  74. struct arizona *arizona = data;
  75. dev_err(arizona->dev, "CLKGEN error\n");
  76. return IRQ_HANDLED;
  77. }
  78. static irqreturn_t arizona_underclocked(int irq, void *data)
  79. {
  80. struct arizona *arizona = data;
  81. unsigned int val;
  82. int ret;
  83. ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_8,
  84. &val);
  85. if (ret != 0) {
  86. dev_err(arizona->dev, "Failed to read underclock status: %d\n",
  87. ret);
  88. return IRQ_NONE;
  89. }
  90. if (val & ARIZONA_AIF3_UNDERCLOCKED_STS)
  91. dev_err(arizona->dev, "AIF3 underclocked\n");
  92. if (val & ARIZONA_AIF2_UNDERCLOCKED_STS)
  93. dev_err(arizona->dev, "AIF2 underclocked\n");
  94. if (val & ARIZONA_AIF1_UNDERCLOCKED_STS)
  95. dev_err(arizona->dev, "AIF1 underclocked\n");
  96. if (val & ARIZONA_ISRC2_UNDERCLOCKED_STS)
  97. dev_err(arizona->dev, "ISRC2 underclocked\n");
  98. if (val & ARIZONA_ISRC1_UNDERCLOCKED_STS)
  99. dev_err(arizona->dev, "ISRC1 underclocked\n");
  100. if (val & ARIZONA_FX_UNDERCLOCKED_STS)
  101. dev_err(arizona->dev, "FX underclocked\n");
  102. if (val & ARIZONA_ASRC_UNDERCLOCKED_STS)
  103. dev_err(arizona->dev, "ASRC underclocked\n");
  104. if (val & ARIZONA_DAC_UNDERCLOCKED_STS)
  105. dev_err(arizona->dev, "DAC underclocked\n");
  106. if (val & ARIZONA_ADC_UNDERCLOCKED_STS)
  107. dev_err(arizona->dev, "ADC underclocked\n");
  108. if (val & ARIZONA_MIXER_UNDERCLOCKED_STS)
  109. dev_err(arizona->dev, "Mixer dropped sample\n");
  110. return IRQ_HANDLED;
  111. }
  112. static irqreturn_t arizona_overclocked(int irq, void *data)
  113. {
  114. struct arizona *arizona = data;
  115. unsigned int val[2];
  116. int ret;
  117. ret = regmap_bulk_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_6,
  118. &val[0], 2);
  119. if (ret != 0) {
  120. dev_err(arizona->dev, "Failed to read overclock status: %d\n",
  121. ret);
  122. return IRQ_NONE;
  123. }
  124. if (val[0] & ARIZONA_PWM_OVERCLOCKED_STS)
  125. dev_err(arizona->dev, "PWM overclocked\n");
  126. if (val[0] & ARIZONA_FX_CORE_OVERCLOCKED_STS)
  127. dev_err(arizona->dev, "FX core overclocked\n");
  128. if (val[0] & ARIZONA_DAC_SYS_OVERCLOCKED_STS)
  129. dev_err(arizona->dev, "DAC SYS overclocked\n");
  130. if (val[0] & ARIZONA_DAC_WARP_OVERCLOCKED_STS)
  131. dev_err(arizona->dev, "DAC WARP overclocked\n");
  132. if (val[0] & ARIZONA_ADC_OVERCLOCKED_STS)
  133. dev_err(arizona->dev, "ADC overclocked\n");
  134. if (val[0] & ARIZONA_MIXER_OVERCLOCKED_STS)
  135. dev_err(arizona->dev, "Mixer overclocked\n");
  136. if (val[0] & ARIZONA_AIF3_SYNC_OVERCLOCKED_STS)
  137. dev_err(arizona->dev, "AIF3 overclocked\n");
  138. if (val[0] & ARIZONA_AIF2_SYNC_OVERCLOCKED_STS)
  139. dev_err(arizona->dev, "AIF2 overclocked\n");
  140. if (val[0] & ARIZONA_AIF1_SYNC_OVERCLOCKED_STS)
  141. dev_err(arizona->dev, "AIF1 overclocked\n");
  142. if (val[0] & ARIZONA_PAD_CTRL_OVERCLOCKED_STS)
  143. dev_err(arizona->dev, "Pad control overclocked\n");
  144. if (val[1] & ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS)
  145. dev_err(arizona->dev, "Slimbus subsystem overclocked\n");
  146. if (val[1] & ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS)
  147. dev_err(arizona->dev, "Slimbus async overclocked\n");
  148. if (val[1] & ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS)
  149. dev_err(arizona->dev, "Slimbus sync overclocked\n");
  150. if (val[1] & ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS)
  151. dev_err(arizona->dev, "ASRC async system overclocked\n");
  152. if (val[1] & ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS)
  153. dev_err(arizona->dev, "ASRC async WARP overclocked\n");
  154. if (val[1] & ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS)
  155. dev_err(arizona->dev, "ASRC sync system overclocked\n");
  156. if (val[1] & ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS)
  157. dev_err(arizona->dev, "ASRC sync WARP overclocked\n");
  158. if (val[1] & ARIZONA_ADSP2_1_OVERCLOCKED_STS)
  159. dev_err(arizona->dev, "DSP1 overclocked\n");
  160. if (val[1] & ARIZONA_ISRC2_OVERCLOCKED_STS)
  161. dev_err(arizona->dev, "ISRC2 overclocked\n");
  162. if (val[1] & ARIZONA_ISRC1_OVERCLOCKED_STS)
  163. dev_err(arizona->dev, "ISRC1 overclocked\n");
  164. return IRQ_HANDLED;
  165. }
  166. static int arizona_poll_reg(struct arizona *arizona,
  167. int timeout, unsigned int reg,
  168. unsigned int mask, unsigned int target)
  169. {
  170. unsigned int val = 0;
  171. int ret, i;
  172. for (i = 0; i < timeout; i++) {
  173. ret = regmap_read(arizona->regmap, reg, &val);
  174. if (ret != 0) {
  175. dev_err(arizona->dev, "Failed to read reg %u: %d\n",
  176. reg, ret);
  177. continue;
  178. }
  179. if ((val & mask) == target)
  180. return 0;
  181. msleep(1);
  182. }
  183. dev_err(arizona->dev, "Polling reg %u timed out: %x\n", reg, val);
  184. return -ETIMEDOUT;
  185. }
  186. static int arizona_wait_for_boot(struct arizona *arizona)
  187. {
  188. int ret;
  189. /*
  190. * We can't use an interrupt as we need to runtime resume to do so,
  191. * we won't race with the interrupt handler as it'll be blocked on
  192. * runtime resume.
  193. */
  194. ret = arizona_poll_reg(arizona, 5, ARIZONA_INTERRUPT_RAW_STATUS_5,
  195. ARIZONA_BOOT_DONE_STS, ARIZONA_BOOT_DONE_STS);
  196. if (!ret)
  197. regmap_write(arizona->regmap, ARIZONA_INTERRUPT_STATUS_5,
  198. ARIZONA_BOOT_DONE_STS);
  199. pm_runtime_mark_last_busy(arizona->dev);
  200. return ret;
  201. }
  202. static int arizona_apply_hardware_patch(struct arizona* arizona)
  203. {
  204. unsigned int fll, sysclk;
  205. int ret, err;
  206. regcache_cache_bypass(arizona->regmap, true);
  207. /* Cache existing FLL and SYSCLK settings */
  208. ret = regmap_read(arizona->regmap, ARIZONA_FLL1_CONTROL_1, &fll);
  209. if (ret != 0) {
  210. dev_err(arizona->dev, "Failed to cache FLL settings: %d\n",
  211. ret);
  212. return ret;
  213. }
  214. ret = regmap_read(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, &sysclk);
  215. if (ret != 0) {
  216. dev_err(arizona->dev, "Failed to cache SYSCLK settings: %d\n",
  217. ret);
  218. return ret;
  219. }
  220. /* Start up SYSCLK using the FLL in free running mode */
  221. ret = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1,
  222. ARIZONA_FLL1_ENA | ARIZONA_FLL1_FREERUN);
  223. if (ret != 0) {
  224. dev_err(arizona->dev,
  225. "Failed to start FLL in freerunning mode: %d\n",
  226. ret);
  227. return ret;
  228. }
  229. ret = arizona_poll_reg(arizona, 25, ARIZONA_INTERRUPT_RAW_STATUS_5,
  230. ARIZONA_FLL1_CLOCK_OK_STS,
  231. ARIZONA_FLL1_CLOCK_OK_STS);
  232. if (ret != 0) {
  233. ret = -ETIMEDOUT;
  234. goto err_fll;
  235. }
  236. ret = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, 0x0144);
  237. if (ret != 0) {
  238. dev_err(arizona->dev, "Failed to start SYSCLK: %d\n", ret);
  239. goto err_fll;
  240. }
  241. /* Start the write sequencer and wait for it to finish */
  242. ret = regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0,
  243. ARIZONA_WSEQ_ENA | ARIZONA_WSEQ_START | 160);
  244. if (ret != 0) {
  245. dev_err(arizona->dev, "Failed to start write sequencer: %d\n",
  246. ret);
  247. goto err_sysclk;
  248. }
  249. ret = arizona_poll_reg(arizona, 5, ARIZONA_WRITE_SEQUENCER_CTRL_1,
  250. ARIZONA_WSEQ_BUSY, 0);
  251. if (ret != 0) {
  252. regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0,
  253. ARIZONA_WSEQ_ABORT);
  254. ret = -ETIMEDOUT;
  255. }
  256. err_sysclk:
  257. err = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, sysclk);
  258. if (err != 0) {
  259. dev_err(arizona->dev,
  260. "Failed to re-apply old SYSCLK settings: %d\n",
  261. err);
  262. }
  263. err_fll:
  264. err = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1, fll);
  265. if (err != 0) {
  266. dev_err(arizona->dev,
  267. "Failed to re-apply old FLL settings: %d\n",
  268. err);
  269. }
  270. regcache_cache_bypass(arizona->regmap, false);
  271. if (ret != 0)
  272. return ret;
  273. else
  274. return err;
  275. }
  276. #ifdef CONFIG_PM_RUNTIME
  277. static int arizona_runtime_resume(struct device *dev)
  278. {
  279. struct arizona *arizona = dev_get_drvdata(dev);
  280. int ret;
  281. dev_dbg(arizona->dev, "Leaving AoD mode\n");
  282. ret = regulator_enable(arizona->dcvdd);
  283. if (ret != 0) {
  284. dev_err(arizona->dev, "Failed to enable DCVDD: %d\n", ret);
  285. return ret;
  286. }
  287. regcache_cache_only(arizona->regmap, false);
  288. switch (arizona->type) {
  289. case WM5102:
  290. ret = wm5102_patch(arizona);
  291. if (ret != 0) {
  292. dev_err(arizona->dev, "Failed to apply patch: %d\n",
  293. ret);
  294. goto err;
  295. }
  296. ret = arizona_apply_hardware_patch(arizona);
  297. if (ret != 0) {
  298. dev_err(arizona->dev,
  299. "Failed to apply hardware patch: %d\n",
  300. ret);
  301. goto err;
  302. }
  303. break;
  304. default:
  305. ret = arizona_wait_for_boot(arizona);
  306. if (ret != 0) {
  307. goto err;
  308. }
  309. break;
  310. }
  311. ret = regcache_sync(arizona->regmap);
  312. if (ret != 0) {
  313. dev_err(arizona->dev, "Failed to restore register cache\n");
  314. goto err;
  315. }
  316. return 0;
  317. err:
  318. regcache_cache_only(arizona->regmap, true);
  319. regulator_disable(arizona->dcvdd);
  320. return ret;
  321. }
  322. static int arizona_runtime_suspend(struct device *dev)
  323. {
  324. struct arizona *arizona = dev_get_drvdata(dev);
  325. dev_dbg(arizona->dev, "Entering AoD mode\n");
  326. regulator_disable(arizona->dcvdd);
  327. regcache_cache_only(arizona->regmap, true);
  328. regcache_mark_dirty(arizona->regmap);
  329. return 0;
  330. }
  331. #endif
  332. #ifdef CONFIG_PM_SLEEP
  333. static int arizona_resume_noirq(struct device *dev)
  334. {
  335. struct arizona *arizona = dev_get_drvdata(dev);
  336. dev_dbg(arizona->dev, "Early resume, disabling IRQ\n");
  337. disable_irq(arizona->irq);
  338. return 0;
  339. }
  340. static int arizona_resume(struct device *dev)
  341. {
  342. struct arizona *arizona = dev_get_drvdata(dev);
  343. dev_dbg(arizona->dev, "Late resume, reenabling IRQ\n");
  344. enable_irq(arizona->irq);
  345. return 0;
  346. }
  347. #endif
  348. const struct dev_pm_ops arizona_pm_ops = {
  349. SET_RUNTIME_PM_OPS(arizona_runtime_suspend,
  350. arizona_runtime_resume,
  351. NULL)
  352. SET_SYSTEM_SLEEP_PM_OPS(NULL, arizona_resume)
  353. #ifdef CONFIG_PM_SLEEP
  354. .resume_noirq = arizona_resume_noirq,
  355. #endif
  356. };
  357. EXPORT_SYMBOL_GPL(arizona_pm_ops);
  358. static struct mfd_cell early_devs[] = {
  359. { .name = "arizona-ldo1" },
  360. };
  361. static struct mfd_cell wm5102_devs[] = {
  362. { .name = "arizona-micsupp" },
  363. { .name = "arizona-extcon" },
  364. { .name = "arizona-gpio" },
  365. { .name = "arizona-haptics" },
  366. { .name = "arizona-pwm" },
  367. { .name = "wm5102-codec" },
  368. };
  369. static struct mfd_cell wm5110_devs[] = {
  370. { .name = "arizona-micsupp" },
  371. { .name = "arizona-extcon" },
  372. { .name = "arizona-gpio" },
  373. { .name = "arizona-haptics" },
  374. { .name = "arizona-pwm" },
  375. { .name = "wm5110-codec" },
  376. };
  377. int arizona_dev_init(struct arizona *arizona)
  378. {
  379. struct device *dev = arizona->dev;
  380. const char *type_name;
  381. unsigned int reg, val;
  382. int (*apply_patch)(struct arizona *) = NULL;
  383. int ret, i;
  384. dev_set_drvdata(arizona->dev, arizona);
  385. mutex_init(&arizona->clk_lock);
  386. if (dev_get_platdata(arizona->dev))
  387. memcpy(&arizona->pdata, dev_get_platdata(arizona->dev),
  388. sizeof(arizona->pdata));
  389. regcache_cache_only(arizona->regmap, true);
  390. switch (arizona->type) {
  391. case WM5102:
  392. case WM5110:
  393. for (i = 0; i < ARRAY_SIZE(wm5102_core_supplies); i++)
  394. arizona->core_supplies[i].supply
  395. = wm5102_core_supplies[i];
  396. arizona->num_core_supplies = ARRAY_SIZE(wm5102_core_supplies);
  397. break;
  398. default:
  399. dev_err(arizona->dev, "Unknown device type %d\n",
  400. arizona->type);
  401. return -EINVAL;
  402. }
  403. ret = mfd_add_devices(arizona->dev, -1, early_devs,
  404. ARRAY_SIZE(early_devs), NULL, 0, NULL);
  405. if (ret != 0) {
  406. dev_err(dev, "Failed to add early children: %d\n", ret);
  407. return ret;
  408. }
  409. ret = devm_regulator_bulk_get(dev, arizona->num_core_supplies,
  410. arizona->core_supplies);
  411. if (ret != 0) {
  412. dev_err(dev, "Failed to request core supplies: %d\n",
  413. ret);
  414. goto err_early;
  415. }
  416. arizona->dcvdd = devm_regulator_get(arizona->dev, "DCVDD");
  417. if (IS_ERR(arizona->dcvdd)) {
  418. ret = PTR_ERR(arizona->dcvdd);
  419. dev_err(dev, "Failed to request DCVDD: %d\n", ret);
  420. goto err_early;
  421. }
  422. if (arizona->pdata.reset) {
  423. /* Start out with /RESET low to put the chip into reset */
  424. ret = gpio_request_one(arizona->pdata.reset,
  425. GPIOF_DIR_OUT | GPIOF_INIT_LOW,
  426. "arizona /RESET");
  427. if (ret != 0) {
  428. dev_err(dev, "Failed to request /RESET: %d\n", ret);
  429. goto err_early;
  430. }
  431. }
  432. ret = regulator_bulk_enable(arizona->num_core_supplies,
  433. arizona->core_supplies);
  434. if (ret != 0) {
  435. dev_err(dev, "Failed to enable core supplies: %d\n",
  436. ret);
  437. goto err_early;
  438. }
  439. ret = regulator_enable(arizona->dcvdd);
  440. if (ret != 0) {
  441. dev_err(dev, "Failed to enable DCVDD: %d\n", ret);
  442. goto err_enable;
  443. }
  444. if (arizona->pdata.reset) {
  445. gpio_set_value_cansleep(arizona->pdata.reset, 1);
  446. msleep(1);
  447. }
  448. regcache_cache_only(arizona->regmap, false);
  449. ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, &reg);
  450. if (ret != 0) {
  451. dev_err(dev, "Failed to read ID register: %d\n", ret);
  452. goto err_reset;
  453. }
  454. ret = regmap_read(arizona->regmap, ARIZONA_DEVICE_REVISION,
  455. &arizona->rev);
  456. if (ret != 0) {
  457. dev_err(dev, "Failed to read revision register: %d\n", ret);
  458. goto err_reset;
  459. }
  460. arizona->rev &= ARIZONA_DEVICE_REVISION_MASK;
  461. switch (reg) {
  462. #ifdef CONFIG_MFD_WM5102
  463. case 0x5102:
  464. type_name = "WM5102";
  465. if (arizona->type != WM5102) {
  466. dev_err(arizona->dev, "WM5102 registered as %d\n",
  467. arizona->type);
  468. arizona->type = WM5102;
  469. }
  470. apply_patch = wm5102_patch;
  471. arizona->rev &= 0x7;
  472. break;
  473. #endif
  474. #ifdef CONFIG_MFD_WM5110
  475. case 0x5110:
  476. type_name = "WM5110";
  477. if (arizona->type != WM5110) {
  478. dev_err(arizona->dev, "WM5110 registered as %d\n",
  479. arizona->type);
  480. arizona->type = WM5110;
  481. }
  482. apply_patch = wm5110_patch;
  483. break;
  484. #endif
  485. default:
  486. dev_err(arizona->dev, "Unknown device ID %x\n", reg);
  487. goto err_reset;
  488. }
  489. dev_info(dev, "%s revision %c\n", type_name, arizona->rev + 'A');
  490. /* If we have a /RESET GPIO we'll already be reset */
  491. if (!arizona->pdata.reset) {
  492. regcache_mark_dirty(arizona->regmap);
  493. ret = regmap_write(arizona->regmap, ARIZONA_SOFTWARE_RESET, 0);
  494. if (ret != 0) {
  495. dev_err(dev, "Failed to reset device: %d\n", ret);
  496. goto err_reset;
  497. }
  498. msleep(1);
  499. ret = regcache_sync(arizona->regmap);
  500. if (ret != 0) {
  501. dev_err(dev, "Failed to sync device: %d\n", ret);
  502. goto err_reset;
  503. }
  504. }
  505. switch (arizona->type) {
  506. case WM5102:
  507. ret = regmap_read(arizona->regmap, 0x19, &val);
  508. if (ret != 0)
  509. dev_err(dev,
  510. "Failed to check write sequencer state: %d\n",
  511. ret);
  512. else if (val & 0x01)
  513. break;
  514. /* Fall through */
  515. default:
  516. ret = arizona_wait_for_boot(arizona);
  517. if (ret != 0) {
  518. dev_err(arizona->dev,
  519. "Device failed initial boot: %d\n", ret);
  520. goto err_reset;
  521. }
  522. break;
  523. }
  524. if (apply_patch) {
  525. ret = apply_patch(arizona);
  526. if (ret != 0) {
  527. dev_err(arizona->dev, "Failed to apply patch: %d\n",
  528. ret);
  529. goto err_reset;
  530. }
  531. switch (arizona->type) {
  532. case WM5102:
  533. ret = arizona_apply_hardware_patch(arizona);
  534. if (ret != 0) {
  535. dev_err(arizona->dev,
  536. "Failed to apply hardware patch: %d\n",
  537. ret);
  538. goto err_reset;
  539. }
  540. break;
  541. default:
  542. break;
  543. }
  544. }
  545. for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
  546. if (!arizona->pdata.gpio_defaults[i])
  547. continue;
  548. regmap_write(arizona->regmap, ARIZONA_GPIO1_CTRL + i,
  549. arizona->pdata.gpio_defaults[i]);
  550. }
  551. pm_runtime_set_autosuspend_delay(arizona->dev, 100);
  552. pm_runtime_use_autosuspend(arizona->dev);
  553. pm_runtime_enable(arizona->dev);
  554. /* Chip default */
  555. if (!arizona->pdata.clk32k_src)
  556. arizona->pdata.clk32k_src = ARIZONA_32KZ_MCLK2;
  557. switch (arizona->pdata.clk32k_src) {
  558. case ARIZONA_32KZ_MCLK1:
  559. case ARIZONA_32KZ_MCLK2:
  560. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  561. ARIZONA_CLK_32K_SRC_MASK,
  562. arizona->pdata.clk32k_src - 1);
  563. arizona_clk32k_enable(arizona);
  564. break;
  565. case ARIZONA_32KZ_NONE:
  566. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  567. ARIZONA_CLK_32K_SRC_MASK, 2);
  568. break;
  569. default:
  570. dev_err(arizona->dev, "Invalid 32kHz clock source: %d\n",
  571. arizona->pdata.clk32k_src);
  572. ret = -EINVAL;
  573. goto err_reset;
  574. }
  575. for (i = 0; i < ARIZONA_MAX_MICBIAS; i++) {
  576. if (!arizona->pdata.micbias[i].mV &&
  577. !arizona->pdata.micbias[i].bypass)
  578. continue;
  579. /* Apply default for bypass mode */
  580. if (!arizona->pdata.micbias[i].mV)
  581. arizona->pdata.micbias[i].mV = 2800;
  582. val = (arizona->pdata.micbias[i].mV - 1500) / 100;
  583. val <<= ARIZONA_MICB1_LVL_SHIFT;
  584. if (arizona->pdata.micbias[i].ext_cap)
  585. val |= ARIZONA_MICB1_EXT_CAP;
  586. if (arizona->pdata.micbias[i].discharge)
  587. val |= ARIZONA_MICB1_DISCH;
  588. if (arizona->pdata.micbias[i].fast_start)
  589. val |= ARIZONA_MICB1_RATE;
  590. if (arizona->pdata.micbias[i].bypass)
  591. val |= ARIZONA_MICB1_BYPASS;
  592. regmap_update_bits(arizona->regmap,
  593. ARIZONA_MIC_BIAS_CTRL_1 + i,
  594. ARIZONA_MICB1_LVL_MASK |
  595. ARIZONA_MICB1_DISCH |
  596. ARIZONA_MICB1_BYPASS |
  597. ARIZONA_MICB1_RATE, val);
  598. }
  599. for (i = 0; i < ARIZONA_MAX_INPUT; i++) {
  600. /* Default for both is 0 so noop with defaults */
  601. val = arizona->pdata.dmic_ref[i]
  602. << ARIZONA_IN1_DMIC_SUP_SHIFT;
  603. val |= arizona->pdata.inmode[i] << ARIZONA_IN1_MODE_SHIFT;
  604. regmap_update_bits(arizona->regmap,
  605. ARIZONA_IN1L_CONTROL + (i * 8),
  606. ARIZONA_IN1_DMIC_SUP_MASK |
  607. ARIZONA_IN1_MODE_MASK, val);
  608. }
  609. for (i = 0; i < ARIZONA_MAX_OUTPUT; i++) {
  610. /* Default is 0 so noop with defaults */
  611. if (arizona->pdata.out_mono[i])
  612. val = ARIZONA_OUT1_MONO;
  613. else
  614. val = 0;
  615. regmap_update_bits(arizona->regmap,
  616. ARIZONA_OUTPUT_PATH_CONFIG_1L + (i * 8),
  617. ARIZONA_OUT1_MONO, val);
  618. }
  619. for (i = 0; i < ARIZONA_MAX_PDM_SPK; i++) {
  620. if (arizona->pdata.spk_mute[i])
  621. regmap_update_bits(arizona->regmap,
  622. ARIZONA_PDM_SPK1_CTRL_1 + (i * 2),
  623. ARIZONA_SPK1_MUTE_ENDIAN_MASK |
  624. ARIZONA_SPK1_MUTE_SEQ1_MASK,
  625. arizona->pdata.spk_mute[i]);
  626. if (arizona->pdata.spk_fmt[i])
  627. regmap_update_bits(arizona->regmap,
  628. ARIZONA_PDM_SPK1_CTRL_2 + (i * 2),
  629. ARIZONA_SPK1_FMT_MASK,
  630. arizona->pdata.spk_fmt[i]);
  631. }
  632. /* Set up for interrupts */
  633. ret = arizona_irq_init(arizona);
  634. if (ret != 0)
  635. goto err_reset;
  636. arizona_request_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, "CLKGEN error",
  637. arizona_clkgen_err, arizona);
  638. arizona_request_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, "Overclocked",
  639. arizona_overclocked, arizona);
  640. arizona_request_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, "Underclocked",
  641. arizona_underclocked, arizona);
  642. switch (arizona->type) {
  643. case WM5102:
  644. ret = mfd_add_devices(arizona->dev, -1, wm5102_devs,
  645. ARRAY_SIZE(wm5102_devs), NULL, 0, NULL);
  646. break;
  647. case WM5110:
  648. ret = mfd_add_devices(arizona->dev, -1, wm5110_devs,
  649. ARRAY_SIZE(wm5110_devs), NULL, 0, NULL);
  650. break;
  651. }
  652. if (ret != 0) {
  653. dev_err(arizona->dev, "Failed to add subdevices: %d\n", ret);
  654. goto err_irq;
  655. }
  656. #ifdef CONFIG_PM_RUNTIME
  657. regulator_disable(arizona->dcvdd);
  658. #endif
  659. return 0;
  660. err_irq:
  661. arizona_irq_exit(arizona);
  662. err_reset:
  663. if (arizona->pdata.reset) {
  664. gpio_set_value_cansleep(arizona->pdata.reset, 0);
  665. gpio_free(arizona->pdata.reset);
  666. }
  667. regulator_disable(arizona->dcvdd);
  668. err_enable:
  669. regulator_bulk_disable(arizona->num_core_supplies,
  670. arizona->core_supplies);
  671. err_early:
  672. mfd_remove_devices(dev);
  673. return ret;
  674. }
  675. EXPORT_SYMBOL_GPL(arizona_dev_init);
  676. int arizona_dev_exit(struct arizona *arizona)
  677. {
  678. mfd_remove_devices(arizona->dev);
  679. arizona_free_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, arizona);
  680. arizona_free_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, arizona);
  681. arizona_free_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, arizona);
  682. pm_runtime_disable(arizona->dev);
  683. arizona_irq_exit(arizona);
  684. return 0;
  685. }
  686. EXPORT_SYMBOL_GPL(arizona_dev_exit);