fimc-lite.c 43 KB

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  1. /*
  2. * Samsung EXYNOS FIMC-LITE (camera host interface) driver
  3. *
  4. * Copyright (C) 2012 Samsung Electronics Co., Ltd.
  5. * Sylwester Nawrocki <s.nawrocki@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
  12. #include <linux/bug.h>
  13. #include <linux/clk.h>
  14. #include <linux/device.h>
  15. #include <linux/errno.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/kernel.h>
  18. #include <linux/list.h>
  19. #include <linux/module.h>
  20. #include <linux/of.h>
  21. #include <linux/types.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/pm_runtime.h>
  24. #include <linux/slab.h>
  25. #include <linux/videodev2.h>
  26. #include <media/v4l2-device.h>
  27. #include <media/v4l2-ioctl.h>
  28. #include <media/v4l2-mem2mem.h>
  29. #include <media/videobuf2-core.h>
  30. #include <media/videobuf2-dma-contig.h>
  31. #include <media/s5p_fimc.h>
  32. #include "fimc-core.h"
  33. #include "fimc-lite.h"
  34. #include "fimc-lite-reg.h"
  35. static int debug;
  36. module_param(debug, int, 0644);
  37. static const struct fimc_fmt fimc_lite_formats[] = {
  38. {
  39. .name = "YUV 4:2:2 packed, YCbYCr",
  40. .fourcc = V4L2_PIX_FMT_YUYV,
  41. .depth = { 16 },
  42. .color = FIMC_FMT_YCBYCR422,
  43. .memplanes = 1,
  44. .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
  45. .flags = FMT_FLAGS_YUV,
  46. }, {
  47. .name = "YUV 4:2:2 packed, CbYCrY",
  48. .fourcc = V4L2_PIX_FMT_UYVY,
  49. .depth = { 16 },
  50. .color = FIMC_FMT_CBYCRY422,
  51. .memplanes = 1,
  52. .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8,
  53. .flags = FMT_FLAGS_YUV,
  54. }, {
  55. .name = "YUV 4:2:2 packed, CrYCbY",
  56. .fourcc = V4L2_PIX_FMT_VYUY,
  57. .depth = { 16 },
  58. .color = FIMC_FMT_CRYCBY422,
  59. .memplanes = 1,
  60. .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8,
  61. .flags = FMT_FLAGS_YUV,
  62. }, {
  63. .name = "YUV 4:2:2 packed, YCrYCb",
  64. .fourcc = V4L2_PIX_FMT_YVYU,
  65. .depth = { 16 },
  66. .color = FIMC_FMT_YCRYCB422,
  67. .memplanes = 1,
  68. .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8,
  69. .flags = FMT_FLAGS_YUV,
  70. }, {
  71. .name = "RAW8 (GRBG)",
  72. .fourcc = V4L2_PIX_FMT_SGRBG8,
  73. .depth = { 8 },
  74. .color = FIMC_FMT_RAW8,
  75. .memplanes = 1,
  76. .mbus_code = V4L2_MBUS_FMT_SGRBG8_1X8,
  77. .flags = FMT_FLAGS_RAW_BAYER,
  78. }, {
  79. .name = "RAW10 (GRBG)",
  80. .fourcc = V4L2_PIX_FMT_SGRBG10,
  81. .depth = { 10 },
  82. .color = FIMC_FMT_RAW10,
  83. .memplanes = 1,
  84. .mbus_code = V4L2_MBUS_FMT_SGRBG10_1X10,
  85. .flags = FMT_FLAGS_RAW_BAYER,
  86. }, {
  87. .name = "RAW12 (GRBG)",
  88. .fourcc = V4L2_PIX_FMT_SGRBG12,
  89. .depth = { 12 },
  90. .color = FIMC_FMT_RAW12,
  91. .memplanes = 1,
  92. .mbus_code = V4L2_MBUS_FMT_SGRBG12_1X12,
  93. .flags = FMT_FLAGS_RAW_BAYER,
  94. },
  95. };
  96. /**
  97. * fimc_lite_find_format - lookup fimc color format by fourcc or media bus code
  98. * @pixelformat: fourcc to match, ignored if null
  99. * @mbus_code: media bus code to match, ignored if null
  100. * @mask: the color format flags to match
  101. * @index: index to the fimc_lite_formats array, ignored if negative
  102. */
  103. static const struct fimc_fmt *fimc_lite_find_format(const u32 *pixelformat,
  104. const u32 *mbus_code, unsigned int mask, int index)
  105. {
  106. const struct fimc_fmt *fmt, *def_fmt = NULL;
  107. unsigned int i;
  108. int id = 0;
  109. if (index >= (int)ARRAY_SIZE(fimc_lite_formats))
  110. return NULL;
  111. for (i = 0; i < ARRAY_SIZE(fimc_lite_formats); ++i) {
  112. fmt = &fimc_lite_formats[i];
  113. if (mask && !(fmt->flags & mask))
  114. continue;
  115. if (pixelformat && fmt->fourcc == *pixelformat)
  116. return fmt;
  117. if (mbus_code && fmt->mbus_code == *mbus_code)
  118. return fmt;
  119. if (index == id)
  120. def_fmt = fmt;
  121. id++;
  122. }
  123. return def_fmt;
  124. }
  125. /* Called with the media graph mutex held or @me stream_count > 0. */
  126. static struct v4l2_subdev *__find_remote_sensor(struct media_entity *me)
  127. {
  128. struct media_pad *pad = &me->pads[0];
  129. struct v4l2_subdev *sd;
  130. while (pad->flags & MEDIA_PAD_FL_SINK) {
  131. /* source pad */
  132. pad = media_entity_remote_source(pad);
  133. if (pad == NULL ||
  134. media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
  135. break;
  136. sd = media_entity_to_v4l2_subdev(pad->entity);
  137. if (sd->grp_id == GRP_ID_FIMC_IS_SENSOR ||
  138. sd->grp_id == GRP_ID_SENSOR)
  139. return sd;
  140. /* sink pad */
  141. pad = &sd->entity.pads[0];
  142. }
  143. return NULL;
  144. }
  145. static int fimc_lite_hw_init(struct fimc_lite *fimc, bool isp_output)
  146. {
  147. struct fimc_source_info *si;
  148. unsigned long flags;
  149. if (fimc->sensor == NULL)
  150. return -ENXIO;
  151. if (fimc->inp_frame.fmt == NULL || fimc->out_frame.fmt == NULL)
  152. return -EINVAL;
  153. /* Get sensor configuration data from the sensor subdev */
  154. si = v4l2_get_subdev_hostdata(fimc->sensor);
  155. if (!si)
  156. return -EINVAL;
  157. spin_lock_irqsave(&fimc->slock, flags);
  158. flite_hw_set_camera_bus(fimc, si);
  159. flite_hw_set_source_format(fimc, &fimc->inp_frame);
  160. flite_hw_set_window_offset(fimc, &fimc->inp_frame);
  161. flite_hw_set_output_dma(fimc, &fimc->out_frame, !isp_output);
  162. flite_hw_set_interrupt_mask(fimc);
  163. flite_hw_set_test_pattern(fimc, fimc->test_pattern->val);
  164. if (debug > 0)
  165. flite_hw_dump_regs(fimc, __func__);
  166. spin_unlock_irqrestore(&fimc->slock, flags);
  167. return 0;
  168. }
  169. /*
  170. * Reinitialize the driver so it is ready to start the streaming again.
  171. * Set fimc->state to indicate stream off and the hardware shut down state.
  172. * If not suspending (@suspend is false), return any buffers to videobuf2.
  173. * Otherwise put any owned buffers onto the pending buffers queue, so they
  174. * can be re-spun when the device is being resumed. Also perform FIMC
  175. * software reset and disable streaming on the whole pipeline if required.
  176. */
  177. static int fimc_lite_reinit(struct fimc_lite *fimc, bool suspend)
  178. {
  179. struct flite_buffer *buf;
  180. unsigned long flags;
  181. bool streaming;
  182. spin_lock_irqsave(&fimc->slock, flags);
  183. streaming = fimc->state & (1 << ST_SENSOR_STREAM);
  184. fimc->state &= ~(1 << ST_FLITE_RUN | 1 << ST_FLITE_OFF |
  185. 1 << ST_FLITE_STREAM | 1 << ST_SENSOR_STREAM);
  186. if (suspend)
  187. fimc->state |= (1 << ST_FLITE_SUSPENDED);
  188. else
  189. fimc->state &= ~(1 << ST_FLITE_PENDING |
  190. 1 << ST_FLITE_SUSPENDED);
  191. /* Release unused buffers */
  192. while (!suspend && !list_empty(&fimc->pending_buf_q)) {
  193. buf = fimc_lite_pending_queue_pop(fimc);
  194. vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
  195. }
  196. /* If suspending put unused buffers onto pending queue */
  197. while (!list_empty(&fimc->active_buf_q)) {
  198. buf = fimc_lite_active_queue_pop(fimc);
  199. if (suspend)
  200. fimc_lite_pending_queue_add(fimc, buf);
  201. else
  202. vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
  203. }
  204. spin_unlock_irqrestore(&fimc->slock, flags);
  205. flite_hw_reset(fimc);
  206. if (!streaming)
  207. return 0;
  208. return fimc_pipeline_call(fimc, set_stream, &fimc->pipeline, 0);
  209. }
  210. static int fimc_lite_stop_capture(struct fimc_lite *fimc, bool suspend)
  211. {
  212. unsigned long flags;
  213. if (!fimc_lite_active(fimc))
  214. return 0;
  215. spin_lock_irqsave(&fimc->slock, flags);
  216. set_bit(ST_FLITE_OFF, &fimc->state);
  217. flite_hw_capture_stop(fimc);
  218. spin_unlock_irqrestore(&fimc->slock, flags);
  219. wait_event_timeout(fimc->irq_queue,
  220. !test_bit(ST_FLITE_OFF, &fimc->state),
  221. (2*HZ/10)); /* 200 ms */
  222. return fimc_lite_reinit(fimc, suspend);
  223. }
  224. /* Must be called with fimc.slock spinlock held. */
  225. static void fimc_lite_config_update(struct fimc_lite *fimc)
  226. {
  227. flite_hw_set_window_offset(fimc, &fimc->inp_frame);
  228. flite_hw_set_dma_window(fimc, &fimc->out_frame);
  229. flite_hw_set_test_pattern(fimc, fimc->test_pattern->val);
  230. clear_bit(ST_FLITE_CONFIG, &fimc->state);
  231. }
  232. static irqreturn_t flite_irq_handler(int irq, void *priv)
  233. {
  234. struct fimc_lite *fimc = priv;
  235. struct flite_buffer *vbuf;
  236. unsigned long flags;
  237. struct timeval *tv;
  238. struct timespec ts;
  239. u32 intsrc;
  240. spin_lock_irqsave(&fimc->slock, flags);
  241. intsrc = flite_hw_get_interrupt_source(fimc);
  242. flite_hw_clear_pending_irq(fimc);
  243. if (test_and_clear_bit(ST_FLITE_OFF, &fimc->state)) {
  244. wake_up(&fimc->irq_queue);
  245. goto done;
  246. }
  247. if (intsrc & FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW) {
  248. clear_bit(ST_FLITE_RUN, &fimc->state);
  249. fimc->events.data_overflow++;
  250. }
  251. if (intsrc & FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND) {
  252. flite_hw_clear_last_capture_end(fimc);
  253. clear_bit(ST_FLITE_STREAM, &fimc->state);
  254. wake_up(&fimc->irq_queue);
  255. }
  256. if (atomic_read(&fimc->out_path) != FIMC_IO_DMA)
  257. goto done;
  258. if ((intsrc & FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART) &&
  259. test_bit(ST_FLITE_RUN, &fimc->state) &&
  260. !list_empty(&fimc->active_buf_q) &&
  261. !list_empty(&fimc->pending_buf_q)) {
  262. vbuf = fimc_lite_active_queue_pop(fimc);
  263. ktime_get_ts(&ts);
  264. tv = &vbuf->vb.v4l2_buf.timestamp;
  265. tv->tv_sec = ts.tv_sec;
  266. tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
  267. vbuf->vb.v4l2_buf.sequence = fimc->frame_count++;
  268. vb2_buffer_done(&vbuf->vb, VB2_BUF_STATE_DONE);
  269. vbuf = fimc_lite_pending_queue_pop(fimc);
  270. flite_hw_set_output_addr(fimc, vbuf->paddr);
  271. fimc_lite_active_queue_add(fimc, vbuf);
  272. }
  273. if (test_bit(ST_FLITE_CONFIG, &fimc->state))
  274. fimc_lite_config_update(fimc);
  275. if (list_empty(&fimc->pending_buf_q)) {
  276. flite_hw_capture_stop(fimc);
  277. clear_bit(ST_FLITE_STREAM, &fimc->state);
  278. }
  279. done:
  280. set_bit(ST_FLITE_RUN, &fimc->state);
  281. spin_unlock_irqrestore(&fimc->slock, flags);
  282. return IRQ_HANDLED;
  283. }
  284. static int start_streaming(struct vb2_queue *q, unsigned int count)
  285. {
  286. struct fimc_lite *fimc = q->drv_priv;
  287. int ret;
  288. fimc->frame_count = 0;
  289. ret = fimc_lite_hw_init(fimc, false);
  290. if (ret) {
  291. fimc_lite_reinit(fimc, false);
  292. return ret;
  293. }
  294. set_bit(ST_FLITE_PENDING, &fimc->state);
  295. if (!list_empty(&fimc->active_buf_q) &&
  296. !test_and_set_bit(ST_FLITE_STREAM, &fimc->state)) {
  297. flite_hw_capture_start(fimc);
  298. if (!test_and_set_bit(ST_SENSOR_STREAM, &fimc->state))
  299. fimc_pipeline_call(fimc, set_stream,
  300. &fimc->pipeline, 1);
  301. }
  302. if (debug > 0)
  303. flite_hw_dump_regs(fimc, __func__);
  304. return 0;
  305. }
  306. static int stop_streaming(struct vb2_queue *q)
  307. {
  308. struct fimc_lite *fimc = q->drv_priv;
  309. if (!fimc_lite_active(fimc))
  310. return -EINVAL;
  311. return fimc_lite_stop_capture(fimc, false);
  312. }
  313. static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *pfmt,
  314. unsigned int *num_buffers, unsigned int *num_planes,
  315. unsigned int sizes[], void *allocators[])
  316. {
  317. const struct v4l2_pix_format_mplane *pixm = NULL;
  318. struct fimc_lite *fimc = vq->drv_priv;
  319. struct flite_frame *frame = &fimc->out_frame;
  320. const struct fimc_fmt *fmt = frame->fmt;
  321. unsigned long wh;
  322. int i;
  323. if (pfmt) {
  324. pixm = &pfmt->fmt.pix_mp;
  325. fmt = fimc_lite_find_format(&pixm->pixelformat, NULL, 0, -1);
  326. wh = pixm->width * pixm->height;
  327. } else {
  328. wh = frame->f_width * frame->f_height;
  329. }
  330. if (fmt == NULL)
  331. return -EINVAL;
  332. *num_planes = fmt->memplanes;
  333. for (i = 0; i < fmt->memplanes; i++) {
  334. unsigned int size = (wh * fmt->depth[i]) / 8;
  335. if (pixm)
  336. sizes[i] = max(size, pixm->plane_fmt[i].sizeimage);
  337. else
  338. sizes[i] = size;
  339. allocators[i] = fimc->alloc_ctx;
  340. }
  341. return 0;
  342. }
  343. static int buffer_prepare(struct vb2_buffer *vb)
  344. {
  345. struct vb2_queue *vq = vb->vb2_queue;
  346. struct fimc_lite *fimc = vq->drv_priv;
  347. int i;
  348. if (fimc->out_frame.fmt == NULL)
  349. return -EINVAL;
  350. for (i = 0; i < fimc->out_frame.fmt->memplanes; i++) {
  351. unsigned long size = fimc->payload[i];
  352. if (vb2_plane_size(vb, i) < size) {
  353. v4l2_err(&fimc->vfd,
  354. "User buffer too small (%ld < %ld)\n",
  355. vb2_plane_size(vb, i), size);
  356. return -EINVAL;
  357. }
  358. vb2_set_plane_payload(vb, i, size);
  359. }
  360. return 0;
  361. }
  362. static void buffer_queue(struct vb2_buffer *vb)
  363. {
  364. struct flite_buffer *buf
  365. = container_of(vb, struct flite_buffer, vb);
  366. struct fimc_lite *fimc = vb2_get_drv_priv(vb->vb2_queue);
  367. unsigned long flags;
  368. spin_lock_irqsave(&fimc->slock, flags);
  369. buf->paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
  370. if (!test_bit(ST_FLITE_SUSPENDED, &fimc->state) &&
  371. !test_bit(ST_FLITE_STREAM, &fimc->state) &&
  372. list_empty(&fimc->active_buf_q)) {
  373. flite_hw_set_output_addr(fimc, buf->paddr);
  374. fimc_lite_active_queue_add(fimc, buf);
  375. } else {
  376. fimc_lite_pending_queue_add(fimc, buf);
  377. }
  378. if (vb2_is_streaming(&fimc->vb_queue) &&
  379. !list_empty(&fimc->pending_buf_q) &&
  380. !test_and_set_bit(ST_FLITE_STREAM, &fimc->state)) {
  381. flite_hw_capture_start(fimc);
  382. spin_unlock_irqrestore(&fimc->slock, flags);
  383. if (!test_and_set_bit(ST_SENSOR_STREAM, &fimc->state))
  384. fimc_pipeline_call(fimc, set_stream,
  385. &fimc->pipeline, 1);
  386. return;
  387. }
  388. spin_unlock_irqrestore(&fimc->slock, flags);
  389. }
  390. static const struct vb2_ops fimc_lite_qops = {
  391. .queue_setup = queue_setup,
  392. .buf_prepare = buffer_prepare,
  393. .buf_queue = buffer_queue,
  394. .wait_prepare = vb2_ops_wait_prepare,
  395. .wait_finish = vb2_ops_wait_finish,
  396. .start_streaming = start_streaming,
  397. .stop_streaming = stop_streaming,
  398. };
  399. static void fimc_lite_clear_event_counters(struct fimc_lite *fimc)
  400. {
  401. unsigned long flags;
  402. spin_lock_irqsave(&fimc->slock, flags);
  403. memset(&fimc->events, 0, sizeof(fimc->events));
  404. spin_unlock_irqrestore(&fimc->slock, flags);
  405. }
  406. static int fimc_lite_open(struct file *file)
  407. {
  408. struct fimc_lite *fimc = video_drvdata(file);
  409. struct media_entity *me = &fimc->vfd.entity;
  410. int ret;
  411. mutex_lock(&me->parent->graph_mutex);
  412. mutex_lock(&fimc->lock);
  413. if (atomic_read(&fimc->out_path) != FIMC_IO_DMA) {
  414. ret = -EBUSY;
  415. goto unlock;
  416. }
  417. set_bit(ST_FLITE_IN_USE, &fimc->state);
  418. ret = pm_runtime_get_sync(&fimc->pdev->dev);
  419. if (ret < 0)
  420. goto unlock;
  421. ret = v4l2_fh_open(file);
  422. if (ret < 0)
  423. goto err_pm;
  424. if (!v4l2_fh_is_singular_file(file) ||
  425. atomic_read(&fimc->out_path) != FIMC_IO_DMA)
  426. goto unlock;
  427. ret = fimc_pipeline_call(fimc, open, &fimc->pipeline,
  428. me, true);
  429. if (!ret) {
  430. fimc_lite_clear_event_counters(fimc);
  431. fimc->ref_count++;
  432. goto unlock;
  433. }
  434. v4l2_fh_release(file);
  435. err_pm:
  436. pm_runtime_put_sync(&fimc->pdev->dev);
  437. clear_bit(ST_FLITE_IN_USE, &fimc->state);
  438. unlock:
  439. mutex_unlock(&fimc->lock);
  440. mutex_unlock(&me->parent->graph_mutex);
  441. return ret;
  442. }
  443. static int fimc_lite_release(struct file *file)
  444. {
  445. struct fimc_lite *fimc = video_drvdata(file);
  446. mutex_lock(&fimc->lock);
  447. if (v4l2_fh_is_singular_file(file) &&
  448. atomic_read(&fimc->out_path) == FIMC_IO_DMA) {
  449. if (fimc->streaming) {
  450. media_entity_pipeline_stop(&fimc->vfd.entity);
  451. fimc->streaming = false;
  452. }
  453. clear_bit(ST_FLITE_IN_USE, &fimc->state);
  454. fimc_lite_stop_capture(fimc, false);
  455. fimc_pipeline_call(fimc, close, &fimc->pipeline);
  456. fimc->ref_count--;
  457. }
  458. vb2_fop_release(file);
  459. pm_runtime_put(&fimc->pdev->dev);
  460. clear_bit(ST_FLITE_SUSPENDED, &fimc->state);
  461. mutex_unlock(&fimc->lock);
  462. return 0;
  463. }
  464. static const struct v4l2_file_operations fimc_lite_fops = {
  465. .owner = THIS_MODULE,
  466. .open = fimc_lite_open,
  467. .release = fimc_lite_release,
  468. .poll = vb2_fop_poll,
  469. .unlocked_ioctl = video_ioctl2,
  470. .mmap = vb2_fop_mmap,
  471. };
  472. /*
  473. * Format and crop negotiation helpers
  474. */
  475. static const struct fimc_fmt *fimc_lite_try_format(struct fimc_lite *fimc,
  476. u32 *width, u32 *height,
  477. u32 *code, u32 *fourcc, int pad)
  478. {
  479. struct flite_drvdata *dd = fimc->dd;
  480. const struct fimc_fmt *fmt;
  481. unsigned int flags = 0;
  482. if (pad == FLITE_SD_PAD_SINK) {
  483. v4l_bound_align_image(width, 8, dd->max_width,
  484. ffs(dd->out_width_align) - 1,
  485. height, 0, dd->max_height, 0, 0);
  486. } else {
  487. v4l_bound_align_image(width, 8, fimc->inp_frame.rect.width,
  488. ffs(dd->out_width_align) - 1,
  489. height, 0, fimc->inp_frame.rect.height,
  490. 0, 0);
  491. flags = fimc->inp_frame.fmt->flags;
  492. }
  493. fmt = fimc_lite_find_format(fourcc, code, flags, 0);
  494. if (WARN_ON(!fmt))
  495. return NULL;
  496. if (code)
  497. *code = fmt->mbus_code;
  498. if (fourcc)
  499. *fourcc = fmt->fourcc;
  500. v4l2_dbg(1, debug, &fimc->subdev, "code: 0x%x, %dx%d\n",
  501. code ? *code : 0, *width, *height);
  502. return fmt;
  503. }
  504. static void fimc_lite_try_crop(struct fimc_lite *fimc, struct v4l2_rect *r)
  505. {
  506. struct flite_frame *frame = &fimc->inp_frame;
  507. v4l_bound_align_image(&r->width, 0, frame->f_width, 0,
  508. &r->height, 0, frame->f_height, 0, 0);
  509. /* Adjust left/top if cropping rectangle got out of bounds */
  510. r->left = clamp_t(u32, r->left, 0, frame->f_width - r->width);
  511. r->left = round_down(r->left, fimc->dd->win_hor_offs_align);
  512. r->top = clamp_t(u32, r->top, 0, frame->f_height - r->height);
  513. v4l2_dbg(1, debug, &fimc->subdev, "(%d,%d)/%dx%d, sink fmt: %dx%d\n",
  514. r->left, r->top, r->width, r->height,
  515. frame->f_width, frame->f_height);
  516. }
  517. static void fimc_lite_try_compose(struct fimc_lite *fimc, struct v4l2_rect *r)
  518. {
  519. struct flite_frame *frame = &fimc->out_frame;
  520. struct v4l2_rect *crop_rect = &fimc->inp_frame.rect;
  521. /* Scaling is not supported so we enforce compose rectangle size
  522. same as size of the sink crop rectangle. */
  523. r->width = crop_rect->width;
  524. r->height = crop_rect->height;
  525. /* Adjust left/top if the composing rectangle got out of bounds */
  526. r->left = clamp_t(u32, r->left, 0, frame->f_width - r->width);
  527. r->left = round_down(r->left, fimc->dd->out_hor_offs_align);
  528. r->top = clamp_t(u32, r->top, 0, fimc->out_frame.f_height - r->height);
  529. v4l2_dbg(1, debug, &fimc->subdev, "(%d,%d)/%dx%d, source fmt: %dx%d\n",
  530. r->left, r->top, r->width, r->height,
  531. frame->f_width, frame->f_height);
  532. }
  533. /*
  534. * Video node ioctl operations
  535. */
  536. static int fimc_vidioc_querycap_capture(struct file *file, void *priv,
  537. struct v4l2_capability *cap)
  538. {
  539. strlcpy(cap->driver, FIMC_LITE_DRV_NAME, sizeof(cap->driver));
  540. cap->bus_info[0] = 0;
  541. cap->card[0] = 0;
  542. cap->capabilities = V4L2_CAP_STREAMING;
  543. return 0;
  544. }
  545. static int fimc_lite_enum_fmt_mplane(struct file *file, void *priv,
  546. struct v4l2_fmtdesc *f)
  547. {
  548. const struct fimc_fmt *fmt;
  549. if (f->index >= ARRAY_SIZE(fimc_lite_formats))
  550. return -EINVAL;
  551. fmt = &fimc_lite_formats[f->index];
  552. strlcpy(f->description, fmt->name, sizeof(f->description));
  553. f->pixelformat = fmt->fourcc;
  554. return 0;
  555. }
  556. static int fimc_lite_g_fmt_mplane(struct file *file, void *fh,
  557. struct v4l2_format *f)
  558. {
  559. struct fimc_lite *fimc = video_drvdata(file);
  560. struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
  561. struct v4l2_plane_pix_format *plane_fmt = &pixm->plane_fmt[0];
  562. struct flite_frame *frame = &fimc->out_frame;
  563. const struct fimc_fmt *fmt = frame->fmt;
  564. plane_fmt->bytesperline = (frame->f_width * fmt->depth[0]) / 8;
  565. plane_fmt->sizeimage = plane_fmt->bytesperline * frame->f_height;
  566. pixm->num_planes = fmt->memplanes;
  567. pixm->pixelformat = fmt->fourcc;
  568. pixm->width = frame->f_width;
  569. pixm->height = frame->f_height;
  570. pixm->field = V4L2_FIELD_NONE;
  571. pixm->colorspace = V4L2_COLORSPACE_JPEG;
  572. return 0;
  573. }
  574. static int fimc_lite_try_fmt(struct fimc_lite *fimc,
  575. struct v4l2_pix_format_mplane *pixm,
  576. const struct fimc_fmt **ffmt)
  577. {
  578. u32 bpl = pixm->plane_fmt[0].bytesperline;
  579. struct flite_drvdata *dd = fimc->dd;
  580. const struct fimc_fmt *inp_fmt = fimc->inp_frame.fmt;
  581. const struct fimc_fmt *fmt;
  582. if (WARN_ON(inp_fmt == NULL))
  583. return -EINVAL;
  584. /*
  585. * We allow some flexibility only for YUV formats. In case of raw
  586. * raw Bayer the FIMC-LITE's output format must match its camera
  587. * interface input format.
  588. */
  589. if (inp_fmt->flags & FMT_FLAGS_YUV)
  590. fmt = fimc_lite_find_format(&pixm->pixelformat, NULL,
  591. inp_fmt->flags, 0);
  592. else
  593. fmt = inp_fmt;
  594. if (WARN_ON(fmt == NULL))
  595. return -EINVAL;
  596. if (ffmt)
  597. *ffmt = fmt;
  598. v4l_bound_align_image(&pixm->width, 8, dd->max_width,
  599. ffs(dd->out_width_align) - 1,
  600. &pixm->height, 0, dd->max_height, 0, 0);
  601. if ((bpl == 0 || ((bpl * 8) / fmt->depth[0]) < pixm->width))
  602. pixm->plane_fmt[0].bytesperline = (pixm->width *
  603. fmt->depth[0]) / 8;
  604. if (pixm->plane_fmt[0].sizeimage == 0)
  605. pixm->plane_fmt[0].sizeimage = (pixm->width * pixm->height *
  606. fmt->depth[0]) / 8;
  607. pixm->num_planes = fmt->memplanes;
  608. pixm->pixelformat = fmt->fourcc;
  609. pixm->colorspace = V4L2_COLORSPACE_JPEG;
  610. pixm->field = V4L2_FIELD_NONE;
  611. return 0;
  612. }
  613. static int fimc_lite_try_fmt_mplane(struct file *file, void *fh,
  614. struct v4l2_format *f)
  615. {
  616. struct fimc_lite *fimc = video_drvdata(file);
  617. return fimc_lite_try_fmt(fimc, &f->fmt.pix_mp, NULL);
  618. }
  619. static int fimc_lite_s_fmt_mplane(struct file *file, void *priv,
  620. struct v4l2_format *f)
  621. {
  622. struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
  623. struct fimc_lite *fimc = video_drvdata(file);
  624. struct flite_frame *frame = &fimc->out_frame;
  625. const struct fimc_fmt *fmt = NULL;
  626. int ret;
  627. if (vb2_is_busy(&fimc->vb_queue))
  628. return -EBUSY;
  629. ret = fimc_lite_try_fmt(fimc, &f->fmt.pix_mp, &fmt);
  630. if (ret < 0)
  631. return ret;
  632. frame->fmt = fmt;
  633. fimc->payload[0] = max((pixm->width * pixm->height * fmt->depth[0]) / 8,
  634. pixm->plane_fmt[0].sizeimage);
  635. frame->f_width = pixm->width;
  636. frame->f_height = pixm->height;
  637. return 0;
  638. }
  639. static int fimc_pipeline_validate(struct fimc_lite *fimc)
  640. {
  641. struct v4l2_subdev *sd = &fimc->subdev;
  642. struct v4l2_subdev_format sink_fmt, src_fmt;
  643. struct media_pad *pad;
  644. int ret;
  645. while (1) {
  646. /* Retrieve format at the sink pad */
  647. pad = &sd->entity.pads[0];
  648. if (!(pad->flags & MEDIA_PAD_FL_SINK))
  649. break;
  650. /* Don't call FIMC subdev operation to avoid nested locking */
  651. if (sd == &fimc->subdev) {
  652. struct flite_frame *ff = &fimc->out_frame;
  653. sink_fmt.format.width = ff->f_width;
  654. sink_fmt.format.height = ff->f_height;
  655. sink_fmt.format.code = fimc->inp_frame.fmt->mbus_code;
  656. } else {
  657. sink_fmt.pad = pad->index;
  658. sink_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
  659. ret = v4l2_subdev_call(sd, pad, get_fmt, NULL,
  660. &sink_fmt);
  661. if (ret < 0 && ret != -ENOIOCTLCMD)
  662. return -EPIPE;
  663. }
  664. /* Retrieve format at the source pad */
  665. pad = media_entity_remote_source(pad);
  666. if (pad == NULL ||
  667. media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
  668. break;
  669. sd = media_entity_to_v4l2_subdev(pad->entity);
  670. src_fmt.pad = pad->index;
  671. src_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
  672. ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &src_fmt);
  673. if (ret < 0 && ret != -ENOIOCTLCMD)
  674. return -EPIPE;
  675. if (src_fmt.format.width != sink_fmt.format.width ||
  676. src_fmt.format.height != sink_fmt.format.height ||
  677. src_fmt.format.code != sink_fmt.format.code)
  678. return -EPIPE;
  679. }
  680. return 0;
  681. }
  682. static int fimc_lite_streamon(struct file *file, void *priv,
  683. enum v4l2_buf_type type)
  684. {
  685. struct fimc_lite *fimc = video_drvdata(file);
  686. struct media_entity *entity = &fimc->vfd.entity;
  687. struct fimc_pipeline *p = &fimc->pipeline;
  688. int ret;
  689. if (fimc_lite_active(fimc))
  690. return -EBUSY;
  691. ret = media_entity_pipeline_start(entity, p->m_pipeline);
  692. if (ret < 0)
  693. return ret;
  694. ret = fimc_pipeline_validate(fimc);
  695. if (ret < 0)
  696. goto err_p_stop;
  697. fimc->sensor = __find_remote_sensor(&fimc->subdev.entity);
  698. ret = vb2_ioctl_streamon(file, priv, type);
  699. if (!ret) {
  700. fimc->streaming = true;
  701. return ret;
  702. }
  703. err_p_stop:
  704. media_entity_pipeline_stop(entity);
  705. return 0;
  706. }
  707. static int fimc_lite_streamoff(struct file *file, void *priv,
  708. enum v4l2_buf_type type)
  709. {
  710. struct fimc_lite *fimc = video_drvdata(file);
  711. int ret;
  712. ret = vb2_ioctl_streamoff(file, priv, type);
  713. if (ret < 0)
  714. return ret;
  715. media_entity_pipeline_stop(&fimc->vfd.entity);
  716. fimc->streaming = false;
  717. return 0;
  718. }
  719. static int fimc_lite_reqbufs(struct file *file, void *priv,
  720. struct v4l2_requestbuffers *reqbufs)
  721. {
  722. struct fimc_lite *fimc = video_drvdata(file);
  723. int ret;
  724. reqbufs->count = max_t(u32, FLITE_REQ_BUFS_MIN, reqbufs->count);
  725. ret = vb2_ioctl_reqbufs(file, priv, reqbufs);
  726. if (!ret)
  727. fimc->reqbufs_count = reqbufs->count;
  728. return ret;
  729. }
  730. /* Return 1 if rectangle a is enclosed in rectangle b, or 0 otherwise. */
  731. static int enclosed_rectangle(struct v4l2_rect *a, struct v4l2_rect *b)
  732. {
  733. if (a->left < b->left || a->top < b->top)
  734. return 0;
  735. if (a->left + a->width > b->left + b->width)
  736. return 0;
  737. if (a->top + a->height > b->top + b->height)
  738. return 0;
  739. return 1;
  740. }
  741. static int fimc_lite_g_selection(struct file *file, void *fh,
  742. struct v4l2_selection *sel)
  743. {
  744. struct fimc_lite *fimc = video_drvdata(file);
  745. struct flite_frame *f = &fimc->out_frame;
  746. if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
  747. return -EINVAL;
  748. switch (sel->target) {
  749. case V4L2_SEL_TGT_COMPOSE_BOUNDS:
  750. case V4L2_SEL_TGT_COMPOSE_DEFAULT:
  751. sel->r.left = 0;
  752. sel->r.top = 0;
  753. sel->r.width = f->f_width;
  754. sel->r.height = f->f_height;
  755. return 0;
  756. case V4L2_SEL_TGT_COMPOSE:
  757. sel->r = f->rect;
  758. return 0;
  759. }
  760. return -EINVAL;
  761. }
  762. static int fimc_lite_s_selection(struct file *file, void *fh,
  763. struct v4l2_selection *sel)
  764. {
  765. struct fimc_lite *fimc = video_drvdata(file);
  766. struct flite_frame *f = &fimc->out_frame;
  767. struct v4l2_rect rect = sel->r;
  768. unsigned long flags;
  769. if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE ||
  770. sel->target != V4L2_SEL_TGT_COMPOSE)
  771. return -EINVAL;
  772. fimc_lite_try_compose(fimc, &rect);
  773. if ((sel->flags & V4L2_SEL_FLAG_LE) &&
  774. !enclosed_rectangle(&rect, &sel->r))
  775. return -ERANGE;
  776. if ((sel->flags & V4L2_SEL_FLAG_GE) &&
  777. !enclosed_rectangle(&sel->r, &rect))
  778. return -ERANGE;
  779. sel->r = rect;
  780. spin_lock_irqsave(&fimc->slock, flags);
  781. f->rect = rect;
  782. set_bit(ST_FLITE_CONFIG, &fimc->state);
  783. spin_unlock_irqrestore(&fimc->slock, flags);
  784. return 0;
  785. }
  786. static const struct v4l2_ioctl_ops fimc_lite_ioctl_ops = {
  787. .vidioc_querycap = fimc_vidioc_querycap_capture,
  788. .vidioc_enum_fmt_vid_cap_mplane = fimc_lite_enum_fmt_mplane,
  789. .vidioc_try_fmt_vid_cap_mplane = fimc_lite_try_fmt_mplane,
  790. .vidioc_s_fmt_vid_cap_mplane = fimc_lite_s_fmt_mplane,
  791. .vidioc_g_fmt_vid_cap_mplane = fimc_lite_g_fmt_mplane,
  792. .vidioc_g_selection = fimc_lite_g_selection,
  793. .vidioc_s_selection = fimc_lite_s_selection,
  794. .vidioc_reqbufs = fimc_lite_reqbufs,
  795. .vidioc_querybuf = vb2_ioctl_querybuf,
  796. .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
  797. .vidioc_create_bufs = vb2_ioctl_create_bufs,
  798. .vidioc_qbuf = vb2_ioctl_qbuf,
  799. .vidioc_dqbuf = vb2_ioctl_dqbuf,
  800. .vidioc_streamon = fimc_lite_streamon,
  801. .vidioc_streamoff = fimc_lite_streamoff,
  802. };
  803. /* Capture subdev media entity operations */
  804. static int fimc_lite_link_setup(struct media_entity *entity,
  805. const struct media_pad *local,
  806. const struct media_pad *remote, u32 flags)
  807. {
  808. struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
  809. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  810. unsigned int remote_ent_type = media_entity_type(remote->entity);
  811. int ret = 0;
  812. if (WARN_ON(fimc == NULL))
  813. return 0;
  814. v4l2_dbg(1, debug, sd, "%s: %s --> %s, flags: 0x%x. source_id: 0x%x\n",
  815. __func__, remote->entity->name, local->entity->name,
  816. flags, fimc->source_subdev_grp_id);
  817. mutex_lock(&fimc->lock);
  818. switch (local->index) {
  819. case FLITE_SD_PAD_SINK:
  820. if (remote_ent_type != MEDIA_ENT_T_V4L2_SUBDEV) {
  821. ret = -EINVAL;
  822. break;
  823. }
  824. if (flags & MEDIA_LNK_FL_ENABLED) {
  825. if (fimc->source_subdev_grp_id == 0)
  826. fimc->source_subdev_grp_id = sd->grp_id;
  827. else
  828. ret = -EBUSY;
  829. } else {
  830. fimc->source_subdev_grp_id = 0;
  831. fimc->sensor = NULL;
  832. }
  833. break;
  834. case FLITE_SD_PAD_SOURCE_DMA:
  835. if (!(flags & MEDIA_LNK_FL_ENABLED))
  836. atomic_set(&fimc->out_path, FIMC_IO_NONE);
  837. else if (remote_ent_type == MEDIA_ENT_T_DEVNODE)
  838. atomic_set(&fimc->out_path, FIMC_IO_DMA);
  839. else
  840. ret = -EINVAL;
  841. break;
  842. case FLITE_SD_PAD_SOURCE_ISP:
  843. if (!(flags & MEDIA_LNK_FL_ENABLED))
  844. atomic_set(&fimc->out_path, FIMC_IO_NONE);
  845. else if (remote_ent_type == MEDIA_ENT_T_V4L2_SUBDEV)
  846. atomic_set(&fimc->out_path, FIMC_IO_ISP);
  847. else
  848. ret = -EINVAL;
  849. break;
  850. default:
  851. v4l2_err(sd, "Invalid pad index\n");
  852. ret = -EINVAL;
  853. }
  854. mb();
  855. mutex_unlock(&fimc->lock);
  856. return ret;
  857. }
  858. static const struct media_entity_operations fimc_lite_subdev_media_ops = {
  859. .link_setup = fimc_lite_link_setup,
  860. };
  861. static int fimc_lite_subdev_enum_mbus_code(struct v4l2_subdev *sd,
  862. struct v4l2_subdev_fh *fh,
  863. struct v4l2_subdev_mbus_code_enum *code)
  864. {
  865. const struct fimc_fmt *fmt;
  866. fmt = fimc_lite_find_format(NULL, NULL, 0, code->index);
  867. if (!fmt)
  868. return -EINVAL;
  869. code->code = fmt->mbus_code;
  870. return 0;
  871. }
  872. static int fimc_lite_subdev_get_fmt(struct v4l2_subdev *sd,
  873. struct v4l2_subdev_fh *fh,
  874. struct v4l2_subdev_format *fmt)
  875. {
  876. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  877. struct v4l2_mbus_framefmt *mf = &fmt->format;
  878. struct flite_frame *f = &fimc->inp_frame;
  879. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  880. mf = v4l2_subdev_get_try_format(fh, fmt->pad);
  881. fmt->format = *mf;
  882. return 0;
  883. }
  884. mf->colorspace = V4L2_COLORSPACE_JPEG;
  885. mutex_lock(&fimc->lock);
  886. mf->code = f->fmt->mbus_code;
  887. if (fmt->pad == FLITE_SD_PAD_SINK) {
  888. /* full camera input frame size */
  889. mf->width = f->f_width;
  890. mf->height = f->f_height;
  891. } else {
  892. /* crop size */
  893. mf->width = f->rect.width;
  894. mf->height = f->rect.height;
  895. }
  896. mutex_unlock(&fimc->lock);
  897. return 0;
  898. }
  899. static int fimc_lite_subdev_set_fmt(struct v4l2_subdev *sd,
  900. struct v4l2_subdev_fh *fh,
  901. struct v4l2_subdev_format *fmt)
  902. {
  903. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  904. struct v4l2_mbus_framefmt *mf = &fmt->format;
  905. struct flite_frame *sink = &fimc->inp_frame;
  906. struct flite_frame *source = &fimc->out_frame;
  907. const struct fimc_fmt *ffmt;
  908. v4l2_dbg(1, debug, sd, "pad%d: code: 0x%x, %dx%d\n",
  909. fmt->pad, mf->code, mf->width, mf->height);
  910. mf->colorspace = V4L2_COLORSPACE_JPEG;
  911. mutex_lock(&fimc->lock);
  912. if ((atomic_read(&fimc->out_path) == FIMC_IO_ISP &&
  913. sd->entity.stream_count > 0) ||
  914. (atomic_read(&fimc->out_path) == FIMC_IO_DMA &&
  915. vb2_is_busy(&fimc->vb_queue))) {
  916. mutex_unlock(&fimc->lock);
  917. return -EBUSY;
  918. }
  919. ffmt = fimc_lite_try_format(fimc, &mf->width, &mf->height,
  920. &mf->code, NULL, fmt->pad);
  921. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  922. mf = v4l2_subdev_get_try_format(fh, fmt->pad);
  923. *mf = fmt->format;
  924. mutex_unlock(&fimc->lock);
  925. return 0;
  926. }
  927. if (fmt->pad == FLITE_SD_PAD_SINK) {
  928. sink->f_width = mf->width;
  929. sink->f_height = mf->height;
  930. sink->fmt = ffmt;
  931. /* Set sink crop rectangle */
  932. sink->rect.width = mf->width;
  933. sink->rect.height = mf->height;
  934. sink->rect.left = 0;
  935. sink->rect.top = 0;
  936. /* Reset source format and crop rectangle */
  937. source->rect = sink->rect;
  938. source->f_width = mf->width;
  939. source->f_height = mf->height;
  940. } else {
  941. /* Allow changing format only on sink pad */
  942. mf->code = sink->fmt->mbus_code;
  943. mf->width = sink->rect.width;
  944. mf->height = sink->rect.height;
  945. }
  946. mutex_unlock(&fimc->lock);
  947. return 0;
  948. }
  949. static int fimc_lite_subdev_get_selection(struct v4l2_subdev *sd,
  950. struct v4l2_subdev_fh *fh,
  951. struct v4l2_subdev_selection *sel)
  952. {
  953. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  954. struct flite_frame *f = &fimc->inp_frame;
  955. if ((sel->target != V4L2_SEL_TGT_CROP &&
  956. sel->target != V4L2_SEL_TGT_CROP_BOUNDS) ||
  957. sel->pad != FLITE_SD_PAD_SINK)
  958. return -EINVAL;
  959. if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
  960. sel->r = *v4l2_subdev_get_try_crop(fh, sel->pad);
  961. return 0;
  962. }
  963. mutex_lock(&fimc->lock);
  964. if (sel->target == V4L2_SEL_TGT_CROP) {
  965. sel->r = f->rect;
  966. } else {
  967. sel->r.left = 0;
  968. sel->r.top = 0;
  969. sel->r.width = f->f_width;
  970. sel->r.height = f->f_height;
  971. }
  972. mutex_unlock(&fimc->lock);
  973. v4l2_dbg(1, debug, sd, "%s: (%d,%d) %dx%d, f_w: %d, f_h: %d\n",
  974. __func__, f->rect.left, f->rect.top, f->rect.width,
  975. f->rect.height, f->f_width, f->f_height);
  976. return 0;
  977. }
  978. static int fimc_lite_subdev_set_selection(struct v4l2_subdev *sd,
  979. struct v4l2_subdev_fh *fh,
  980. struct v4l2_subdev_selection *sel)
  981. {
  982. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  983. struct flite_frame *f = &fimc->inp_frame;
  984. int ret = 0;
  985. if (sel->target != V4L2_SEL_TGT_CROP || sel->pad != FLITE_SD_PAD_SINK)
  986. return -EINVAL;
  987. mutex_lock(&fimc->lock);
  988. fimc_lite_try_crop(fimc, &sel->r);
  989. if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
  990. *v4l2_subdev_get_try_crop(fh, sel->pad) = sel->r;
  991. } else {
  992. unsigned long flags;
  993. spin_lock_irqsave(&fimc->slock, flags);
  994. f->rect = sel->r;
  995. /* Same crop rectangle on the source pad */
  996. fimc->out_frame.rect = sel->r;
  997. set_bit(ST_FLITE_CONFIG, &fimc->state);
  998. spin_unlock_irqrestore(&fimc->slock, flags);
  999. }
  1000. mutex_unlock(&fimc->lock);
  1001. v4l2_dbg(1, debug, sd, "%s: (%d,%d) %dx%d, f_w: %d, f_h: %d\n",
  1002. __func__, f->rect.left, f->rect.top, f->rect.width,
  1003. f->rect.height, f->f_width, f->f_height);
  1004. return ret;
  1005. }
  1006. static int fimc_lite_subdev_s_stream(struct v4l2_subdev *sd, int on)
  1007. {
  1008. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1009. unsigned long flags;
  1010. int ret;
  1011. /*
  1012. * Find sensor subdev linked to FIMC-LITE directly or through
  1013. * MIPI-CSIS. This is required for configuration where FIMC-LITE
  1014. * is used as a subdev only and feeds data internally to FIMC-IS.
  1015. * The pipeline links are protected through entity.stream_count
  1016. * so there is no need to take the media graph mutex here.
  1017. */
  1018. fimc->sensor = __find_remote_sensor(&sd->entity);
  1019. if (atomic_read(&fimc->out_path) != FIMC_IO_ISP)
  1020. return -ENOIOCTLCMD;
  1021. mutex_lock(&fimc->lock);
  1022. if (on) {
  1023. flite_hw_reset(fimc);
  1024. ret = fimc_lite_hw_init(fimc, true);
  1025. if (!ret) {
  1026. spin_lock_irqsave(&fimc->slock, flags);
  1027. flite_hw_capture_start(fimc);
  1028. spin_unlock_irqrestore(&fimc->slock, flags);
  1029. }
  1030. } else {
  1031. set_bit(ST_FLITE_OFF, &fimc->state);
  1032. spin_lock_irqsave(&fimc->slock, flags);
  1033. flite_hw_capture_stop(fimc);
  1034. spin_unlock_irqrestore(&fimc->slock, flags);
  1035. ret = wait_event_timeout(fimc->irq_queue,
  1036. !test_bit(ST_FLITE_OFF, &fimc->state),
  1037. msecs_to_jiffies(200));
  1038. if (ret == 0)
  1039. v4l2_err(sd, "s_stream(0) timeout\n");
  1040. clear_bit(ST_FLITE_RUN, &fimc->state);
  1041. }
  1042. mutex_unlock(&fimc->lock);
  1043. return ret;
  1044. }
  1045. static int fimc_lite_log_status(struct v4l2_subdev *sd)
  1046. {
  1047. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1048. flite_hw_dump_regs(fimc, __func__);
  1049. return 0;
  1050. }
  1051. static int fimc_lite_subdev_registered(struct v4l2_subdev *sd)
  1052. {
  1053. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1054. struct vb2_queue *q = &fimc->vb_queue;
  1055. struct video_device *vfd = &fimc->vfd;
  1056. int ret;
  1057. memset(vfd, 0, sizeof(*vfd));
  1058. fimc->inp_frame.fmt = &fimc_lite_formats[0];
  1059. fimc->out_frame.fmt = &fimc_lite_formats[0];
  1060. atomic_set(&fimc->out_path, FIMC_IO_DMA);
  1061. snprintf(vfd->name, sizeof(vfd->name), "fimc-lite.%d.capture",
  1062. fimc->index);
  1063. vfd->fops = &fimc_lite_fops;
  1064. vfd->ioctl_ops = &fimc_lite_ioctl_ops;
  1065. vfd->v4l2_dev = sd->v4l2_dev;
  1066. vfd->minor = -1;
  1067. vfd->release = video_device_release_empty;
  1068. vfd->queue = q;
  1069. fimc->reqbufs_count = 0;
  1070. INIT_LIST_HEAD(&fimc->pending_buf_q);
  1071. INIT_LIST_HEAD(&fimc->active_buf_q);
  1072. memset(q, 0, sizeof(*q));
  1073. q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
  1074. q->io_modes = VB2_MMAP | VB2_USERPTR;
  1075. q->ops = &fimc_lite_qops;
  1076. q->mem_ops = &vb2_dma_contig_memops;
  1077. q->buf_struct_size = sizeof(struct flite_buffer);
  1078. q->drv_priv = fimc;
  1079. q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
  1080. q->lock = &fimc->lock;
  1081. ret = vb2_queue_init(q);
  1082. if (ret < 0)
  1083. return ret;
  1084. fimc->vd_pad.flags = MEDIA_PAD_FL_SINK;
  1085. ret = media_entity_init(&vfd->entity, 1, &fimc->vd_pad, 0);
  1086. if (ret < 0)
  1087. return ret;
  1088. video_set_drvdata(vfd, fimc);
  1089. fimc->pipeline_ops = v4l2_get_subdev_hostdata(sd);
  1090. ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
  1091. if (ret < 0) {
  1092. media_entity_cleanup(&vfd->entity);
  1093. fimc->pipeline_ops = NULL;
  1094. return ret;
  1095. }
  1096. v4l2_info(sd->v4l2_dev, "Registered %s as /dev/%s\n",
  1097. vfd->name, video_device_node_name(vfd));
  1098. return 0;
  1099. }
  1100. static void fimc_lite_subdev_unregistered(struct v4l2_subdev *sd)
  1101. {
  1102. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1103. if (fimc == NULL)
  1104. return;
  1105. if (video_is_registered(&fimc->vfd)) {
  1106. video_unregister_device(&fimc->vfd);
  1107. media_entity_cleanup(&fimc->vfd.entity);
  1108. fimc->pipeline_ops = NULL;
  1109. }
  1110. }
  1111. static const struct v4l2_subdev_internal_ops fimc_lite_subdev_internal_ops = {
  1112. .registered = fimc_lite_subdev_registered,
  1113. .unregistered = fimc_lite_subdev_unregistered,
  1114. };
  1115. static const struct v4l2_subdev_pad_ops fimc_lite_subdev_pad_ops = {
  1116. .enum_mbus_code = fimc_lite_subdev_enum_mbus_code,
  1117. .get_selection = fimc_lite_subdev_get_selection,
  1118. .set_selection = fimc_lite_subdev_set_selection,
  1119. .get_fmt = fimc_lite_subdev_get_fmt,
  1120. .set_fmt = fimc_lite_subdev_set_fmt,
  1121. };
  1122. static const struct v4l2_subdev_video_ops fimc_lite_subdev_video_ops = {
  1123. .s_stream = fimc_lite_subdev_s_stream,
  1124. };
  1125. static const struct v4l2_subdev_core_ops fimc_lite_core_ops = {
  1126. .log_status = fimc_lite_log_status,
  1127. };
  1128. static struct v4l2_subdev_ops fimc_lite_subdev_ops = {
  1129. .core = &fimc_lite_core_ops,
  1130. .video = &fimc_lite_subdev_video_ops,
  1131. .pad = &fimc_lite_subdev_pad_ops,
  1132. };
  1133. static int fimc_lite_s_ctrl(struct v4l2_ctrl *ctrl)
  1134. {
  1135. struct fimc_lite *fimc = container_of(ctrl->handler, struct fimc_lite,
  1136. ctrl_handler);
  1137. set_bit(ST_FLITE_CONFIG, &fimc->state);
  1138. return 0;
  1139. }
  1140. static const struct v4l2_ctrl_ops fimc_lite_ctrl_ops = {
  1141. .s_ctrl = fimc_lite_s_ctrl,
  1142. };
  1143. static const struct v4l2_ctrl_config fimc_lite_ctrl = {
  1144. .ops = &fimc_lite_ctrl_ops,
  1145. .id = V4L2_CTRL_CLASS_USER | 0x1001,
  1146. .type = V4L2_CTRL_TYPE_BOOLEAN,
  1147. .name = "Test Pattern 640x480",
  1148. .step = 1,
  1149. };
  1150. static int fimc_lite_create_capture_subdev(struct fimc_lite *fimc)
  1151. {
  1152. struct v4l2_ctrl_handler *handler = &fimc->ctrl_handler;
  1153. struct v4l2_subdev *sd = &fimc->subdev;
  1154. int ret;
  1155. v4l2_subdev_init(sd, &fimc_lite_subdev_ops);
  1156. sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  1157. snprintf(sd->name, sizeof(sd->name), "FIMC-LITE.%d", fimc->index);
  1158. fimc->subdev_pads[FLITE_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
  1159. fimc->subdev_pads[FLITE_SD_PAD_SOURCE_DMA].flags = MEDIA_PAD_FL_SOURCE;
  1160. fimc->subdev_pads[FLITE_SD_PAD_SOURCE_ISP].flags = MEDIA_PAD_FL_SOURCE;
  1161. ret = media_entity_init(&sd->entity, FLITE_SD_PADS_NUM,
  1162. fimc->subdev_pads, 0);
  1163. if (ret)
  1164. return ret;
  1165. v4l2_ctrl_handler_init(handler, 1);
  1166. fimc->test_pattern = v4l2_ctrl_new_custom(handler, &fimc_lite_ctrl,
  1167. NULL);
  1168. if (handler->error) {
  1169. media_entity_cleanup(&sd->entity);
  1170. return handler->error;
  1171. }
  1172. sd->ctrl_handler = handler;
  1173. sd->internal_ops = &fimc_lite_subdev_internal_ops;
  1174. sd->entity.ops = &fimc_lite_subdev_media_ops;
  1175. sd->owner = THIS_MODULE;
  1176. v4l2_set_subdevdata(sd, fimc);
  1177. return 0;
  1178. }
  1179. static void fimc_lite_unregister_capture_subdev(struct fimc_lite *fimc)
  1180. {
  1181. struct v4l2_subdev *sd = &fimc->subdev;
  1182. v4l2_device_unregister_subdev(sd);
  1183. media_entity_cleanup(&sd->entity);
  1184. v4l2_ctrl_handler_free(&fimc->ctrl_handler);
  1185. v4l2_set_subdevdata(sd, NULL);
  1186. }
  1187. static void fimc_lite_clk_put(struct fimc_lite *fimc)
  1188. {
  1189. if (IS_ERR_OR_NULL(fimc->clock))
  1190. return;
  1191. clk_unprepare(fimc->clock);
  1192. clk_put(fimc->clock);
  1193. fimc->clock = NULL;
  1194. }
  1195. static int fimc_lite_clk_get(struct fimc_lite *fimc)
  1196. {
  1197. int ret;
  1198. fimc->clock = clk_get(&fimc->pdev->dev, FLITE_CLK_NAME);
  1199. if (IS_ERR(fimc->clock))
  1200. return PTR_ERR(fimc->clock);
  1201. ret = clk_prepare(fimc->clock);
  1202. if (ret < 0) {
  1203. clk_put(fimc->clock);
  1204. fimc->clock = NULL;
  1205. }
  1206. return ret;
  1207. }
  1208. static const struct of_device_id flite_of_match[];
  1209. static int fimc_lite_probe(struct platform_device *pdev)
  1210. {
  1211. struct flite_drvdata *drv_data = NULL;
  1212. struct device *dev = &pdev->dev;
  1213. const struct of_device_id *of_id;
  1214. struct fimc_lite *fimc;
  1215. struct resource *res;
  1216. int ret;
  1217. fimc = devm_kzalloc(dev, sizeof(*fimc), GFP_KERNEL);
  1218. if (!fimc)
  1219. return -ENOMEM;
  1220. if (dev->of_node) {
  1221. of_id = of_match_node(flite_of_match, dev->of_node);
  1222. if (of_id)
  1223. drv_data = (struct flite_drvdata *)of_id->data;
  1224. fimc->index = of_alias_get_id(dev->of_node, "fimc-lite");
  1225. } else {
  1226. drv_data = fimc_lite_get_drvdata(pdev);
  1227. fimc->index = pdev->id;
  1228. }
  1229. if (!drv_data || fimc->index < 0 || fimc->index >= FIMC_LITE_MAX_DEVS)
  1230. return -EINVAL;
  1231. fimc->dd = drv_data;
  1232. fimc->pdev = pdev;
  1233. init_waitqueue_head(&fimc->irq_queue);
  1234. spin_lock_init(&fimc->slock);
  1235. mutex_init(&fimc->lock);
  1236. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1237. fimc->regs = devm_ioremap_resource(dev, res);
  1238. if (IS_ERR(fimc->regs))
  1239. return PTR_ERR(fimc->regs);
  1240. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1241. if (res == NULL) {
  1242. dev_err(dev, "Failed to get IRQ resource\n");
  1243. return -ENXIO;
  1244. }
  1245. ret = fimc_lite_clk_get(fimc);
  1246. if (ret)
  1247. return ret;
  1248. ret = devm_request_irq(dev, res->start, flite_irq_handler,
  1249. 0, dev_name(dev), fimc);
  1250. if (ret) {
  1251. dev_err(dev, "Failed to install irq (%d)\n", ret);
  1252. goto err_clk;
  1253. }
  1254. /* The video node will be created within the subdev's registered() op */
  1255. ret = fimc_lite_create_capture_subdev(fimc);
  1256. if (ret)
  1257. goto err_clk;
  1258. platform_set_drvdata(pdev, fimc);
  1259. pm_runtime_enable(dev);
  1260. ret = pm_runtime_get_sync(dev);
  1261. if (ret < 0)
  1262. goto err_sd;
  1263. fimc->alloc_ctx = vb2_dma_contig_init_ctx(dev);
  1264. if (IS_ERR(fimc->alloc_ctx)) {
  1265. ret = PTR_ERR(fimc->alloc_ctx);
  1266. goto err_pm;
  1267. }
  1268. pm_runtime_put(dev);
  1269. dev_dbg(dev, "FIMC-LITE.%d registered successfully\n",
  1270. fimc->index);
  1271. return 0;
  1272. err_pm:
  1273. pm_runtime_put(dev);
  1274. err_sd:
  1275. fimc_lite_unregister_capture_subdev(fimc);
  1276. err_clk:
  1277. fimc_lite_clk_put(fimc);
  1278. return ret;
  1279. }
  1280. static int fimc_lite_runtime_resume(struct device *dev)
  1281. {
  1282. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1283. clk_enable(fimc->clock);
  1284. return 0;
  1285. }
  1286. static int fimc_lite_runtime_suspend(struct device *dev)
  1287. {
  1288. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1289. clk_disable(fimc->clock);
  1290. return 0;
  1291. }
  1292. #ifdef CONFIG_PM_SLEEP
  1293. static int fimc_lite_resume(struct device *dev)
  1294. {
  1295. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1296. struct flite_buffer *buf;
  1297. unsigned long flags;
  1298. int i;
  1299. spin_lock_irqsave(&fimc->slock, flags);
  1300. if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
  1301. !test_bit(ST_FLITE_IN_USE, &fimc->state)) {
  1302. spin_unlock_irqrestore(&fimc->slock, flags);
  1303. return 0;
  1304. }
  1305. flite_hw_reset(fimc);
  1306. spin_unlock_irqrestore(&fimc->slock, flags);
  1307. if (!test_and_clear_bit(ST_FLITE_SUSPENDED, &fimc->state))
  1308. return 0;
  1309. INIT_LIST_HEAD(&fimc->active_buf_q);
  1310. fimc_pipeline_call(fimc, open, &fimc->pipeline,
  1311. &fimc->vfd.entity, false);
  1312. fimc_lite_hw_init(fimc, atomic_read(&fimc->out_path) == FIMC_IO_ISP);
  1313. clear_bit(ST_FLITE_SUSPENDED, &fimc->state);
  1314. for (i = 0; i < fimc->reqbufs_count; i++) {
  1315. if (list_empty(&fimc->pending_buf_q))
  1316. break;
  1317. buf = fimc_lite_pending_queue_pop(fimc);
  1318. buffer_queue(&buf->vb);
  1319. }
  1320. return 0;
  1321. }
  1322. static int fimc_lite_suspend(struct device *dev)
  1323. {
  1324. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1325. bool suspend = test_bit(ST_FLITE_IN_USE, &fimc->state);
  1326. int ret;
  1327. if (test_and_set_bit(ST_LPM, &fimc->state))
  1328. return 0;
  1329. ret = fimc_lite_stop_capture(fimc, suspend);
  1330. if (ret < 0 || !fimc_lite_active(fimc))
  1331. return ret;
  1332. return fimc_pipeline_call(fimc, close, &fimc->pipeline);
  1333. }
  1334. #endif /* CONFIG_PM_SLEEP */
  1335. static int fimc_lite_remove(struct platform_device *pdev)
  1336. {
  1337. struct fimc_lite *fimc = platform_get_drvdata(pdev);
  1338. struct device *dev = &pdev->dev;
  1339. pm_runtime_disable(dev);
  1340. pm_runtime_set_suspended(dev);
  1341. fimc_lite_unregister_capture_subdev(fimc);
  1342. vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
  1343. fimc_lite_clk_put(fimc);
  1344. dev_info(dev, "Driver unloaded\n");
  1345. return 0;
  1346. }
  1347. static const struct dev_pm_ops fimc_lite_pm_ops = {
  1348. SET_SYSTEM_SLEEP_PM_OPS(fimc_lite_suspend, fimc_lite_resume)
  1349. SET_RUNTIME_PM_OPS(fimc_lite_runtime_suspend, fimc_lite_runtime_resume,
  1350. NULL)
  1351. };
  1352. /* EXYNOS4212, EXYNOS4412 */
  1353. static struct flite_drvdata fimc_lite_drvdata_exynos4 = {
  1354. .max_width = 8192,
  1355. .max_height = 8192,
  1356. .out_width_align = 8,
  1357. .win_hor_offs_align = 2,
  1358. .out_hor_offs_align = 8,
  1359. };
  1360. static struct platform_device_id fimc_lite_driver_ids[] = {
  1361. {
  1362. .name = "exynos-fimc-lite",
  1363. .driver_data = (unsigned long)&fimc_lite_drvdata_exynos4,
  1364. },
  1365. { /* sentinel */ },
  1366. };
  1367. MODULE_DEVICE_TABLE(platform, fimc_lite_driver_ids);
  1368. static const struct of_device_id flite_of_match[] = {
  1369. {
  1370. .compatible = "samsung,exynos4212-fimc-lite",
  1371. .data = &fimc_lite_drvdata_exynos4,
  1372. },
  1373. { /* sentinel */ },
  1374. };
  1375. MODULE_DEVICE_TABLE(of, flite_of_match);
  1376. static struct platform_driver fimc_lite_driver = {
  1377. .probe = fimc_lite_probe,
  1378. .remove = fimc_lite_remove,
  1379. .id_table = fimc_lite_driver_ids,
  1380. .driver = {
  1381. .of_match_table = flite_of_match,
  1382. .name = FIMC_LITE_DRV_NAME,
  1383. .owner = THIS_MODULE,
  1384. .pm = &fimc_lite_pm_ops,
  1385. }
  1386. };
  1387. module_platform_driver(fimc_lite_driver);
  1388. MODULE_LICENSE("GPL");
  1389. MODULE_ALIAS("platform:" FIMC_LITE_DRV_NAME);