gpio-omap.c 40 KB

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  1. /*
  2. * Support functions for OMAP GPIO
  3. *
  4. * Copyright (C) 2003-2005 Nokia Corporation
  5. * Written by Juha Yrjölä <juha.yrjola@nokia.com>
  6. *
  7. * Copyright (C) 2009 Texas Instruments
  8. * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/module.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/syscore_ops.h>
  18. #include <linux/err.h>
  19. #include <linux/clk.h>
  20. #include <linux/io.h>
  21. #include <linux/device.h>
  22. #include <linux/pm_runtime.h>
  23. #include <linux/pm.h>
  24. #include <linux/of.h>
  25. #include <linux/of_device.h>
  26. #include <linux/irqdomain.h>
  27. #include <linux/irqchip/chained_irq.h>
  28. #include <linux/gpio.h>
  29. #include <linux/platform_data/gpio-omap.h>
  30. #define OFF_MODE 1
  31. static LIST_HEAD(omap_gpio_list);
  32. struct gpio_regs {
  33. u32 irqenable1;
  34. u32 irqenable2;
  35. u32 wake_en;
  36. u32 ctrl;
  37. u32 oe;
  38. u32 leveldetect0;
  39. u32 leveldetect1;
  40. u32 risingdetect;
  41. u32 fallingdetect;
  42. u32 dataout;
  43. u32 debounce;
  44. u32 debounce_en;
  45. };
  46. struct gpio_bank {
  47. struct list_head node;
  48. void __iomem *base;
  49. u16 irq;
  50. struct irq_domain *domain;
  51. u32 non_wakeup_gpios;
  52. u32 enabled_non_wakeup_gpios;
  53. struct gpio_regs context;
  54. u32 saved_datain;
  55. u32 level_mask;
  56. u32 toggle_mask;
  57. spinlock_t lock;
  58. struct gpio_chip chip;
  59. struct clk *dbck;
  60. u32 mod_usage;
  61. u32 dbck_enable_mask;
  62. bool dbck_enabled;
  63. struct device *dev;
  64. bool is_mpuio;
  65. bool dbck_flag;
  66. bool loses_context;
  67. int stride;
  68. u32 width;
  69. int context_loss_count;
  70. int power_mode;
  71. bool workaround_enabled;
  72. void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
  73. int (*get_context_loss_count)(struct device *dev);
  74. struct omap_gpio_reg_offs *regs;
  75. };
  76. #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
  77. #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
  78. #define GPIO_MOD_CTRL_BIT BIT(0)
  79. static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
  80. {
  81. return bank->chip.base + gpio_irq;
  82. }
  83. static int omap_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
  84. {
  85. struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
  86. return irq_find_mapping(bank->domain, offset);
  87. }
  88. static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
  89. {
  90. void __iomem *reg = bank->base;
  91. u32 l;
  92. reg += bank->regs->direction;
  93. l = __raw_readl(reg);
  94. if (is_input)
  95. l |= 1 << gpio;
  96. else
  97. l &= ~(1 << gpio);
  98. __raw_writel(l, reg);
  99. bank->context.oe = l;
  100. }
  101. /* set data out value using dedicate set/clear register */
  102. static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
  103. {
  104. void __iomem *reg = bank->base;
  105. u32 l = GPIO_BIT(bank, gpio);
  106. if (enable) {
  107. reg += bank->regs->set_dataout;
  108. bank->context.dataout |= l;
  109. } else {
  110. reg += bank->regs->clr_dataout;
  111. bank->context.dataout &= ~l;
  112. }
  113. __raw_writel(l, reg);
  114. }
  115. /* set data out value using mask register */
  116. static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
  117. {
  118. void __iomem *reg = bank->base + bank->regs->dataout;
  119. u32 gpio_bit = GPIO_BIT(bank, gpio);
  120. u32 l;
  121. l = __raw_readl(reg);
  122. if (enable)
  123. l |= gpio_bit;
  124. else
  125. l &= ~gpio_bit;
  126. __raw_writel(l, reg);
  127. bank->context.dataout = l;
  128. }
  129. static int _get_gpio_datain(struct gpio_bank *bank, int offset)
  130. {
  131. void __iomem *reg = bank->base + bank->regs->datain;
  132. return (__raw_readl(reg) & (1 << offset)) != 0;
  133. }
  134. static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
  135. {
  136. void __iomem *reg = bank->base + bank->regs->dataout;
  137. return (__raw_readl(reg) & (1 << offset)) != 0;
  138. }
  139. static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
  140. {
  141. int l = __raw_readl(base + reg);
  142. if (set)
  143. l |= mask;
  144. else
  145. l &= ~mask;
  146. __raw_writel(l, base + reg);
  147. }
  148. static inline void _gpio_dbck_enable(struct gpio_bank *bank)
  149. {
  150. if (bank->dbck_enable_mask && !bank->dbck_enabled) {
  151. clk_enable(bank->dbck);
  152. bank->dbck_enabled = true;
  153. __raw_writel(bank->dbck_enable_mask,
  154. bank->base + bank->regs->debounce_en);
  155. }
  156. }
  157. static inline void _gpio_dbck_disable(struct gpio_bank *bank)
  158. {
  159. if (bank->dbck_enable_mask && bank->dbck_enabled) {
  160. /*
  161. * Disable debounce before cutting it's clock. If debounce is
  162. * enabled but the clock is not, GPIO module seems to be unable
  163. * to detect events and generate interrupts at least on OMAP3.
  164. */
  165. __raw_writel(0, bank->base + bank->regs->debounce_en);
  166. clk_disable(bank->dbck);
  167. bank->dbck_enabled = false;
  168. }
  169. }
  170. /**
  171. * _set_gpio_debounce - low level gpio debounce time
  172. * @bank: the gpio bank we're acting upon
  173. * @gpio: the gpio number on this @gpio
  174. * @debounce: debounce time to use
  175. *
  176. * OMAP's debounce time is in 31us steps so we need
  177. * to convert and round up to the closest unit.
  178. */
  179. static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
  180. unsigned debounce)
  181. {
  182. void __iomem *reg;
  183. u32 val;
  184. u32 l;
  185. if (!bank->dbck_flag)
  186. return;
  187. if (debounce < 32)
  188. debounce = 0x01;
  189. else if (debounce > 7936)
  190. debounce = 0xff;
  191. else
  192. debounce = (debounce / 0x1f) - 1;
  193. l = GPIO_BIT(bank, gpio);
  194. clk_enable(bank->dbck);
  195. reg = bank->base + bank->regs->debounce;
  196. __raw_writel(debounce, reg);
  197. reg = bank->base + bank->regs->debounce_en;
  198. val = __raw_readl(reg);
  199. if (debounce)
  200. val |= l;
  201. else
  202. val &= ~l;
  203. bank->dbck_enable_mask = val;
  204. __raw_writel(val, reg);
  205. clk_disable(bank->dbck);
  206. /*
  207. * Enable debounce clock per module.
  208. * This call is mandatory because in omap_gpio_request() when
  209. * *_runtime_get_sync() is called, _gpio_dbck_enable() within
  210. * runtime callbck fails to turn on dbck because dbck_enable_mask
  211. * used within _gpio_dbck_enable() is still not initialized at
  212. * that point. Therefore we have to enable dbck here.
  213. */
  214. _gpio_dbck_enable(bank);
  215. if (bank->dbck_enable_mask) {
  216. bank->context.debounce = debounce;
  217. bank->context.debounce_en = val;
  218. }
  219. }
  220. /**
  221. * _clear_gpio_debounce - clear debounce settings for a gpio
  222. * @bank: the gpio bank we're acting upon
  223. * @gpio: the gpio number on this @gpio
  224. *
  225. * If a gpio is using debounce, then clear the debounce enable bit and if
  226. * this is the only gpio in this bank using debounce, then clear the debounce
  227. * time too. The debounce clock will also be disabled when calling this function
  228. * if this is the only gpio in the bank using debounce.
  229. */
  230. static void _clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio)
  231. {
  232. u32 gpio_bit = GPIO_BIT(bank, gpio);
  233. if (!bank->dbck_flag)
  234. return;
  235. if (!(bank->dbck_enable_mask & gpio_bit))
  236. return;
  237. bank->dbck_enable_mask &= ~gpio_bit;
  238. bank->context.debounce_en &= ~gpio_bit;
  239. __raw_writel(bank->context.debounce_en,
  240. bank->base + bank->regs->debounce_en);
  241. if (!bank->dbck_enable_mask) {
  242. bank->context.debounce = 0;
  243. __raw_writel(bank->context.debounce, bank->base +
  244. bank->regs->debounce);
  245. clk_disable(bank->dbck);
  246. bank->dbck_enabled = false;
  247. }
  248. }
  249. static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
  250. unsigned trigger)
  251. {
  252. void __iomem *base = bank->base;
  253. u32 gpio_bit = 1 << gpio;
  254. _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
  255. trigger & IRQ_TYPE_LEVEL_LOW);
  256. _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
  257. trigger & IRQ_TYPE_LEVEL_HIGH);
  258. _gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
  259. trigger & IRQ_TYPE_EDGE_RISING);
  260. _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
  261. trigger & IRQ_TYPE_EDGE_FALLING);
  262. bank->context.leveldetect0 =
  263. __raw_readl(bank->base + bank->regs->leveldetect0);
  264. bank->context.leveldetect1 =
  265. __raw_readl(bank->base + bank->regs->leveldetect1);
  266. bank->context.risingdetect =
  267. __raw_readl(bank->base + bank->regs->risingdetect);
  268. bank->context.fallingdetect =
  269. __raw_readl(bank->base + bank->regs->fallingdetect);
  270. if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
  271. _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
  272. bank->context.wake_en =
  273. __raw_readl(bank->base + bank->regs->wkup_en);
  274. }
  275. /* This part needs to be executed always for OMAP{34xx, 44xx} */
  276. if (!bank->regs->irqctrl) {
  277. /* On omap24xx proceed only when valid GPIO bit is set */
  278. if (bank->non_wakeup_gpios) {
  279. if (!(bank->non_wakeup_gpios & gpio_bit))
  280. goto exit;
  281. }
  282. /*
  283. * Log the edge gpio and manually trigger the IRQ
  284. * after resume if the input level changes
  285. * to avoid irq lost during PER RET/OFF mode
  286. * Applies for omap2 non-wakeup gpio and all omap3 gpios
  287. */
  288. if (trigger & IRQ_TYPE_EDGE_BOTH)
  289. bank->enabled_non_wakeup_gpios |= gpio_bit;
  290. else
  291. bank->enabled_non_wakeup_gpios &= ~gpio_bit;
  292. }
  293. exit:
  294. bank->level_mask =
  295. __raw_readl(bank->base + bank->regs->leveldetect0) |
  296. __raw_readl(bank->base + bank->regs->leveldetect1);
  297. }
  298. #ifdef CONFIG_ARCH_OMAP1
  299. /*
  300. * This only applies to chips that can't do both rising and falling edge
  301. * detection at once. For all other chips, this function is a noop.
  302. */
  303. static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
  304. {
  305. void __iomem *reg = bank->base;
  306. u32 l = 0;
  307. if (!bank->regs->irqctrl)
  308. return;
  309. reg += bank->regs->irqctrl;
  310. l = __raw_readl(reg);
  311. if ((l >> gpio) & 1)
  312. l &= ~(1 << gpio);
  313. else
  314. l |= 1 << gpio;
  315. __raw_writel(l, reg);
  316. }
  317. #else
  318. static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
  319. #endif
  320. static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
  321. unsigned trigger)
  322. {
  323. void __iomem *reg = bank->base;
  324. void __iomem *base = bank->base;
  325. u32 l = 0;
  326. if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
  327. set_gpio_trigger(bank, gpio, trigger);
  328. } else if (bank->regs->irqctrl) {
  329. reg += bank->regs->irqctrl;
  330. l = __raw_readl(reg);
  331. if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
  332. bank->toggle_mask |= 1 << gpio;
  333. if (trigger & IRQ_TYPE_EDGE_RISING)
  334. l |= 1 << gpio;
  335. else if (trigger & IRQ_TYPE_EDGE_FALLING)
  336. l &= ~(1 << gpio);
  337. else
  338. return -EINVAL;
  339. __raw_writel(l, reg);
  340. } else if (bank->regs->edgectrl1) {
  341. if (gpio & 0x08)
  342. reg += bank->regs->edgectrl2;
  343. else
  344. reg += bank->regs->edgectrl1;
  345. gpio &= 0x07;
  346. l = __raw_readl(reg);
  347. l &= ~(3 << (gpio << 1));
  348. if (trigger & IRQ_TYPE_EDGE_RISING)
  349. l |= 2 << (gpio << 1);
  350. if (trigger & IRQ_TYPE_EDGE_FALLING)
  351. l |= 1 << (gpio << 1);
  352. /* Enable wake-up during idle for dynamic tick */
  353. _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
  354. bank->context.wake_en =
  355. __raw_readl(bank->base + bank->regs->wkup_en);
  356. __raw_writel(l, reg);
  357. }
  358. return 0;
  359. }
  360. static int gpio_irq_type(struct irq_data *d, unsigned type)
  361. {
  362. struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
  363. unsigned gpio = 0;
  364. int retval;
  365. unsigned long flags;
  366. if (WARN_ON(!bank->mod_usage))
  367. return -EINVAL;
  368. #ifdef CONFIG_ARCH_OMAP1
  369. if (d->irq > IH_MPUIO_BASE)
  370. gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
  371. #endif
  372. if (!gpio)
  373. gpio = irq_to_gpio(bank, d->hwirq);
  374. if (type & ~IRQ_TYPE_SENSE_MASK)
  375. return -EINVAL;
  376. if (!bank->regs->leveldetect0 &&
  377. (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
  378. return -EINVAL;
  379. spin_lock_irqsave(&bank->lock, flags);
  380. retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
  381. spin_unlock_irqrestore(&bank->lock, flags);
  382. if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
  383. __irq_set_handler_locked(d->irq, handle_level_irq);
  384. else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
  385. __irq_set_handler_locked(d->irq, handle_edge_irq);
  386. return retval;
  387. }
  388. static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
  389. {
  390. void __iomem *reg = bank->base;
  391. reg += bank->regs->irqstatus;
  392. __raw_writel(gpio_mask, reg);
  393. /* Workaround for clearing DSP GPIO interrupts to allow retention */
  394. if (bank->regs->irqstatus2) {
  395. reg = bank->base + bank->regs->irqstatus2;
  396. __raw_writel(gpio_mask, reg);
  397. }
  398. /* Flush posted write for the irq status to avoid spurious interrupts */
  399. __raw_readl(reg);
  400. }
  401. static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
  402. {
  403. _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
  404. }
  405. static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
  406. {
  407. void __iomem *reg = bank->base;
  408. u32 l;
  409. u32 mask = (1 << bank->width) - 1;
  410. reg += bank->regs->irqenable;
  411. l = __raw_readl(reg);
  412. if (bank->regs->irqenable_inv)
  413. l = ~l;
  414. l &= mask;
  415. return l;
  416. }
  417. static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
  418. {
  419. void __iomem *reg = bank->base;
  420. u32 l;
  421. if (bank->regs->set_irqenable) {
  422. reg += bank->regs->set_irqenable;
  423. l = gpio_mask;
  424. bank->context.irqenable1 |= gpio_mask;
  425. } else {
  426. reg += bank->regs->irqenable;
  427. l = __raw_readl(reg);
  428. if (bank->regs->irqenable_inv)
  429. l &= ~gpio_mask;
  430. else
  431. l |= gpio_mask;
  432. bank->context.irqenable1 = l;
  433. }
  434. __raw_writel(l, reg);
  435. }
  436. static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
  437. {
  438. void __iomem *reg = bank->base;
  439. u32 l;
  440. if (bank->regs->clr_irqenable) {
  441. reg += bank->regs->clr_irqenable;
  442. l = gpio_mask;
  443. bank->context.irqenable1 &= ~gpio_mask;
  444. } else {
  445. reg += bank->regs->irqenable;
  446. l = __raw_readl(reg);
  447. if (bank->regs->irqenable_inv)
  448. l |= gpio_mask;
  449. else
  450. l &= ~gpio_mask;
  451. bank->context.irqenable1 = l;
  452. }
  453. __raw_writel(l, reg);
  454. }
  455. static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
  456. {
  457. if (enable)
  458. _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
  459. else
  460. _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
  461. }
  462. /*
  463. * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
  464. * 1510 does not seem to have a wake-up register. If JTAG is connected
  465. * to the target, system will wake up always on GPIO events. While
  466. * system is running all registered GPIO interrupts need to have wake-up
  467. * enabled. When system is suspended, only selected GPIO interrupts need
  468. * to have wake-up enabled.
  469. */
  470. static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
  471. {
  472. u32 gpio_bit = GPIO_BIT(bank, gpio);
  473. unsigned long flags;
  474. if (bank->non_wakeup_gpios & gpio_bit) {
  475. dev_err(bank->dev,
  476. "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
  477. return -EINVAL;
  478. }
  479. spin_lock_irqsave(&bank->lock, flags);
  480. if (enable)
  481. bank->context.wake_en |= gpio_bit;
  482. else
  483. bank->context.wake_en &= ~gpio_bit;
  484. __raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en);
  485. spin_unlock_irqrestore(&bank->lock, flags);
  486. return 0;
  487. }
  488. static void _reset_gpio(struct gpio_bank *bank, int gpio)
  489. {
  490. _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
  491. _set_gpio_irqenable(bank, gpio, 0);
  492. _clear_gpio_irqstatus(bank, gpio);
  493. _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
  494. _clear_gpio_debounce(bank, gpio);
  495. }
  496. /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
  497. static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
  498. {
  499. struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
  500. unsigned int gpio = irq_to_gpio(bank, d->hwirq);
  501. return _set_gpio_wakeup(bank, gpio, enable);
  502. }
  503. static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
  504. {
  505. struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
  506. unsigned long flags;
  507. /*
  508. * If this is the first gpio_request for the bank,
  509. * enable the bank module.
  510. */
  511. if (!bank->mod_usage)
  512. pm_runtime_get_sync(bank->dev);
  513. spin_lock_irqsave(&bank->lock, flags);
  514. /* Set trigger to none. You need to enable the desired trigger with
  515. * request_irq() or set_irq_type().
  516. */
  517. _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
  518. if (bank->regs->pinctrl) {
  519. void __iomem *reg = bank->base + bank->regs->pinctrl;
  520. /* Claim the pin for MPU */
  521. __raw_writel(__raw_readl(reg) | (1 << offset), reg);
  522. }
  523. if (bank->regs->ctrl && !bank->mod_usage) {
  524. void __iomem *reg = bank->base + bank->regs->ctrl;
  525. u32 ctrl;
  526. ctrl = __raw_readl(reg);
  527. /* Module is enabled, clocks are not gated */
  528. ctrl &= ~GPIO_MOD_CTRL_BIT;
  529. __raw_writel(ctrl, reg);
  530. bank->context.ctrl = ctrl;
  531. }
  532. bank->mod_usage |= 1 << offset;
  533. spin_unlock_irqrestore(&bank->lock, flags);
  534. return 0;
  535. }
  536. static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
  537. {
  538. struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
  539. void __iomem *base = bank->base;
  540. unsigned long flags;
  541. spin_lock_irqsave(&bank->lock, flags);
  542. if (bank->regs->wkup_en) {
  543. /* Disable wake-up during idle for dynamic tick */
  544. _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
  545. bank->context.wake_en =
  546. __raw_readl(bank->base + bank->regs->wkup_en);
  547. }
  548. bank->mod_usage &= ~(1 << offset);
  549. if (bank->regs->ctrl && !bank->mod_usage) {
  550. void __iomem *reg = bank->base + bank->regs->ctrl;
  551. u32 ctrl;
  552. ctrl = __raw_readl(reg);
  553. /* Module is disabled, clocks are gated */
  554. ctrl |= GPIO_MOD_CTRL_BIT;
  555. __raw_writel(ctrl, reg);
  556. bank->context.ctrl = ctrl;
  557. }
  558. _reset_gpio(bank, bank->chip.base + offset);
  559. spin_unlock_irqrestore(&bank->lock, flags);
  560. /*
  561. * If this is the last gpio to be freed in the bank,
  562. * disable the bank module.
  563. */
  564. if (!bank->mod_usage)
  565. pm_runtime_put(bank->dev);
  566. }
  567. /*
  568. * We need to unmask the GPIO bank interrupt as soon as possible to
  569. * avoid missing GPIO interrupts for other lines in the bank.
  570. * Then we need to mask-read-clear-unmask the triggered GPIO lines
  571. * in the bank to avoid missing nested interrupts for a GPIO line.
  572. * If we wait to unmask individual GPIO lines in the bank after the
  573. * line's interrupt handler has been run, we may miss some nested
  574. * interrupts.
  575. */
  576. static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
  577. {
  578. void __iomem *isr_reg = NULL;
  579. u32 isr;
  580. unsigned int bit;
  581. struct gpio_bank *bank;
  582. int unmasked = 0;
  583. struct irq_chip *chip = irq_desc_get_chip(desc);
  584. chained_irq_enter(chip, desc);
  585. bank = irq_get_handler_data(irq);
  586. isr_reg = bank->base + bank->regs->irqstatus;
  587. pm_runtime_get_sync(bank->dev);
  588. if (WARN_ON(!isr_reg))
  589. goto exit;
  590. while (1) {
  591. u32 isr_saved, level_mask = 0;
  592. u32 enabled;
  593. enabled = _get_gpio_irqbank_mask(bank);
  594. isr_saved = isr = __raw_readl(isr_reg) & enabled;
  595. if (bank->level_mask)
  596. level_mask = bank->level_mask & enabled;
  597. /* clear edge sensitive interrupts before handler(s) are
  598. called so that we don't miss any interrupt occurred while
  599. executing them */
  600. _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
  601. _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
  602. _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
  603. /* if there is only edge sensitive GPIO pin interrupts
  604. configured, we could unmask GPIO bank interrupt immediately */
  605. if (!level_mask && !unmasked) {
  606. unmasked = 1;
  607. chained_irq_exit(chip, desc);
  608. }
  609. if (!isr)
  610. break;
  611. while (isr) {
  612. bit = __ffs(isr);
  613. isr &= ~(1 << bit);
  614. /*
  615. * Some chips can't respond to both rising and falling
  616. * at the same time. If this irq was requested with
  617. * both flags, we need to flip the ICR data for the IRQ
  618. * to respond to the IRQ for the opposite direction.
  619. * This will be indicated in the bank toggle_mask.
  620. */
  621. if (bank->toggle_mask & (1 << bit))
  622. _toggle_gpio_edge_triggering(bank, bit);
  623. generic_handle_irq(irq_find_mapping(bank->domain, bit));
  624. }
  625. }
  626. /* if bank has any level sensitive GPIO pin interrupt
  627. configured, we must unmask the bank interrupt only after
  628. handler(s) are executed in order to avoid spurious bank
  629. interrupt */
  630. exit:
  631. if (!unmasked)
  632. chained_irq_exit(chip, desc);
  633. pm_runtime_put(bank->dev);
  634. }
  635. static void gpio_irq_shutdown(struct irq_data *d)
  636. {
  637. struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
  638. unsigned int gpio = irq_to_gpio(bank, d->hwirq);
  639. unsigned long flags;
  640. spin_lock_irqsave(&bank->lock, flags);
  641. _reset_gpio(bank, gpio);
  642. spin_unlock_irqrestore(&bank->lock, flags);
  643. }
  644. static void gpio_ack_irq(struct irq_data *d)
  645. {
  646. struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
  647. unsigned int gpio = irq_to_gpio(bank, d->hwirq);
  648. _clear_gpio_irqstatus(bank, gpio);
  649. }
  650. static void gpio_mask_irq(struct irq_data *d)
  651. {
  652. struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
  653. unsigned int gpio = irq_to_gpio(bank, d->hwirq);
  654. unsigned long flags;
  655. spin_lock_irqsave(&bank->lock, flags);
  656. _set_gpio_irqenable(bank, gpio, 0);
  657. _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
  658. spin_unlock_irqrestore(&bank->lock, flags);
  659. }
  660. static void gpio_unmask_irq(struct irq_data *d)
  661. {
  662. struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
  663. unsigned int gpio = irq_to_gpio(bank, d->hwirq);
  664. unsigned int irq_mask = GPIO_BIT(bank, gpio);
  665. u32 trigger = irqd_get_trigger_type(d);
  666. unsigned long flags;
  667. spin_lock_irqsave(&bank->lock, flags);
  668. if (trigger)
  669. _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
  670. /* For level-triggered GPIOs, the clearing must be done after
  671. * the HW source is cleared, thus after the handler has run */
  672. if (bank->level_mask & irq_mask) {
  673. _set_gpio_irqenable(bank, gpio, 0);
  674. _clear_gpio_irqstatus(bank, gpio);
  675. }
  676. _set_gpio_irqenable(bank, gpio, 1);
  677. spin_unlock_irqrestore(&bank->lock, flags);
  678. }
  679. static struct irq_chip gpio_irq_chip = {
  680. .name = "GPIO",
  681. .irq_shutdown = gpio_irq_shutdown,
  682. .irq_ack = gpio_ack_irq,
  683. .irq_mask = gpio_mask_irq,
  684. .irq_unmask = gpio_unmask_irq,
  685. .irq_set_type = gpio_irq_type,
  686. .irq_set_wake = gpio_wake_enable,
  687. };
  688. /*---------------------------------------------------------------------*/
  689. static int omap_mpuio_suspend_noirq(struct device *dev)
  690. {
  691. struct platform_device *pdev = to_platform_device(dev);
  692. struct gpio_bank *bank = platform_get_drvdata(pdev);
  693. void __iomem *mask_reg = bank->base +
  694. OMAP_MPUIO_GPIO_MASKIT / bank->stride;
  695. unsigned long flags;
  696. spin_lock_irqsave(&bank->lock, flags);
  697. __raw_writel(0xffff & ~bank->context.wake_en, mask_reg);
  698. spin_unlock_irqrestore(&bank->lock, flags);
  699. return 0;
  700. }
  701. static int omap_mpuio_resume_noirq(struct device *dev)
  702. {
  703. struct platform_device *pdev = to_platform_device(dev);
  704. struct gpio_bank *bank = platform_get_drvdata(pdev);
  705. void __iomem *mask_reg = bank->base +
  706. OMAP_MPUIO_GPIO_MASKIT / bank->stride;
  707. unsigned long flags;
  708. spin_lock_irqsave(&bank->lock, flags);
  709. __raw_writel(bank->context.wake_en, mask_reg);
  710. spin_unlock_irqrestore(&bank->lock, flags);
  711. return 0;
  712. }
  713. static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
  714. .suspend_noirq = omap_mpuio_suspend_noirq,
  715. .resume_noirq = omap_mpuio_resume_noirq,
  716. };
  717. /* use platform_driver for this. */
  718. static struct platform_driver omap_mpuio_driver = {
  719. .driver = {
  720. .name = "mpuio",
  721. .pm = &omap_mpuio_dev_pm_ops,
  722. },
  723. };
  724. static struct platform_device omap_mpuio_device = {
  725. .name = "mpuio",
  726. .id = -1,
  727. .dev = {
  728. .driver = &omap_mpuio_driver.driver,
  729. }
  730. /* could list the /proc/iomem resources */
  731. };
  732. static inline void mpuio_init(struct gpio_bank *bank)
  733. {
  734. platform_set_drvdata(&omap_mpuio_device, bank);
  735. if (platform_driver_register(&omap_mpuio_driver) == 0)
  736. (void) platform_device_register(&omap_mpuio_device);
  737. }
  738. /*---------------------------------------------------------------------*/
  739. static int gpio_input(struct gpio_chip *chip, unsigned offset)
  740. {
  741. struct gpio_bank *bank;
  742. unsigned long flags;
  743. bank = container_of(chip, struct gpio_bank, chip);
  744. spin_lock_irqsave(&bank->lock, flags);
  745. _set_gpio_direction(bank, offset, 1);
  746. spin_unlock_irqrestore(&bank->lock, flags);
  747. return 0;
  748. }
  749. static int gpio_is_input(struct gpio_bank *bank, int mask)
  750. {
  751. void __iomem *reg = bank->base + bank->regs->direction;
  752. return __raw_readl(reg) & mask;
  753. }
  754. static int gpio_get(struct gpio_chip *chip, unsigned offset)
  755. {
  756. struct gpio_bank *bank;
  757. u32 mask;
  758. bank = container_of(chip, struct gpio_bank, chip);
  759. mask = (1 << offset);
  760. if (gpio_is_input(bank, mask))
  761. return _get_gpio_datain(bank, offset);
  762. else
  763. return _get_gpio_dataout(bank, offset);
  764. }
  765. static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
  766. {
  767. struct gpio_bank *bank;
  768. unsigned long flags;
  769. bank = container_of(chip, struct gpio_bank, chip);
  770. spin_lock_irqsave(&bank->lock, flags);
  771. bank->set_dataout(bank, offset, value);
  772. _set_gpio_direction(bank, offset, 0);
  773. spin_unlock_irqrestore(&bank->lock, flags);
  774. return 0;
  775. }
  776. static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
  777. unsigned debounce)
  778. {
  779. struct gpio_bank *bank;
  780. unsigned long flags;
  781. bank = container_of(chip, struct gpio_bank, chip);
  782. spin_lock_irqsave(&bank->lock, flags);
  783. _set_gpio_debounce(bank, offset, debounce);
  784. spin_unlock_irqrestore(&bank->lock, flags);
  785. return 0;
  786. }
  787. static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  788. {
  789. struct gpio_bank *bank;
  790. unsigned long flags;
  791. bank = container_of(chip, struct gpio_bank, chip);
  792. spin_lock_irqsave(&bank->lock, flags);
  793. bank->set_dataout(bank, offset, value);
  794. spin_unlock_irqrestore(&bank->lock, flags);
  795. }
  796. /*---------------------------------------------------------------------*/
  797. static void __init omap_gpio_show_rev(struct gpio_bank *bank)
  798. {
  799. static bool called;
  800. u32 rev;
  801. if (called || bank->regs->revision == USHRT_MAX)
  802. return;
  803. rev = __raw_readw(bank->base + bank->regs->revision);
  804. pr_info("OMAP GPIO hardware version %d.%d\n",
  805. (rev >> 4) & 0x0f, rev & 0x0f);
  806. called = true;
  807. }
  808. /* This lock class tells lockdep that GPIO irqs are in a different
  809. * category than their parents, so it won't report false recursion.
  810. */
  811. static struct lock_class_key gpio_lock_class;
  812. static void omap_gpio_mod_init(struct gpio_bank *bank)
  813. {
  814. void __iomem *base = bank->base;
  815. u32 l = 0xffffffff;
  816. if (bank->width == 16)
  817. l = 0xffff;
  818. if (bank->is_mpuio) {
  819. __raw_writel(l, bank->base + bank->regs->irqenable);
  820. return;
  821. }
  822. _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
  823. _gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv);
  824. if (bank->regs->debounce_en)
  825. __raw_writel(0, base + bank->regs->debounce_en);
  826. /* Save OE default value (0xffffffff) in the context */
  827. bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
  828. /* Initialize interface clk ungated, module enabled */
  829. if (bank->regs->ctrl)
  830. __raw_writel(0, base + bank->regs->ctrl);
  831. bank->dbck = clk_get(bank->dev, "dbclk");
  832. if (IS_ERR(bank->dbck))
  833. dev_err(bank->dev, "Could not get gpio dbck\n");
  834. }
  835. static void
  836. omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
  837. unsigned int num)
  838. {
  839. struct irq_chip_generic *gc;
  840. struct irq_chip_type *ct;
  841. gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
  842. handle_simple_irq);
  843. if (!gc) {
  844. dev_err(bank->dev, "Memory alloc failed for gc\n");
  845. return;
  846. }
  847. ct = gc->chip_types;
  848. /* NOTE: No ack required, reading IRQ status clears it. */
  849. ct->chip.irq_mask = irq_gc_mask_set_bit;
  850. ct->chip.irq_unmask = irq_gc_mask_clr_bit;
  851. ct->chip.irq_set_type = gpio_irq_type;
  852. if (bank->regs->wkup_en)
  853. ct->chip.irq_set_wake = gpio_wake_enable,
  854. ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
  855. irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
  856. IRQ_NOREQUEST | IRQ_NOPROBE, 0);
  857. }
  858. static void omap_gpio_chip_init(struct gpio_bank *bank)
  859. {
  860. int j;
  861. static int gpio;
  862. /*
  863. * REVISIT eventually switch from OMAP-specific gpio structs
  864. * over to the generic ones
  865. */
  866. bank->chip.request = omap_gpio_request;
  867. bank->chip.free = omap_gpio_free;
  868. bank->chip.direction_input = gpio_input;
  869. bank->chip.get = gpio_get;
  870. bank->chip.direction_output = gpio_output;
  871. bank->chip.set_debounce = gpio_debounce;
  872. bank->chip.set = gpio_set;
  873. bank->chip.to_irq = omap_gpio_to_irq;
  874. if (bank->is_mpuio) {
  875. bank->chip.label = "mpuio";
  876. if (bank->regs->wkup_en)
  877. bank->chip.dev = &omap_mpuio_device.dev;
  878. bank->chip.base = OMAP_MPUIO(0);
  879. } else {
  880. bank->chip.label = "gpio";
  881. bank->chip.base = gpio;
  882. gpio += bank->width;
  883. }
  884. bank->chip.ngpio = bank->width;
  885. gpiochip_add(&bank->chip);
  886. for (j = 0; j < bank->width; j++) {
  887. int irq = irq_create_mapping(bank->domain, j);
  888. irq_set_lockdep_class(irq, &gpio_lock_class);
  889. irq_set_chip_data(irq, bank);
  890. if (bank->is_mpuio) {
  891. omap_mpuio_alloc_gc(bank, irq, bank->width);
  892. } else {
  893. irq_set_chip_and_handler(irq, &gpio_irq_chip,
  894. handle_simple_irq);
  895. set_irq_flags(irq, IRQF_VALID);
  896. }
  897. }
  898. irq_set_chained_handler(bank->irq, gpio_irq_handler);
  899. irq_set_handler_data(bank->irq, bank);
  900. }
  901. static const struct of_device_id omap_gpio_match[];
  902. static int omap_gpio_probe(struct platform_device *pdev)
  903. {
  904. struct device *dev = &pdev->dev;
  905. struct device_node *node = dev->of_node;
  906. const struct of_device_id *match;
  907. const struct omap_gpio_platform_data *pdata;
  908. struct resource *res;
  909. struct gpio_bank *bank;
  910. match = of_match_device(of_match_ptr(omap_gpio_match), dev);
  911. pdata = match ? match->data : dev->platform_data;
  912. if (!pdata)
  913. return -EINVAL;
  914. bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
  915. if (!bank) {
  916. dev_err(dev, "Memory alloc failed\n");
  917. return -ENOMEM;
  918. }
  919. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  920. if (unlikely(!res)) {
  921. dev_err(dev, "Invalid IRQ resource\n");
  922. return -ENODEV;
  923. }
  924. bank->irq = res->start;
  925. bank->dev = dev;
  926. bank->dbck_flag = pdata->dbck_flag;
  927. bank->stride = pdata->bank_stride;
  928. bank->width = pdata->bank_width;
  929. bank->is_mpuio = pdata->is_mpuio;
  930. bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
  931. bank->regs = pdata->regs;
  932. #ifdef CONFIG_OF_GPIO
  933. bank->chip.of_node = of_node_get(node);
  934. #endif
  935. if (node) {
  936. if (!of_property_read_bool(node, "ti,gpio-always-on"))
  937. bank->loses_context = true;
  938. } else {
  939. bank->loses_context = pdata->loses_context;
  940. }
  941. bank->domain = irq_domain_add_linear(node, bank->width,
  942. &irq_domain_simple_ops, NULL);
  943. if (!bank->domain)
  944. return -ENODEV;
  945. if (bank->regs->set_dataout && bank->regs->clr_dataout)
  946. bank->set_dataout = _set_gpio_dataout_reg;
  947. else
  948. bank->set_dataout = _set_gpio_dataout_mask;
  949. spin_lock_init(&bank->lock);
  950. /* Static mapping, never released */
  951. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  952. if (unlikely(!res)) {
  953. dev_err(dev, "Invalid mem resource\n");
  954. irq_domain_remove(bank->domain);
  955. return -ENODEV;
  956. }
  957. if (!devm_request_mem_region(dev, res->start, resource_size(res),
  958. pdev->name)) {
  959. dev_err(dev, "Region already claimed\n");
  960. irq_domain_remove(bank->domain);
  961. return -EBUSY;
  962. }
  963. bank->base = devm_ioremap(dev, res->start, resource_size(res));
  964. if (!bank->base) {
  965. dev_err(dev, "Could not ioremap\n");
  966. irq_domain_remove(bank->domain);
  967. return -ENOMEM;
  968. }
  969. platform_set_drvdata(pdev, bank);
  970. pm_runtime_enable(bank->dev);
  971. pm_runtime_irq_safe(bank->dev);
  972. pm_runtime_get_sync(bank->dev);
  973. if (bank->is_mpuio)
  974. mpuio_init(bank);
  975. omap_gpio_mod_init(bank);
  976. omap_gpio_chip_init(bank);
  977. omap_gpio_show_rev(bank);
  978. if (bank->loses_context)
  979. bank->get_context_loss_count = pdata->get_context_loss_count;
  980. pm_runtime_put(bank->dev);
  981. list_add_tail(&bank->node, &omap_gpio_list);
  982. return 0;
  983. }
  984. #ifdef CONFIG_ARCH_OMAP2PLUS
  985. #if defined(CONFIG_PM_RUNTIME)
  986. static void omap_gpio_restore_context(struct gpio_bank *bank);
  987. static int omap_gpio_runtime_suspend(struct device *dev)
  988. {
  989. struct platform_device *pdev = to_platform_device(dev);
  990. struct gpio_bank *bank = platform_get_drvdata(pdev);
  991. u32 l1 = 0, l2 = 0;
  992. unsigned long flags;
  993. u32 wake_low, wake_hi;
  994. spin_lock_irqsave(&bank->lock, flags);
  995. /*
  996. * Only edges can generate a wakeup event to the PRCM.
  997. *
  998. * Therefore, ensure any wake-up capable GPIOs have
  999. * edge-detection enabled before going idle to ensure a wakeup
  1000. * to the PRCM is generated on a GPIO transition. (c.f. 34xx
  1001. * NDA TRM 25.5.3.1)
  1002. *
  1003. * The normal values will be restored upon ->runtime_resume()
  1004. * by writing back the values saved in bank->context.
  1005. */
  1006. wake_low = bank->context.leveldetect0 & bank->context.wake_en;
  1007. if (wake_low)
  1008. __raw_writel(wake_low | bank->context.fallingdetect,
  1009. bank->base + bank->regs->fallingdetect);
  1010. wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
  1011. if (wake_hi)
  1012. __raw_writel(wake_hi | bank->context.risingdetect,
  1013. bank->base + bank->regs->risingdetect);
  1014. if (!bank->enabled_non_wakeup_gpios)
  1015. goto update_gpio_context_count;
  1016. if (bank->power_mode != OFF_MODE) {
  1017. bank->power_mode = 0;
  1018. goto update_gpio_context_count;
  1019. }
  1020. /*
  1021. * If going to OFF, remove triggering for all
  1022. * non-wakeup GPIOs. Otherwise spurious IRQs will be
  1023. * generated. See OMAP2420 Errata item 1.101.
  1024. */
  1025. bank->saved_datain = __raw_readl(bank->base +
  1026. bank->regs->datain);
  1027. l1 = bank->context.fallingdetect;
  1028. l2 = bank->context.risingdetect;
  1029. l1 &= ~bank->enabled_non_wakeup_gpios;
  1030. l2 &= ~bank->enabled_non_wakeup_gpios;
  1031. __raw_writel(l1, bank->base + bank->regs->fallingdetect);
  1032. __raw_writel(l2, bank->base + bank->regs->risingdetect);
  1033. bank->workaround_enabled = true;
  1034. update_gpio_context_count:
  1035. if (bank->get_context_loss_count)
  1036. bank->context_loss_count =
  1037. bank->get_context_loss_count(bank->dev);
  1038. _gpio_dbck_disable(bank);
  1039. spin_unlock_irqrestore(&bank->lock, flags);
  1040. return 0;
  1041. }
  1042. static int omap_gpio_runtime_resume(struct device *dev)
  1043. {
  1044. struct platform_device *pdev = to_platform_device(dev);
  1045. struct gpio_bank *bank = platform_get_drvdata(pdev);
  1046. u32 l = 0, gen, gen0, gen1;
  1047. unsigned long flags;
  1048. int c;
  1049. spin_lock_irqsave(&bank->lock, flags);
  1050. _gpio_dbck_enable(bank);
  1051. /*
  1052. * In ->runtime_suspend(), level-triggered, wakeup-enabled
  1053. * GPIOs were set to edge trigger also in order to be able to
  1054. * generate a PRCM wakeup. Here we restore the
  1055. * pre-runtime_suspend() values for edge triggering.
  1056. */
  1057. __raw_writel(bank->context.fallingdetect,
  1058. bank->base + bank->regs->fallingdetect);
  1059. __raw_writel(bank->context.risingdetect,
  1060. bank->base + bank->regs->risingdetect);
  1061. if (bank->loses_context) {
  1062. if (!bank->get_context_loss_count) {
  1063. omap_gpio_restore_context(bank);
  1064. } else {
  1065. c = bank->get_context_loss_count(bank->dev);
  1066. if (c != bank->context_loss_count) {
  1067. omap_gpio_restore_context(bank);
  1068. } else {
  1069. spin_unlock_irqrestore(&bank->lock, flags);
  1070. return 0;
  1071. }
  1072. }
  1073. }
  1074. if (!bank->workaround_enabled) {
  1075. spin_unlock_irqrestore(&bank->lock, flags);
  1076. return 0;
  1077. }
  1078. l = __raw_readl(bank->base + bank->regs->datain);
  1079. /*
  1080. * Check if any of the non-wakeup interrupt GPIOs have changed
  1081. * state. If so, generate an IRQ by software. This is
  1082. * horribly racy, but it's the best we can do to work around
  1083. * this silicon bug.
  1084. */
  1085. l ^= bank->saved_datain;
  1086. l &= bank->enabled_non_wakeup_gpios;
  1087. /*
  1088. * No need to generate IRQs for the rising edge for gpio IRQs
  1089. * configured with falling edge only; and vice versa.
  1090. */
  1091. gen0 = l & bank->context.fallingdetect;
  1092. gen0 &= bank->saved_datain;
  1093. gen1 = l & bank->context.risingdetect;
  1094. gen1 &= ~(bank->saved_datain);
  1095. /* FIXME: Consider GPIO IRQs with level detections properly! */
  1096. gen = l & (~(bank->context.fallingdetect) &
  1097. ~(bank->context.risingdetect));
  1098. /* Consider all GPIO IRQs needed to be updated */
  1099. gen |= gen0 | gen1;
  1100. if (gen) {
  1101. u32 old0, old1;
  1102. old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
  1103. old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
  1104. if (!bank->regs->irqstatus_raw0) {
  1105. __raw_writel(old0 | gen, bank->base +
  1106. bank->regs->leveldetect0);
  1107. __raw_writel(old1 | gen, bank->base +
  1108. bank->regs->leveldetect1);
  1109. }
  1110. if (bank->regs->irqstatus_raw0) {
  1111. __raw_writel(old0 | l, bank->base +
  1112. bank->regs->leveldetect0);
  1113. __raw_writel(old1 | l, bank->base +
  1114. bank->regs->leveldetect1);
  1115. }
  1116. __raw_writel(old0, bank->base + bank->regs->leveldetect0);
  1117. __raw_writel(old1, bank->base + bank->regs->leveldetect1);
  1118. }
  1119. bank->workaround_enabled = false;
  1120. spin_unlock_irqrestore(&bank->lock, flags);
  1121. return 0;
  1122. }
  1123. #endif /* CONFIG_PM_RUNTIME */
  1124. void omap2_gpio_prepare_for_idle(int pwr_mode)
  1125. {
  1126. struct gpio_bank *bank;
  1127. list_for_each_entry(bank, &omap_gpio_list, node) {
  1128. if (!bank->mod_usage || !bank->loses_context)
  1129. continue;
  1130. bank->power_mode = pwr_mode;
  1131. pm_runtime_put_sync_suspend(bank->dev);
  1132. }
  1133. }
  1134. void omap2_gpio_resume_after_idle(void)
  1135. {
  1136. struct gpio_bank *bank;
  1137. list_for_each_entry(bank, &omap_gpio_list, node) {
  1138. if (!bank->mod_usage || !bank->loses_context)
  1139. continue;
  1140. pm_runtime_get_sync(bank->dev);
  1141. }
  1142. }
  1143. #if defined(CONFIG_PM_RUNTIME)
  1144. static void omap_gpio_restore_context(struct gpio_bank *bank)
  1145. {
  1146. __raw_writel(bank->context.wake_en,
  1147. bank->base + bank->regs->wkup_en);
  1148. __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
  1149. __raw_writel(bank->context.leveldetect0,
  1150. bank->base + bank->regs->leveldetect0);
  1151. __raw_writel(bank->context.leveldetect1,
  1152. bank->base + bank->regs->leveldetect1);
  1153. __raw_writel(bank->context.risingdetect,
  1154. bank->base + bank->regs->risingdetect);
  1155. __raw_writel(bank->context.fallingdetect,
  1156. bank->base + bank->regs->fallingdetect);
  1157. if (bank->regs->set_dataout && bank->regs->clr_dataout)
  1158. __raw_writel(bank->context.dataout,
  1159. bank->base + bank->regs->set_dataout);
  1160. else
  1161. __raw_writel(bank->context.dataout,
  1162. bank->base + bank->regs->dataout);
  1163. __raw_writel(bank->context.oe, bank->base + bank->regs->direction);
  1164. if (bank->dbck_enable_mask) {
  1165. __raw_writel(bank->context.debounce, bank->base +
  1166. bank->regs->debounce);
  1167. __raw_writel(bank->context.debounce_en,
  1168. bank->base + bank->regs->debounce_en);
  1169. }
  1170. __raw_writel(bank->context.irqenable1,
  1171. bank->base + bank->regs->irqenable);
  1172. __raw_writel(bank->context.irqenable2,
  1173. bank->base + bank->regs->irqenable2);
  1174. }
  1175. #endif /* CONFIG_PM_RUNTIME */
  1176. #else
  1177. #define omap_gpio_runtime_suspend NULL
  1178. #define omap_gpio_runtime_resume NULL
  1179. #endif
  1180. static const struct dev_pm_ops gpio_pm_ops = {
  1181. SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
  1182. NULL)
  1183. };
  1184. #if defined(CONFIG_OF)
  1185. static struct omap_gpio_reg_offs omap2_gpio_regs = {
  1186. .revision = OMAP24XX_GPIO_REVISION,
  1187. .direction = OMAP24XX_GPIO_OE,
  1188. .datain = OMAP24XX_GPIO_DATAIN,
  1189. .dataout = OMAP24XX_GPIO_DATAOUT,
  1190. .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
  1191. .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
  1192. .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
  1193. .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
  1194. .irqenable = OMAP24XX_GPIO_IRQENABLE1,
  1195. .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
  1196. .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
  1197. .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
  1198. .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
  1199. .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
  1200. .ctrl = OMAP24XX_GPIO_CTRL,
  1201. .wkup_en = OMAP24XX_GPIO_WAKE_EN,
  1202. .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
  1203. .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
  1204. .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
  1205. .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
  1206. };
  1207. static struct omap_gpio_reg_offs omap4_gpio_regs = {
  1208. .revision = OMAP4_GPIO_REVISION,
  1209. .direction = OMAP4_GPIO_OE,
  1210. .datain = OMAP4_GPIO_DATAIN,
  1211. .dataout = OMAP4_GPIO_DATAOUT,
  1212. .set_dataout = OMAP4_GPIO_SETDATAOUT,
  1213. .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
  1214. .irqstatus = OMAP4_GPIO_IRQSTATUS0,
  1215. .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
  1216. .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
  1217. .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
  1218. .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
  1219. .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
  1220. .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
  1221. .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
  1222. .ctrl = OMAP4_GPIO_CTRL,
  1223. .wkup_en = OMAP4_GPIO_IRQWAKEN0,
  1224. .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
  1225. .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
  1226. .risingdetect = OMAP4_GPIO_RISINGDETECT,
  1227. .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
  1228. };
  1229. static const struct omap_gpio_platform_data omap2_pdata = {
  1230. .regs = &omap2_gpio_regs,
  1231. .bank_width = 32,
  1232. .dbck_flag = false,
  1233. };
  1234. static const struct omap_gpio_platform_data omap3_pdata = {
  1235. .regs = &omap2_gpio_regs,
  1236. .bank_width = 32,
  1237. .dbck_flag = true,
  1238. };
  1239. static const struct omap_gpio_platform_data omap4_pdata = {
  1240. .regs = &omap4_gpio_regs,
  1241. .bank_width = 32,
  1242. .dbck_flag = true,
  1243. };
  1244. static const struct of_device_id omap_gpio_match[] = {
  1245. {
  1246. .compatible = "ti,omap4-gpio",
  1247. .data = &omap4_pdata,
  1248. },
  1249. {
  1250. .compatible = "ti,omap3-gpio",
  1251. .data = &omap3_pdata,
  1252. },
  1253. {
  1254. .compatible = "ti,omap2-gpio",
  1255. .data = &omap2_pdata,
  1256. },
  1257. { },
  1258. };
  1259. MODULE_DEVICE_TABLE(of, omap_gpio_match);
  1260. #endif
  1261. static struct platform_driver omap_gpio_driver = {
  1262. .probe = omap_gpio_probe,
  1263. .driver = {
  1264. .name = "omap_gpio",
  1265. .pm = &gpio_pm_ops,
  1266. .of_match_table = of_match_ptr(omap_gpio_match),
  1267. },
  1268. };
  1269. /*
  1270. * gpio driver register needs to be done before
  1271. * machine_init functions access gpio APIs.
  1272. * Hence omap_gpio_drv_reg() is a postcore_initcall.
  1273. */
  1274. static int __init omap_gpio_drv_reg(void)
  1275. {
  1276. return platform_driver_register(&omap_gpio_driver);
  1277. }
  1278. postcore_initcall(omap_gpio_drv_reg);