tegra-cpufreq.c 6.6 KB

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  1. /*
  2. * Copyright (C) 2010 Google, Inc.
  3. *
  4. * Author:
  5. * Colin Cross <ccross@google.com>
  6. * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
  7. *
  8. * This software is licensed under the terms of the GNU General Public
  9. * License version 2, as published by the Free Software Foundation, and
  10. * may be copied, distributed, and modified under those terms.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/types.h>
  21. #include <linux/sched.h>
  22. #include <linux/cpufreq.h>
  23. #include <linux/delay.h>
  24. #include <linux/init.h>
  25. #include <linux/err.h>
  26. #include <linux/clk.h>
  27. #include <linux/io.h>
  28. #include <linux/suspend.h>
  29. /* Frequency table index must be sequential starting at 0 */
  30. static struct cpufreq_frequency_table freq_table[] = {
  31. { 0, 216000 },
  32. { 1, 312000 },
  33. { 2, 456000 },
  34. { 3, 608000 },
  35. { 4, 760000 },
  36. { 5, 816000 },
  37. { 6, 912000 },
  38. { 7, 1000000 },
  39. { 8, CPUFREQ_TABLE_END },
  40. };
  41. #define NUM_CPUS 2
  42. static struct clk *cpu_clk;
  43. static struct clk *pll_x_clk;
  44. static struct clk *pll_p_clk;
  45. static struct clk *emc_clk;
  46. static unsigned long target_cpu_speed[NUM_CPUS];
  47. static DEFINE_MUTEX(tegra_cpu_lock);
  48. static bool is_suspended;
  49. static int tegra_verify_speed(struct cpufreq_policy *policy)
  50. {
  51. return cpufreq_frequency_table_verify(policy, freq_table);
  52. }
  53. static unsigned int tegra_getspeed(unsigned int cpu)
  54. {
  55. unsigned long rate;
  56. if (cpu >= NUM_CPUS)
  57. return 0;
  58. rate = clk_get_rate(cpu_clk) / 1000;
  59. return rate;
  60. }
  61. static int tegra_cpu_clk_set_rate(unsigned long rate)
  62. {
  63. int ret;
  64. /*
  65. * Take an extra reference to the main pll so it doesn't turn
  66. * off when we move the cpu off of it
  67. */
  68. clk_prepare_enable(pll_x_clk);
  69. ret = clk_set_parent(cpu_clk, pll_p_clk);
  70. if (ret) {
  71. pr_err("Failed to switch cpu to clock pll_p\n");
  72. goto out;
  73. }
  74. if (rate == clk_get_rate(pll_p_clk))
  75. goto out;
  76. ret = clk_set_rate(pll_x_clk, rate);
  77. if (ret) {
  78. pr_err("Failed to change pll_x to %lu\n", rate);
  79. goto out;
  80. }
  81. ret = clk_set_parent(cpu_clk, pll_x_clk);
  82. if (ret) {
  83. pr_err("Failed to switch cpu to clock pll_x\n");
  84. goto out;
  85. }
  86. out:
  87. clk_disable_unprepare(pll_x_clk);
  88. return ret;
  89. }
  90. static int tegra_update_cpu_speed(struct cpufreq_policy *policy,
  91. unsigned long rate)
  92. {
  93. int ret = 0;
  94. struct cpufreq_freqs freqs;
  95. freqs.old = tegra_getspeed(0);
  96. freqs.new = rate;
  97. if (freqs.old == freqs.new)
  98. return ret;
  99. /*
  100. * Vote on memory bus frequency based on cpu frequency
  101. * This sets the minimum frequency, display or avp may request higher
  102. */
  103. if (rate >= 816000)
  104. clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
  105. else if (rate >= 456000)
  106. clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
  107. else
  108. clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */
  109. cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
  110. #ifdef CONFIG_CPU_FREQ_DEBUG
  111. printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n",
  112. freqs.old, freqs.new);
  113. #endif
  114. ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
  115. if (ret) {
  116. pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
  117. freqs.new);
  118. return ret;
  119. }
  120. cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
  121. return 0;
  122. }
  123. static unsigned long tegra_cpu_highest_speed(void)
  124. {
  125. unsigned long rate = 0;
  126. int i;
  127. for_each_online_cpu(i)
  128. rate = max(rate, target_cpu_speed[i]);
  129. return rate;
  130. }
  131. static int tegra_target(struct cpufreq_policy *policy,
  132. unsigned int target_freq,
  133. unsigned int relation)
  134. {
  135. unsigned int idx;
  136. unsigned int freq;
  137. int ret = 0;
  138. mutex_lock(&tegra_cpu_lock);
  139. if (is_suspended) {
  140. ret = -EBUSY;
  141. goto out;
  142. }
  143. cpufreq_frequency_table_target(policy, freq_table, target_freq,
  144. relation, &idx);
  145. freq = freq_table[idx].frequency;
  146. target_cpu_speed[policy->cpu] = freq;
  147. ret = tegra_update_cpu_speed(policy, tegra_cpu_highest_speed());
  148. out:
  149. mutex_unlock(&tegra_cpu_lock);
  150. return ret;
  151. }
  152. static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
  153. void *dummy)
  154. {
  155. mutex_lock(&tegra_cpu_lock);
  156. if (event == PM_SUSPEND_PREPARE) {
  157. struct cpufreq_policy *policy = cpufreq_cpu_get(0);
  158. is_suspended = true;
  159. pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n",
  160. freq_table[0].frequency);
  161. tegra_update_cpu_speed(policy, freq_table[0].frequency);
  162. cpufreq_cpu_put(policy);
  163. } else if (event == PM_POST_SUSPEND) {
  164. is_suspended = false;
  165. }
  166. mutex_unlock(&tegra_cpu_lock);
  167. return NOTIFY_OK;
  168. }
  169. static struct notifier_block tegra_cpu_pm_notifier = {
  170. .notifier_call = tegra_pm_notify,
  171. };
  172. static int tegra_cpu_init(struct cpufreq_policy *policy)
  173. {
  174. if (policy->cpu >= NUM_CPUS)
  175. return -EINVAL;
  176. clk_prepare_enable(emc_clk);
  177. clk_prepare_enable(cpu_clk);
  178. cpufreq_frequency_table_cpuinfo(policy, freq_table);
  179. cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
  180. policy->cur = tegra_getspeed(policy->cpu);
  181. target_cpu_speed[policy->cpu] = policy->cur;
  182. /* FIXME: what's the actual transition time? */
  183. policy->cpuinfo.transition_latency = 300 * 1000;
  184. cpumask_copy(policy->cpus, cpu_possible_mask);
  185. if (policy->cpu == 0)
  186. register_pm_notifier(&tegra_cpu_pm_notifier);
  187. return 0;
  188. }
  189. static int tegra_cpu_exit(struct cpufreq_policy *policy)
  190. {
  191. cpufreq_frequency_table_cpuinfo(policy, freq_table);
  192. clk_disable_unprepare(emc_clk);
  193. return 0;
  194. }
  195. static struct freq_attr *tegra_cpufreq_attr[] = {
  196. &cpufreq_freq_attr_scaling_available_freqs,
  197. NULL,
  198. };
  199. static struct cpufreq_driver tegra_cpufreq_driver = {
  200. .verify = tegra_verify_speed,
  201. .target = tegra_target,
  202. .get = tegra_getspeed,
  203. .init = tegra_cpu_init,
  204. .exit = tegra_cpu_exit,
  205. .name = "tegra",
  206. .attr = tegra_cpufreq_attr,
  207. };
  208. static int __init tegra_cpufreq_init(void)
  209. {
  210. cpu_clk = clk_get_sys(NULL, "cpu");
  211. if (IS_ERR(cpu_clk))
  212. return PTR_ERR(cpu_clk);
  213. pll_x_clk = clk_get_sys(NULL, "pll_x");
  214. if (IS_ERR(pll_x_clk))
  215. return PTR_ERR(pll_x_clk);
  216. pll_p_clk = clk_get_sys(NULL, "pll_p_cclk");
  217. if (IS_ERR(pll_p_clk))
  218. return PTR_ERR(pll_p_clk);
  219. emc_clk = clk_get_sys("cpu", "emc");
  220. if (IS_ERR(emc_clk)) {
  221. clk_put(cpu_clk);
  222. return PTR_ERR(emc_clk);
  223. }
  224. return cpufreq_register_driver(&tegra_cpufreq_driver);
  225. }
  226. static void __exit tegra_cpufreq_exit(void)
  227. {
  228. cpufreq_unregister_driver(&tegra_cpufreq_driver);
  229. clk_put(emc_clk);
  230. clk_put(cpu_clk);
  231. }
  232. MODULE_AUTHOR("Colin Cross <ccross@android.com>");
  233. MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
  234. MODULE_LICENSE("GPL");
  235. module_init(tegra_cpufreq_init);
  236. module_exit(tegra_cpufreq_exit);