nvme-scsi.c 84 KB

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  1. /*
  2. * NVM Express device driver
  3. * Copyright (c) 2011, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17. */
  18. /*
  19. * Refer to the SCSI-NVMe Translation spec for details on how
  20. * each command is translated.
  21. */
  22. #include <linux/nvme.h>
  23. #include <linux/bio.h>
  24. #include <linux/bitops.h>
  25. #include <linux/blkdev.h>
  26. #include <linux/delay.h>
  27. #include <linux/errno.h>
  28. #include <linux/fs.h>
  29. #include <linux/genhd.h>
  30. #include <linux/idr.h>
  31. #include <linux/init.h>
  32. #include <linux/interrupt.h>
  33. #include <linux/io.h>
  34. #include <linux/kdev_t.h>
  35. #include <linux/kthread.h>
  36. #include <linux/kernel.h>
  37. #include <linux/mm.h>
  38. #include <linux/module.h>
  39. #include <linux/moduleparam.h>
  40. #include <linux/pci.h>
  41. #include <linux/poison.h>
  42. #include <linux/sched.h>
  43. #include <linux/slab.h>
  44. #include <linux/types.h>
  45. #include <linux/version.h>
  46. #include <scsi/sg.h>
  47. #include <scsi/scsi.h>
  48. static int sg_version_num = 30534; /* 2 digits for each component */
  49. #define SNTI_TRANSLATION_SUCCESS 0
  50. #define SNTI_INTERNAL_ERROR 1
  51. /* VPD Page Codes */
  52. #define VPD_SUPPORTED_PAGES 0x00
  53. #define VPD_SERIAL_NUMBER 0x80
  54. #define VPD_DEVICE_IDENTIFIERS 0x83
  55. #define VPD_EXTENDED_INQUIRY 0x86
  56. #define VPD_BLOCK_DEV_CHARACTERISTICS 0xB1
  57. /* CDB offsets */
  58. #define REPORT_LUNS_CDB_ALLOC_LENGTH_OFFSET 6
  59. #define REPORT_LUNS_SR_OFFSET 2
  60. #define READ_CAP_16_CDB_ALLOC_LENGTH_OFFSET 10
  61. #define REQUEST_SENSE_CDB_ALLOC_LENGTH_OFFSET 4
  62. #define REQUEST_SENSE_DESC_OFFSET 1
  63. #define REQUEST_SENSE_DESC_MASK 0x01
  64. #define DESCRIPTOR_FORMAT_SENSE_DATA_TYPE 1
  65. #define INQUIRY_EVPD_BYTE_OFFSET 1
  66. #define INQUIRY_PAGE_CODE_BYTE_OFFSET 2
  67. #define INQUIRY_EVPD_BIT_MASK 1
  68. #define INQUIRY_CDB_ALLOCATION_LENGTH_OFFSET 3
  69. #define START_STOP_UNIT_CDB_IMMED_OFFSET 1
  70. #define START_STOP_UNIT_CDB_IMMED_MASK 0x1
  71. #define START_STOP_UNIT_CDB_POWER_COND_MOD_OFFSET 3
  72. #define START_STOP_UNIT_CDB_POWER_COND_MOD_MASK 0xF
  73. #define START_STOP_UNIT_CDB_POWER_COND_OFFSET 4
  74. #define START_STOP_UNIT_CDB_POWER_COND_MASK 0xF0
  75. #define START_STOP_UNIT_CDB_NO_FLUSH_OFFSET 4
  76. #define START_STOP_UNIT_CDB_NO_FLUSH_MASK 0x4
  77. #define START_STOP_UNIT_CDB_START_OFFSET 4
  78. #define START_STOP_UNIT_CDB_START_MASK 0x1
  79. #define WRITE_BUFFER_CDB_MODE_OFFSET 1
  80. #define WRITE_BUFFER_CDB_MODE_MASK 0x1F
  81. #define WRITE_BUFFER_CDB_BUFFER_ID_OFFSET 2
  82. #define WRITE_BUFFER_CDB_BUFFER_OFFSET_OFFSET 3
  83. #define WRITE_BUFFER_CDB_PARM_LIST_LENGTH_OFFSET 6
  84. #define FORMAT_UNIT_CDB_FORMAT_PROT_INFO_OFFSET 1
  85. #define FORMAT_UNIT_CDB_FORMAT_PROT_INFO_MASK 0xC0
  86. #define FORMAT_UNIT_CDB_FORMAT_PROT_INFO_SHIFT 6
  87. #define FORMAT_UNIT_CDB_LONG_LIST_OFFSET 1
  88. #define FORMAT_UNIT_CDB_LONG_LIST_MASK 0x20
  89. #define FORMAT_UNIT_CDB_FORMAT_DATA_OFFSET 1
  90. #define FORMAT_UNIT_CDB_FORMAT_DATA_MASK 0x10
  91. #define FORMAT_UNIT_SHORT_PARM_LIST_LEN 4
  92. #define FORMAT_UNIT_LONG_PARM_LIST_LEN 8
  93. #define FORMAT_UNIT_PROT_INT_OFFSET 3
  94. #define FORMAT_UNIT_PROT_FIELD_USAGE_OFFSET 0
  95. #define FORMAT_UNIT_PROT_FIELD_USAGE_MASK 0x07
  96. #define UNMAP_CDB_PARAM_LIST_LENGTH_OFFSET 7
  97. /* Misc. defines */
  98. #define NIBBLE_SHIFT 4
  99. #define FIXED_SENSE_DATA 0x70
  100. #define DESC_FORMAT_SENSE_DATA 0x72
  101. #define FIXED_SENSE_DATA_ADD_LENGTH 10
  102. #define LUN_ENTRY_SIZE 8
  103. #define LUN_DATA_HEADER_SIZE 8
  104. #define ALL_LUNS_RETURNED 0x02
  105. #define ALL_WELL_KNOWN_LUNS_RETURNED 0x01
  106. #define RESTRICTED_LUNS_RETURNED 0x00
  107. #define NVME_POWER_STATE_START_VALID 0x00
  108. #define NVME_POWER_STATE_ACTIVE 0x01
  109. #define NVME_POWER_STATE_IDLE 0x02
  110. #define NVME_POWER_STATE_STANDBY 0x03
  111. #define NVME_POWER_STATE_LU_CONTROL 0x07
  112. #define POWER_STATE_0 0
  113. #define POWER_STATE_1 1
  114. #define POWER_STATE_2 2
  115. #define POWER_STATE_3 3
  116. #define DOWNLOAD_SAVE_ACTIVATE 0x05
  117. #define DOWNLOAD_SAVE_DEFER_ACTIVATE 0x0E
  118. #define ACTIVATE_DEFERRED_MICROCODE 0x0F
  119. #define FORMAT_UNIT_IMMED_MASK 0x2
  120. #define FORMAT_UNIT_IMMED_OFFSET 1
  121. #define KELVIN_TEMP_FACTOR 273
  122. #define FIXED_FMT_SENSE_DATA_SIZE 18
  123. #define DESC_FMT_SENSE_DATA_SIZE 8
  124. /* SCSI/NVMe defines and bit masks */
  125. #define INQ_STANDARD_INQUIRY_PAGE 0x00
  126. #define INQ_SUPPORTED_VPD_PAGES_PAGE 0x00
  127. #define INQ_UNIT_SERIAL_NUMBER_PAGE 0x80
  128. #define INQ_DEVICE_IDENTIFICATION_PAGE 0x83
  129. #define INQ_EXTENDED_INQUIRY_DATA_PAGE 0x86
  130. #define INQ_BDEV_CHARACTERISTICS_PAGE 0xB1
  131. #define INQ_SERIAL_NUMBER_LENGTH 0x14
  132. #define INQ_NUM_SUPPORTED_VPD_PAGES 5
  133. #define VERSION_SPC_4 0x06
  134. #define ACA_UNSUPPORTED 0
  135. #define STANDARD_INQUIRY_LENGTH 36
  136. #define ADDITIONAL_STD_INQ_LENGTH 31
  137. #define EXTENDED_INQUIRY_DATA_PAGE_LENGTH 0x3C
  138. #define RESERVED_FIELD 0
  139. /* SCSI READ/WRITE Defines */
  140. #define IO_CDB_WP_MASK 0xE0
  141. #define IO_CDB_WP_SHIFT 5
  142. #define IO_CDB_FUA_MASK 0x8
  143. #define IO_6_CDB_LBA_OFFSET 0
  144. #define IO_6_CDB_LBA_MASK 0x001FFFFF
  145. #define IO_6_CDB_TX_LEN_OFFSET 4
  146. #define IO_6_DEFAULT_TX_LEN 256
  147. #define IO_10_CDB_LBA_OFFSET 2
  148. #define IO_10_CDB_TX_LEN_OFFSET 7
  149. #define IO_10_CDB_WP_OFFSET 1
  150. #define IO_10_CDB_FUA_OFFSET 1
  151. #define IO_12_CDB_LBA_OFFSET 2
  152. #define IO_12_CDB_TX_LEN_OFFSET 6
  153. #define IO_12_CDB_WP_OFFSET 1
  154. #define IO_12_CDB_FUA_OFFSET 1
  155. #define IO_16_CDB_FUA_OFFSET 1
  156. #define IO_16_CDB_WP_OFFSET 1
  157. #define IO_16_CDB_LBA_OFFSET 2
  158. #define IO_16_CDB_TX_LEN_OFFSET 10
  159. /* Mode Sense/Select defines */
  160. #define MODE_PAGE_INFO_EXCEP 0x1C
  161. #define MODE_PAGE_CACHING 0x08
  162. #define MODE_PAGE_CONTROL 0x0A
  163. #define MODE_PAGE_POWER_CONDITION 0x1A
  164. #define MODE_PAGE_RETURN_ALL 0x3F
  165. #define MODE_PAGE_BLK_DES_LEN 0x08
  166. #define MODE_PAGE_LLBAA_BLK_DES_LEN 0x10
  167. #define MODE_PAGE_CACHING_LEN 0x14
  168. #define MODE_PAGE_CONTROL_LEN 0x0C
  169. #define MODE_PAGE_POW_CND_LEN 0x28
  170. #define MODE_PAGE_INF_EXC_LEN 0x0C
  171. #define MODE_PAGE_ALL_LEN 0x54
  172. #define MODE_SENSE6_MPH_SIZE 4
  173. #define MODE_SENSE6_ALLOC_LEN_OFFSET 4
  174. #define MODE_SENSE_PAGE_CONTROL_OFFSET 2
  175. #define MODE_SENSE_PAGE_CONTROL_MASK 0xC0
  176. #define MODE_SENSE_PAGE_CODE_OFFSET 2
  177. #define MODE_SENSE_PAGE_CODE_MASK 0x3F
  178. #define MODE_SENSE_LLBAA_OFFSET 1
  179. #define MODE_SENSE_LLBAA_MASK 0x10
  180. #define MODE_SENSE_LLBAA_SHIFT 4
  181. #define MODE_SENSE_DBD_OFFSET 1
  182. #define MODE_SENSE_DBD_MASK 8
  183. #define MODE_SENSE_DBD_SHIFT 3
  184. #define MODE_SENSE10_MPH_SIZE 8
  185. #define MODE_SENSE10_ALLOC_LEN_OFFSET 7
  186. #define MODE_SELECT_CDB_PAGE_FORMAT_OFFSET 1
  187. #define MODE_SELECT_CDB_SAVE_PAGES_OFFSET 1
  188. #define MODE_SELECT_6_CDB_PARAM_LIST_LENGTH_OFFSET 4
  189. #define MODE_SELECT_10_CDB_PARAM_LIST_LENGTH_OFFSET 7
  190. #define MODE_SELECT_CDB_PAGE_FORMAT_MASK 0x10
  191. #define MODE_SELECT_CDB_SAVE_PAGES_MASK 0x1
  192. #define MODE_SELECT_6_BD_OFFSET 3
  193. #define MODE_SELECT_10_BD_OFFSET 6
  194. #define MODE_SELECT_10_LLBAA_OFFSET 4
  195. #define MODE_SELECT_10_LLBAA_MASK 1
  196. #define MODE_SELECT_6_MPH_SIZE 4
  197. #define MODE_SELECT_10_MPH_SIZE 8
  198. #define CACHING_MODE_PAGE_WCE_MASK 0x04
  199. #define MODE_SENSE_BLK_DESC_ENABLED 0
  200. #define MODE_SENSE_BLK_DESC_COUNT 1
  201. #define MODE_SELECT_PAGE_CODE_MASK 0x3F
  202. #define SHORT_DESC_BLOCK 8
  203. #define LONG_DESC_BLOCK 16
  204. #define MODE_PAGE_POW_CND_LEN_FIELD 0x26
  205. #define MODE_PAGE_INF_EXC_LEN_FIELD 0x0A
  206. #define MODE_PAGE_CACHING_LEN_FIELD 0x12
  207. #define MODE_PAGE_CONTROL_LEN_FIELD 0x0A
  208. #define MODE_SENSE_PC_CURRENT_VALUES 0
  209. /* Log Sense defines */
  210. #define LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE 0x00
  211. #define LOG_PAGE_SUPPORTED_LOG_PAGES_LENGTH 0x07
  212. #define LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE 0x2F
  213. #define LOG_PAGE_TEMPERATURE_PAGE 0x0D
  214. #define LOG_SENSE_CDB_SP_OFFSET 1
  215. #define LOG_SENSE_CDB_SP_NOT_ENABLED 0
  216. #define LOG_SENSE_CDB_PC_OFFSET 2
  217. #define LOG_SENSE_CDB_PC_MASK 0xC0
  218. #define LOG_SENSE_CDB_PC_SHIFT 6
  219. #define LOG_SENSE_CDB_PC_CUMULATIVE_VALUES 1
  220. #define LOG_SENSE_CDB_PAGE_CODE_MASK 0x3F
  221. #define LOG_SENSE_CDB_ALLOC_LENGTH_OFFSET 7
  222. #define REMAINING_INFO_EXCP_PAGE_LENGTH 0x8
  223. #define LOG_INFO_EXCP_PAGE_LENGTH 0xC
  224. #define REMAINING_TEMP_PAGE_LENGTH 0xC
  225. #define LOG_TEMP_PAGE_LENGTH 0x10
  226. #define LOG_TEMP_UNKNOWN 0xFF
  227. #define SUPPORTED_LOG_PAGES_PAGE_LENGTH 0x3
  228. /* Read Capacity defines */
  229. #define READ_CAP_10_RESP_SIZE 8
  230. #define READ_CAP_16_RESP_SIZE 32
  231. /* NVMe Namespace and Command Defines */
  232. #define NVME_GET_SMART_LOG_PAGE 0x02
  233. #define NVME_GET_FEAT_TEMP_THRESH 0x04
  234. #define BYTES_TO_DWORDS 4
  235. #define NVME_MAX_FIRMWARE_SLOT 7
  236. /* Report LUNs defines */
  237. #define REPORT_LUNS_FIRST_LUN_OFFSET 8
  238. /* SCSI ADDITIONAL SENSE Codes */
  239. #define SCSI_ASC_NO_SENSE 0x00
  240. #define SCSI_ASC_PERIPHERAL_DEV_WRITE_FAULT 0x03
  241. #define SCSI_ASC_LUN_NOT_READY 0x04
  242. #define SCSI_ASC_WARNING 0x0B
  243. #define SCSI_ASC_LOG_BLOCK_GUARD_CHECK_FAILED 0x10
  244. #define SCSI_ASC_LOG_BLOCK_APPTAG_CHECK_FAILED 0x10
  245. #define SCSI_ASC_LOG_BLOCK_REFTAG_CHECK_FAILED 0x10
  246. #define SCSI_ASC_UNRECOVERED_READ_ERROR 0x11
  247. #define SCSI_ASC_MISCOMPARE_DURING_VERIFY 0x1D
  248. #define SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID 0x20
  249. #define SCSI_ASC_ILLEGAL_COMMAND 0x20
  250. #define SCSI_ASC_ILLEGAL_BLOCK 0x21
  251. #define SCSI_ASC_INVALID_CDB 0x24
  252. #define SCSI_ASC_INVALID_LUN 0x25
  253. #define SCSI_ASC_INVALID_PARAMETER 0x26
  254. #define SCSI_ASC_FORMAT_COMMAND_FAILED 0x31
  255. #define SCSI_ASC_INTERNAL_TARGET_FAILURE 0x44
  256. /* SCSI ADDITIONAL SENSE Code Qualifiers */
  257. #define SCSI_ASCQ_CAUSE_NOT_REPORTABLE 0x00
  258. #define SCSI_ASCQ_FORMAT_COMMAND_FAILED 0x01
  259. #define SCSI_ASCQ_LOG_BLOCK_GUARD_CHECK_FAILED 0x01
  260. #define SCSI_ASCQ_LOG_BLOCK_APPTAG_CHECK_FAILED 0x02
  261. #define SCSI_ASCQ_LOG_BLOCK_REFTAG_CHECK_FAILED 0x03
  262. #define SCSI_ASCQ_FORMAT_IN_PROGRESS 0x04
  263. #define SCSI_ASCQ_POWER_LOSS_EXPECTED 0x08
  264. #define SCSI_ASCQ_INVALID_LUN_ID 0x09
  265. /**
  266. * DEVICE_SPECIFIC_PARAMETER in mode parameter header (see sbc2r16) to
  267. * enable DPOFUA support type 0x10 value.
  268. */
  269. #define DEVICE_SPECIFIC_PARAMETER 0
  270. #define VPD_ID_DESCRIPTOR_LENGTH sizeof(VPD_IDENTIFICATION_DESCRIPTOR)
  271. /* MACROs to extract information from CDBs */
  272. #define GET_OPCODE(cdb) cdb[0]
  273. #define GET_U8_FROM_CDB(cdb, index) (cdb[index] << 0)
  274. #define GET_U16_FROM_CDB(cdb, index) ((cdb[index] << 8) | (cdb[index + 1] << 0))
  275. #define GET_U24_FROM_CDB(cdb, index) ((cdb[index] << 16) | \
  276. (cdb[index + 1] << 8) | \
  277. (cdb[index + 2] << 0))
  278. #define GET_U32_FROM_CDB(cdb, index) ((cdb[index] << 24) | \
  279. (cdb[index + 1] << 16) | \
  280. (cdb[index + 2] << 8) | \
  281. (cdb[index + 3] << 0))
  282. #define GET_U64_FROM_CDB(cdb, index) ((((u64)cdb[index]) << 56) | \
  283. (((u64)cdb[index + 1]) << 48) | \
  284. (((u64)cdb[index + 2]) << 40) | \
  285. (((u64)cdb[index + 3]) << 32) | \
  286. (((u64)cdb[index + 4]) << 24) | \
  287. (((u64)cdb[index + 5]) << 16) | \
  288. (((u64)cdb[index + 6]) << 8) | \
  289. (((u64)cdb[index + 7]) << 0))
  290. /* Inquiry Helper Macros */
  291. #define GET_INQ_EVPD_BIT(cdb) \
  292. ((GET_U8_FROM_CDB(cdb, INQUIRY_EVPD_BYTE_OFFSET) & \
  293. INQUIRY_EVPD_BIT_MASK) ? 1 : 0)
  294. #define GET_INQ_PAGE_CODE(cdb) \
  295. (GET_U8_FROM_CDB(cdb, INQUIRY_PAGE_CODE_BYTE_OFFSET))
  296. #define GET_INQ_ALLOC_LENGTH(cdb) \
  297. (GET_U16_FROM_CDB(cdb, INQUIRY_CDB_ALLOCATION_LENGTH_OFFSET))
  298. /* Report LUNs Helper Macros */
  299. #define GET_REPORT_LUNS_ALLOC_LENGTH(cdb) \
  300. (GET_U32_FROM_CDB(cdb, REPORT_LUNS_CDB_ALLOC_LENGTH_OFFSET))
  301. /* Read Capacity Helper Macros */
  302. #define GET_READ_CAP_16_ALLOC_LENGTH(cdb) \
  303. (GET_U32_FROM_CDB(cdb, READ_CAP_16_CDB_ALLOC_LENGTH_OFFSET))
  304. #define IS_READ_CAP_16(cdb) \
  305. ((cdb[0] == SERVICE_ACTION_IN && cdb[1] == SAI_READ_CAPACITY_16) ? 1 : 0)
  306. /* Request Sense Helper Macros */
  307. #define GET_REQUEST_SENSE_ALLOC_LENGTH(cdb) \
  308. (GET_U8_FROM_CDB(cdb, REQUEST_SENSE_CDB_ALLOC_LENGTH_OFFSET))
  309. /* Mode Sense Helper Macros */
  310. #define GET_MODE_SENSE_DBD(cdb) \
  311. ((GET_U8_FROM_CDB(cdb, MODE_SENSE_DBD_OFFSET) & MODE_SENSE_DBD_MASK) >> \
  312. MODE_SENSE_DBD_SHIFT)
  313. #define GET_MODE_SENSE_LLBAA(cdb) \
  314. ((GET_U8_FROM_CDB(cdb, MODE_SENSE_LLBAA_OFFSET) & \
  315. MODE_SENSE_LLBAA_MASK) >> MODE_SENSE_LLBAA_SHIFT)
  316. #define GET_MODE_SENSE_MPH_SIZE(cdb10) \
  317. (cdb10 ? MODE_SENSE10_MPH_SIZE : MODE_SENSE6_MPH_SIZE)
  318. /* Struct to gather data that needs to be extracted from a SCSI CDB.
  319. Not conforming to any particular CDB variant, but compatible with all. */
  320. struct nvme_trans_io_cdb {
  321. u8 fua;
  322. u8 prot_info;
  323. u64 lba;
  324. u32 xfer_len;
  325. };
  326. /* Internal Helper Functions */
  327. /* Copy data to userspace memory */
  328. static int nvme_trans_copy_to_user(struct sg_io_hdr *hdr, void *from,
  329. unsigned long n)
  330. {
  331. int res = SNTI_TRANSLATION_SUCCESS;
  332. unsigned long not_copied;
  333. int i;
  334. void *index = from;
  335. size_t remaining = n;
  336. size_t xfer_len;
  337. if (hdr->iovec_count > 0) {
  338. struct sg_iovec sgl;
  339. for (i = 0; i < hdr->iovec_count; i++) {
  340. not_copied = copy_from_user(&sgl, hdr->dxferp +
  341. i * sizeof(struct sg_iovec),
  342. sizeof(struct sg_iovec));
  343. if (not_copied)
  344. return -EFAULT;
  345. xfer_len = min(remaining, sgl.iov_len);
  346. not_copied = copy_to_user(sgl.iov_base, index,
  347. xfer_len);
  348. if (not_copied) {
  349. res = -EFAULT;
  350. break;
  351. }
  352. index += xfer_len;
  353. remaining -= xfer_len;
  354. if (remaining == 0)
  355. break;
  356. }
  357. return res;
  358. }
  359. not_copied = copy_to_user(hdr->dxferp, from, n);
  360. if (not_copied)
  361. res = -EFAULT;
  362. return res;
  363. }
  364. /* Copy data from userspace memory */
  365. static int nvme_trans_copy_from_user(struct sg_io_hdr *hdr, void *to,
  366. unsigned long n)
  367. {
  368. int res = SNTI_TRANSLATION_SUCCESS;
  369. unsigned long not_copied;
  370. int i;
  371. void *index = to;
  372. size_t remaining = n;
  373. size_t xfer_len;
  374. if (hdr->iovec_count > 0) {
  375. struct sg_iovec sgl;
  376. for (i = 0; i < hdr->iovec_count; i++) {
  377. not_copied = copy_from_user(&sgl, hdr->dxferp +
  378. i * sizeof(struct sg_iovec),
  379. sizeof(struct sg_iovec));
  380. if (not_copied)
  381. return -EFAULT;
  382. xfer_len = min(remaining, sgl.iov_len);
  383. not_copied = copy_from_user(index, sgl.iov_base,
  384. xfer_len);
  385. if (not_copied) {
  386. res = -EFAULT;
  387. break;
  388. }
  389. index += xfer_len;
  390. remaining -= xfer_len;
  391. if (remaining == 0)
  392. break;
  393. }
  394. return res;
  395. }
  396. not_copied = copy_from_user(to, hdr->dxferp, n);
  397. if (not_copied)
  398. res = -EFAULT;
  399. return res;
  400. }
  401. /* Status/Sense Buffer Writeback */
  402. static int nvme_trans_completion(struct sg_io_hdr *hdr, u8 status, u8 sense_key,
  403. u8 asc, u8 ascq)
  404. {
  405. int res = SNTI_TRANSLATION_SUCCESS;
  406. u8 xfer_len;
  407. u8 resp[DESC_FMT_SENSE_DATA_SIZE];
  408. if (scsi_status_is_good(status)) {
  409. hdr->status = SAM_STAT_GOOD;
  410. hdr->masked_status = GOOD;
  411. hdr->host_status = DID_OK;
  412. hdr->driver_status = DRIVER_OK;
  413. hdr->sb_len_wr = 0;
  414. } else {
  415. hdr->status = status;
  416. hdr->masked_status = status >> 1;
  417. hdr->host_status = DID_OK;
  418. hdr->driver_status = DRIVER_OK;
  419. memset(resp, 0, DESC_FMT_SENSE_DATA_SIZE);
  420. resp[0] = DESC_FORMAT_SENSE_DATA;
  421. resp[1] = sense_key;
  422. resp[2] = asc;
  423. resp[3] = ascq;
  424. xfer_len = min_t(u8, hdr->mx_sb_len, DESC_FMT_SENSE_DATA_SIZE);
  425. hdr->sb_len_wr = xfer_len;
  426. if (copy_to_user(hdr->sbp, resp, xfer_len) > 0)
  427. res = -EFAULT;
  428. }
  429. return res;
  430. }
  431. static int nvme_trans_status_code(struct sg_io_hdr *hdr, int nvme_sc)
  432. {
  433. u8 status, sense_key, asc, ascq;
  434. int res = SNTI_TRANSLATION_SUCCESS;
  435. /* For non-nvme (Linux) errors, simply return the error code */
  436. if (nvme_sc < 0)
  437. return nvme_sc;
  438. /* Mask DNR, More, and reserved fields */
  439. nvme_sc &= 0x7FF;
  440. switch (nvme_sc) {
  441. /* Generic Command Status */
  442. case NVME_SC_SUCCESS:
  443. status = SAM_STAT_GOOD;
  444. sense_key = NO_SENSE;
  445. asc = SCSI_ASC_NO_SENSE;
  446. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  447. break;
  448. case NVME_SC_INVALID_OPCODE:
  449. status = SAM_STAT_CHECK_CONDITION;
  450. sense_key = ILLEGAL_REQUEST;
  451. asc = SCSI_ASC_ILLEGAL_COMMAND;
  452. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  453. break;
  454. case NVME_SC_INVALID_FIELD:
  455. status = SAM_STAT_CHECK_CONDITION;
  456. sense_key = ILLEGAL_REQUEST;
  457. asc = SCSI_ASC_INVALID_CDB;
  458. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  459. break;
  460. case NVME_SC_DATA_XFER_ERROR:
  461. status = SAM_STAT_CHECK_CONDITION;
  462. sense_key = MEDIUM_ERROR;
  463. asc = SCSI_ASC_NO_SENSE;
  464. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  465. break;
  466. case NVME_SC_POWER_LOSS:
  467. status = SAM_STAT_TASK_ABORTED;
  468. sense_key = ABORTED_COMMAND;
  469. asc = SCSI_ASC_WARNING;
  470. ascq = SCSI_ASCQ_POWER_LOSS_EXPECTED;
  471. break;
  472. case NVME_SC_INTERNAL:
  473. status = SAM_STAT_CHECK_CONDITION;
  474. sense_key = HARDWARE_ERROR;
  475. asc = SCSI_ASC_INTERNAL_TARGET_FAILURE;
  476. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  477. break;
  478. case NVME_SC_ABORT_REQ:
  479. status = SAM_STAT_TASK_ABORTED;
  480. sense_key = ABORTED_COMMAND;
  481. asc = SCSI_ASC_NO_SENSE;
  482. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  483. break;
  484. case NVME_SC_ABORT_QUEUE:
  485. status = SAM_STAT_TASK_ABORTED;
  486. sense_key = ABORTED_COMMAND;
  487. asc = SCSI_ASC_NO_SENSE;
  488. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  489. break;
  490. case NVME_SC_FUSED_FAIL:
  491. status = SAM_STAT_TASK_ABORTED;
  492. sense_key = ABORTED_COMMAND;
  493. asc = SCSI_ASC_NO_SENSE;
  494. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  495. break;
  496. case NVME_SC_FUSED_MISSING:
  497. status = SAM_STAT_TASK_ABORTED;
  498. sense_key = ABORTED_COMMAND;
  499. asc = SCSI_ASC_NO_SENSE;
  500. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  501. break;
  502. case NVME_SC_INVALID_NS:
  503. status = SAM_STAT_CHECK_CONDITION;
  504. sense_key = ILLEGAL_REQUEST;
  505. asc = SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID;
  506. ascq = SCSI_ASCQ_INVALID_LUN_ID;
  507. break;
  508. case NVME_SC_LBA_RANGE:
  509. status = SAM_STAT_CHECK_CONDITION;
  510. sense_key = ILLEGAL_REQUEST;
  511. asc = SCSI_ASC_ILLEGAL_BLOCK;
  512. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  513. break;
  514. case NVME_SC_CAP_EXCEEDED:
  515. status = SAM_STAT_CHECK_CONDITION;
  516. sense_key = MEDIUM_ERROR;
  517. asc = SCSI_ASC_NO_SENSE;
  518. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  519. break;
  520. case NVME_SC_NS_NOT_READY:
  521. status = SAM_STAT_CHECK_CONDITION;
  522. sense_key = NOT_READY;
  523. asc = SCSI_ASC_LUN_NOT_READY;
  524. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  525. break;
  526. /* Command Specific Status */
  527. case NVME_SC_INVALID_FORMAT:
  528. status = SAM_STAT_CHECK_CONDITION;
  529. sense_key = ILLEGAL_REQUEST;
  530. asc = SCSI_ASC_FORMAT_COMMAND_FAILED;
  531. ascq = SCSI_ASCQ_FORMAT_COMMAND_FAILED;
  532. break;
  533. case NVME_SC_BAD_ATTRIBUTES:
  534. status = SAM_STAT_CHECK_CONDITION;
  535. sense_key = ILLEGAL_REQUEST;
  536. asc = SCSI_ASC_INVALID_CDB;
  537. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  538. break;
  539. /* Media Errors */
  540. case NVME_SC_WRITE_FAULT:
  541. status = SAM_STAT_CHECK_CONDITION;
  542. sense_key = MEDIUM_ERROR;
  543. asc = SCSI_ASC_PERIPHERAL_DEV_WRITE_FAULT;
  544. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  545. break;
  546. case NVME_SC_READ_ERROR:
  547. status = SAM_STAT_CHECK_CONDITION;
  548. sense_key = MEDIUM_ERROR;
  549. asc = SCSI_ASC_UNRECOVERED_READ_ERROR;
  550. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  551. break;
  552. case NVME_SC_GUARD_CHECK:
  553. status = SAM_STAT_CHECK_CONDITION;
  554. sense_key = MEDIUM_ERROR;
  555. asc = SCSI_ASC_LOG_BLOCK_GUARD_CHECK_FAILED;
  556. ascq = SCSI_ASCQ_LOG_BLOCK_GUARD_CHECK_FAILED;
  557. break;
  558. case NVME_SC_APPTAG_CHECK:
  559. status = SAM_STAT_CHECK_CONDITION;
  560. sense_key = MEDIUM_ERROR;
  561. asc = SCSI_ASC_LOG_BLOCK_APPTAG_CHECK_FAILED;
  562. ascq = SCSI_ASCQ_LOG_BLOCK_APPTAG_CHECK_FAILED;
  563. break;
  564. case NVME_SC_REFTAG_CHECK:
  565. status = SAM_STAT_CHECK_CONDITION;
  566. sense_key = MEDIUM_ERROR;
  567. asc = SCSI_ASC_LOG_BLOCK_REFTAG_CHECK_FAILED;
  568. ascq = SCSI_ASCQ_LOG_BLOCK_REFTAG_CHECK_FAILED;
  569. break;
  570. case NVME_SC_COMPARE_FAILED:
  571. status = SAM_STAT_CHECK_CONDITION;
  572. sense_key = MISCOMPARE;
  573. asc = SCSI_ASC_MISCOMPARE_DURING_VERIFY;
  574. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  575. break;
  576. case NVME_SC_ACCESS_DENIED:
  577. status = SAM_STAT_CHECK_CONDITION;
  578. sense_key = ILLEGAL_REQUEST;
  579. asc = SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID;
  580. ascq = SCSI_ASCQ_INVALID_LUN_ID;
  581. break;
  582. /* Unspecified/Default */
  583. case NVME_SC_CMDID_CONFLICT:
  584. case NVME_SC_CMD_SEQ_ERROR:
  585. case NVME_SC_CQ_INVALID:
  586. case NVME_SC_QID_INVALID:
  587. case NVME_SC_QUEUE_SIZE:
  588. case NVME_SC_ABORT_LIMIT:
  589. case NVME_SC_ABORT_MISSING:
  590. case NVME_SC_ASYNC_LIMIT:
  591. case NVME_SC_FIRMWARE_SLOT:
  592. case NVME_SC_FIRMWARE_IMAGE:
  593. case NVME_SC_INVALID_VECTOR:
  594. case NVME_SC_INVALID_LOG_PAGE:
  595. default:
  596. status = SAM_STAT_CHECK_CONDITION;
  597. sense_key = ILLEGAL_REQUEST;
  598. asc = SCSI_ASC_NO_SENSE;
  599. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  600. break;
  601. }
  602. res = nvme_trans_completion(hdr, status, sense_key, asc, ascq);
  603. return res;
  604. }
  605. /* INQUIRY Helper Functions */
  606. static int nvme_trans_standard_inquiry_page(struct nvme_ns *ns,
  607. struct sg_io_hdr *hdr, u8 *inq_response,
  608. int alloc_len)
  609. {
  610. struct nvme_dev *dev = ns->dev;
  611. dma_addr_t dma_addr;
  612. void *mem;
  613. struct nvme_id_ns *id_ns;
  614. int res = SNTI_TRANSLATION_SUCCESS;
  615. int nvme_sc;
  616. int xfer_len;
  617. u8 resp_data_format = 0x02;
  618. u8 protect;
  619. u8 cmdque = 0x01 << 1;
  620. mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns),
  621. &dma_addr, GFP_KERNEL);
  622. if (mem == NULL) {
  623. res = -ENOMEM;
  624. goto out_dma;
  625. }
  626. /* nvme ns identify - use DPS value for PROTECT field */
  627. nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
  628. res = nvme_trans_status_code(hdr, nvme_sc);
  629. /*
  630. * If nvme_sc was -ve, res will be -ve here.
  631. * If nvme_sc was +ve, the status would bace been translated, and res
  632. * can only be 0 or -ve.
  633. * - If 0 && nvme_sc > 0, then go into next if where res gets nvme_sc
  634. * - If -ve, return because its a Linux error.
  635. */
  636. if (res)
  637. goto out_free;
  638. if (nvme_sc) {
  639. res = nvme_sc;
  640. goto out_free;
  641. }
  642. id_ns = mem;
  643. (id_ns->dps) ? (protect = 0x01) : (protect = 0);
  644. memset(inq_response, 0, STANDARD_INQUIRY_LENGTH);
  645. inq_response[2] = VERSION_SPC_4;
  646. inq_response[3] = resp_data_format; /*normaca=0 | hisup=0 */
  647. inq_response[4] = ADDITIONAL_STD_INQ_LENGTH;
  648. inq_response[5] = protect; /* sccs=0 | acc=0 | tpgs=0 | pc3=0 */
  649. inq_response[7] = cmdque; /* wbus16=0 | sync=0 | vs=0 */
  650. strncpy(&inq_response[8], "NVMe ", 8);
  651. strncpy(&inq_response[16], dev->model, 16);
  652. strncpy(&inq_response[32], dev->firmware_rev, 4);
  653. xfer_len = min(alloc_len, STANDARD_INQUIRY_LENGTH);
  654. res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
  655. out_free:
  656. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem,
  657. dma_addr);
  658. out_dma:
  659. return res;
  660. }
  661. static int nvme_trans_supported_vpd_pages(struct nvme_ns *ns,
  662. struct sg_io_hdr *hdr, u8 *inq_response,
  663. int alloc_len)
  664. {
  665. int res = SNTI_TRANSLATION_SUCCESS;
  666. int xfer_len;
  667. memset(inq_response, 0, STANDARD_INQUIRY_LENGTH);
  668. inq_response[1] = INQ_SUPPORTED_VPD_PAGES_PAGE; /* Page Code */
  669. inq_response[3] = INQ_NUM_SUPPORTED_VPD_PAGES; /* Page Length */
  670. inq_response[4] = INQ_SUPPORTED_VPD_PAGES_PAGE;
  671. inq_response[5] = INQ_UNIT_SERIAL_NUMBER_PAGE;
  672. inq_response[6] = INQ_DEVICE_IDENTIFICATION_PAGE;
  673. inq_response[7] = INQ_EXTENDED_INQUIRY_DATA_PAGE;
  674. inq_response[8] = INQ_BDEV_CHARACTERISTICS_PAGE;
  675. xfer_len = min(alloc_len, STANDARD_INQUIRY_LENGTH);
  676. res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
  677. return res;
  678. }
  679. static int nvme_trans_unit_serial_page(struct nvme_ns *ns,
  680. struct sg_io_hdr *hdr, u8 *inq_response,
  681. int alloc_len)
  682. {
  683. struct nvme_dev *dev = ns->dev;
  684. int res = SNTI_TRANSLATION_SUCCESS;
  685. int xfer_len;
  686. memset(inq_response, 0, STANDARD_INQUIRY_LENGTH);
  687. inq_response[1] = INQ_UNIT_SERIAL_NUMBER_PAGE; /* Page Code */
  688. inq_response[3] = INQ_SERIAL_NUMBER_LENGTH; /* Page Length */
  689. strncpy(&inq_response[4], dev->serial, INQ_SERIAL_NUMBER_LENGTH);
  690. xfer_len = min(alloc_len, STANDARD_INQUIRY_LENGTH);
  691. res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
  692. return res;
  693. }
  694. static int nvme_trans_device_id_page(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  695. u8 *inq_response, int alloc_len)
  696. {
  697. struct nvme_dev *dev = ns->dev;
  698. dma_addr_t dma_addr;
  699. void *mem;
  700. struct nvme_id_ctrl *id_ctrl;
  701. int res = SNTI_TRANSLATION_SUCCESS;
  702. int nvme_sc;
  703. u8 ieee[4];
  704. int xfer_len;
  705. __be32 tmp_id = cpu_to_be32(ns->ns_id);
  706. mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns),
  707. &dma_addr, GFP_KERNEL);
  708. if (mem == NULL) {
  709. res = -ENOMEM;
  710. goto out_dma;
  711. }
  712. /* nvme controller identify */
  713. nvme_sc = nvme_identify(dev, 0, 1, dma_addr);
  714. res = nvme_trans_status_code(hdr, nvme_sc);
  715. if (res)
  716. goto out_free;
  717. if (nvme_sc) {
  718. res = nvme_sc;
  719. goto out_free;
  720. }
  721. id_ctrl = mem;
  722. /* Since SCSI tried to save 4 bits... [SPC-4(r34) Table 591] */
  723. ieee[0] = id_ctrl->ieee[0] << 4;
  724. ieee[1] = id_ctrl->ieee[0] >> 4 | id_ctrl->ieee[1] << 4;
  725. ieee[2] = id_ctrl->ieee[1] >> 4 | id_ctrl->ieee[2] << 4;
  726. ieee[3] = id_ctrl->ieee[2] >> 4;
  727. memset(inq_response, 0, STANDARD_INQUIRY_LENGTH);
  728. inq_response[1] = INQ_DEVICE_IDENTIFICATION_PAGE; /* Page Code */
  729. inq_response[3] = 20; /* Page Length */
  730. /* Designation Descriptor start */
  731. inq_response[4] = 0x01; /* Proto ID=0h | Code set=1h */
  732. inq_response[5] = 0x03; /* PIV=0b | Asso=00b | Designator Type=3h */
  733. inq_response[6] = 0x00; /* Rsvd */
  734. inq_response[7] = 16; /* Designator Length */
  735. /* Designator start */
  736. inq_response[8] = 0x60 | ieee[3]; /* NAA=6h | IEEE ID MSB, High nibble*/
  737. inq_response[9] = ieee[2]; /* IEEE ID */
  738. inq_response[10] = ieee[1]; /* IEEE ID */
  739. inq_response[11] = ieee[0]; /* IEEE ID| Vendor Specific ID... */
  740. inq_response[12] = (dev->pci_dev->vendor & 0xFF00) >> 8;
  741. inq_response[13] = (dev->pci_dev->vendor & 0x00FF);
  742. inq_response[14] = dev->serial[0];
  743. inq_response[15] = dev->serial[1];
  744. inq_response[16] = dev->model[0];
  745. inq_response[17] = dev->model[1];
  746. memcpy(&inq_response[18], &tmp_id, sizeof(u32));
  747. /* Last 2 bytes are zero */
  748. xfer_len = min(alloc_len, STANDARD_INQUIRY_LENGTH);
  749. res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
  750. out_free:
  751. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem,
  752. dma_addr);
  753. out_dma:
  754. return res;
  755. }
  756. static int nvme_trans_ext_inq_page(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  757. int alloc_len)
  758. {
  759. u8 *inq_response;
  760. int res = SNTI_TRANSLATION_SUCCESS;
  761. int nvme_sc;
  762. struct nvme_dev *dev = ns->dev;
  763. dma_addr_t dma_addr;
  764. void *mem;
  765. struct nvme_id_ctrl *id_ctrl;
  766. struct nvme_id_ns *id_ns;
  767. int xfer_len;
  768. u8 microcode = 0x80;
  769. u8 spt;
  770. u8 spt_lut[8] = {0, 0, 2, 1, 4, 6, 5, 7};
  771. u8 grd_chk, app_chk, ref_chk, protect;
  772. u8 uask_sup = 0x20;
  773. u8 v_sup;
  774. u8 luiclr = 0x01;
  775. inq_response = kmalloc(EXTENDED_INQUIRY_DATA_PAGE_LENGTH, GFP_KERNEL);
  776. if (inq_response == NULL) {
  777. res = -ENOMEM;
  778. goto out_mem;
  779. }
  780. mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns),
  781. &dma_addr, GFP_KERNEL);
  782. if (mem == NULL) {
  783. res = -ENOMEM;
  784. goto out_dma;
  785. }
  786. /* nvme ns identify */
  787. nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
  788. res = nvme_trans_status_code(hdr, nvme_sc);
  789. if (res)
  790. goto out_free;
  791. if (nvme_sc) {
  792. res = nvme_sc;
  793. goto out_free;
  794. }
  795. id_ns = mem;
  796. spt = spt_lut[(id_ns->dpc) & 0x07] << 3;
  797. (id_ns->dps) ? (protect = 0x01) : (protect = 0);
  798. grd_chk = protect << 2;
  799. app_chk = protect << 1;
  800. ref_chk = protect;
  801. /* nvme controller identify */
  802. nvme_sc = nvme_identify(dev, 0, 1, dma_addr);
  803. res = nvme_trans_status_code(hdr, nvme_sc);
  804. if (res)
  805. goto out_free;
  806. if (nvme_sc) {
  807. res = nvme_sc;
  808. goto out_free;
  809. }
  810. id_ctrl = mem;
  811. v_sup = id_ctrl->vwc;
  812. memset(inq_response, 0, EXTENDED_INQUIRY_DATA_PAGE_LENGTH);
  813. inq_response[1] = INQ_EXTENDED_INQUIRY_DATA_PAGE; /* Page Code */
  814. inq_response[2] = 0x00; /* Page Length MSB */
  815. inq_response[3] = 0x3C; /* Page Length LSB */
  816. inq_response[4] = microcode | spt | grd_chk | app_chk | ref_chk;
  817. inq_response[5] = uask_sup;
  818. inq_response[6] = v_sup;
  819. inq_response[7] = luiclr;
  820. inq_response[8] = 0;
  821. inq_response[9] = 0;
  822. xfer_len = min(alloc_len, EXTENDED_INQUIRY_DATA_PAGE_LENGTH);
  823. res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
  824. out_free:
  825. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem,
  826. dma_addr);
  827. out_dma:
  828. kfree(inq_response);
  829. out_mem:
  830. return res;
  831. }
  832. static int nvme_trans_bdev_char_page(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  833. int alloc_len)
  834. {
  835. u8 *inq_response;
  836. int res = SNTI_TRANSLATION_SUCCESS;
  837. int xfer_len;
  838. inq_response = kmalloc(EXTENDED_INQUIRY_DATA_PAGE_LENGTH, GFP_KERNEL);
  839. if (inq_response == NULL) {
  840. res = -ENOMEM;
  841. goto out_mem;
  842. }
  843. memset(inq_response, 0, EXTENDED_INQUIRY_DATA_PAGE_LENGTH);
  844. inq_response[1] = INQ_BDEV_CHARACTERISTICS_PAGE; /* Page Code */
  845. inq_response[2] = 0x00; /* Page Length MSB */
  846. inq_response[3] = 0x3C; /* Page Length LSB */
  847. inq_response[4] = 0x00; /* Medium Rotation Rate MSB */
  848. inq_response[5] = 0x01; /* Medium Rotation Rate LSB */
  849. inq_response[6] = 0x00; /* Form Factor */
  850. xfer_len = min(alloc_len, EXTENDED_INQUIRY_DATA_PAGE_LENGTH);
  851. res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
  852. kfree(inq_response);
  853. out_mem:
  854. return res;
  855. }
  856. /* LOG SENSE Helper Functions */
  857. static int nvme_trans_log_supp_pages(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  858. int alloc_len)
  859. {
  860. int res = SNTI_TRANSLATION_SUCCESS;
  861. int xfer_len;
  862. u8 *log_response;
  863. log_response = kmalloc(LOG_PAGE_SUPPORTED_LOG_PAGES_LENGTH, GFP_KERNEL);
  864. if (log_response == NULL) {
  865. res = -ENOMEM;
  866. goto out_mem;
  867. }
  868. memset(log_response, 0, LOG_PAGE_SUPPORTED_LOG_PAGES_LENGTH);
  869. log_response[0] = LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE;
  870. /* Subpage=0x00, Page Length MSB=0 */
  871. log_response[3] = SUPPORTED_LOG_PAGES_PAGE_LENGTH;
  872. log_response[4] = LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE;
  873. log_response[5] = LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE;
  874. log_response[6] = LOG_PAGE_TEMPERATURE_PAGE;
  875. xfer_len = min(alloc_len, LOG_PAGE_SUPPORTED_LOG_PAGES_LENGTH);
  876. res = nvme_trans_copy_to_user(hdr, log_response, xfer_len);
  877. kfree(log_response);
  878. out_mem:
  879. return res;
  880. }
  881. static int nvme_trans_log_info_exceptions(struct nvme_ns *ns,
  882. struct sg_io_hdr *hdr, int alloc_len)
  883. {
  884. int res = SNTI_TRANSLATION_SUCCESS;
  885. int xfer_len;
  886. u8 *log_response;
  887. struct nvme_command c;
  888. struct nvme_dev *dev = ns->dev;
  889. struct nvme_smart_log *smart_log;
  890. dma_addr_t dma_addr;
  891. void *mem;
  892. u8 temp_c;
  893. u16 temp_k;
  894. log_response = kmalloc(LOG_INFO_EXCP_PAGE_LENGTH, GFP_KERNEL);
  895. if (log_response == NULL) {
  896. res = -ENOMEM;
  897. goto out_mem;
  898. }
  899. memset(log_response, 0, LOG_INFO_EXCP_PAGE_LENGTH);
  900. mem = dma_alloc_coherent(&dev->pci_dev->dev,
  901. sizeof(struct nvme_smart_log),
  902. &dma_addr, GFP_KERNEL);
  903. if (mem == NULL) {
  904. res = -ENOMEM;
  905. goto out_dma;
  906. }
  907. /* Get SMART Log Page */
  908. memset(&c, 0, sizeof(c));
  909. c.common.opcode = nvme_admin_get_log_page;
  910. c.common.nsid = cpu_to_le32(0xFFFFFFFF);
  911. c.common.prp1 = cpu_to_le64(dma_addr);
  912. c.common.cdw10[0] = cpu_to_le32(((sizeof(struct nvme_smart_log) /
  913. BYTES_TO_DWORDS) << 16) | NVME_GET_SMART_LOG_PAGE);
  914. res = nvme_submit_admin_cmd(dev, &c, NULL);
  915. if (res != NVME_SC_SUCCESS) {
  916. temp_c = LOG_TEMP_UNKNOWN;
  917. } else {
  918. smart_log = mem;
  919. temp_k = (smart_log->temperature[1] << 8) +
  920. (smart_log->temperature[0]);
  921. temp_c = temp_k - KELVIN_TEMP_FACTOR;
  922. }
  923. log_response[0] = LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE;
  924. /* Subpage=0x00, Page Length MSB=0 */
  925. log_response[3] = REMAINING_INFO_EXCP_PAGE_LENGTH;
  926. /* Informational Exceptions Log Parameter 1 Start */
  927. /* Parameter Code=0x0000 bytes 4,5 */
  928. log_response[6] = 0x23; /* DU=0, TSD=1, ETC=0, TMC=0, FMT_AND_LNK=11b */
  929. log_response[7] = 0x04; /* PARAMETER LENGTH */
  930. /* Add sense Code and qualifier = 0x00 each */
  931. /* Use Temperature from NVMe Get Log Page, convert to C from K */
  932. log_response[10] = temp_c;
  933. xfer_len = min(alloc_len, LOG_INFO_EXCP_PAGE_LENGTH);
  934. res = nvme_trans_copy_to_user(hdr, log_response, xfer_len);
  935. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_smart_log),
  936. mem, dma_addr);
  937. out_dma:
  938. kfree(log_response);
  939. out_mem:
  940. return res;
  941. }
  942. static int nvme_trans_log_temperature(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  943. int alloc_len)
  944. {
  945. int res = SNTI_TRANSLATION_SUCCESS;
  946. int xfer_len;
  947. u8 *log_response;
  948. struct nvme_command c;
  949. struct nvme_dev *dev = ns->dev;
  950. struct nvme_smart_log *smart_log;
  951. dma_addr_t dma_addr;
  952. void *mem;
  953. u32 feature_resp;
  954. u8 temp_c_cur, temp_c_thresh;
  955. u16 temp_k;
  956. log_response = kmalloc(LOG_TEMP_PAGE_LENGTH, GFP_KERNEL);
  957. if (log_response == NULL) {
  958. res = -ENOMEM;
  959. goto out_mem;
  960. }
  961. memset(log_response, 0, LOG_TEMP_PAGE_LENGTH);
  962. mem = dma_alloc_coherent(&dev->pci_dev->dev,
  963. sizeof(struct nvme_smart_log),
  964. &dma_addr, GFP_KERNEL);
  965. if (mem == NULL) {
  966. res = -ENOMEM;
  967. goto out_dma;
  968. }
  969. /* Get SMART Log Page */
  970. memset(&c, 0, sizeof(c));
  971. c.common.opcode = nvme_admin_get_log_page;
  972. c.common.nsid = cpu_to_le32(0xFFFFFFFF);
  973. c.common.prp1 = cpu_to_le64(dma_addr);
  974. c.common.cdw10[0] = cpu_to_le32(((sizeof(struct nvme_smart_log) /
  975. BYTES_TO_DWORDS) << 16) | NVME_GET_SMART_LOG_PAGE);
  976. res = nvme_submit_admin_cmd(dev, &c, NULL);
  977. if (res != NVME_SC_SUCCESS) {
  978. temp_c_cur = LOG_TEMP_UNKNOWN;
  979. } else {
  980. smart_log = mem;
  981. temp_k = (smart_log->temperature[1] << 8) +
  982. (smart_log->temperature[0]);
  983. temp_c_cur = temp_k - KELVIN_TEMP_FACTOR;
  984. }
  985. /* Get Features for Temp Threshold */
  986. res = nvme_get_features(dev, NVME_FEAT_TEMP_THRESH, 0, 0,
  987. &feature_resp);
  988. if (res != NVME_SC_SUCCESS)
  989. temp_c_thresh = LOG_TEMP_UNKNOWN;
  990. else
  991. temp_c_thresh = (feature_resp & 0xFFFF) - KELVIN_TEMP_FACTOR;
  992. log_response[0] = LOG_PAGE_TEMPERATURE_PAGE;
  993. /* Subpage=0x00, Page Length MSB=0 */
  994. log_response[3] = REMAINING_TEMP_PAGE_LENGTH;
  995. /* Temperature Log Parameter 1 (Temperature) Start */
  996. /* Parameter Code = 0x0000 */
  997. log_response[6] = 0x01; /* Format and Linking = 01b */
  998. log_response[7] = 0x02; /* Parameter Length */
  999. /* Use Temperature from NVMe Get Log Page, convert to C from K */
  1000. log_response[9] = temp_c_cur;
  1001. /* Temperature Log Parameter 2 (Reference Temperature) Start */
  1002. log_response[11] = 0x01; /* Parameter Code = 0x0001 */
  1003. log_response[12] = 0x01; /* Format and Linking = 01b */
  1004. log_response[13] = 0x02; /* Parameter Length */
  1005. /* Use Temperature Thresh from NVMe Get Log Page, convert to C from K */
  1006. log_response[15] = temp_c_thresh;
  1007. xfer_len = min(alloc_len, LOG_TEMP_PAGE_LENGTH);
  1008. res = nvme_trans_copy_to_user(hdr, log_response, xfer_len);
  1009. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_smart_log),
  1010. mem, dma_addr);
  1011. out_dma:
  1012. kfree(log_response);
  1013. out_mem:
  1014. return res;
  1015. }
  1016. /* MODE SENSE Helper Functions */
  1017. static int nvme_trans_fill_mode_parm_hdr(u8 *resp, int len, u8 cdb10, u8 llbaa,
  1018. u16 mode_data_length, u16 blk_desc_len)
  1019. {
  1020. /* Quick check to make sure I don't stomp on my own memory... */
  1021. if ((cdb10 && len < 8) || (!cdb10 && len < 4))
  1022. return SNTI_INTERNAL_ERROR;
  1023. if (cdb10) {
  1024. resp[0] = (mode_data_length & 0xFF00) >> 8;
  1025. resp[1] = (mode_data_length & 0x00FF);
  1026. /* resp[2] and [3] are zero */
  1027. resp[4] = llbaa;
  1028. resp[5] = RESERVED_FIELD;
  1029. resp[6] = (blk_desc_len & 0xFF00) >> 8;
  1030. resp[7] = (blk_desc_len & 0x00FF);
  1031. } else {
  1032. resp[0] = (mode_data_length & 0x00FF);
  1033. /* resp[1] and [2] are zero */
  1034. resp[3] = (blk_desc_len & 0x00FF);
  1035. }
  1036. return SNTI_TRANSLATION_SUCCESS;
  1037. }
  1038. static int nvme_trans_fill_blk_desc(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1039. u8 *resp, int len, u8 llbaa)
  1040. {
  1041. int res = SNTI_TRANSLATION_SUCCESS;
  1042. int nvme_sc;
  1043. struct nvme_dev *dev = ns->dev;
  1044. dma_addr_t dma_addr;
  1045. void *mem;
  1046. struct nvme_id_ns *id_ns;
  1047. u8 flbas;
  1048. u32 lba_length;
  1049. if (llbaa == 0 && len < MODE_PAGE_BLK_DES_LEN)
  1050. return SNTI_INTERNAL_ERROR;
  1051. else if (llbaa > 0 && len < MODE_PAGE_LLBAA_BLK_DES_LEN)
  1052. return SNTI_INTERNAL_ERROR;
  1053. mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns),
  1054. &dma_addr, GFP_KERNEL);
  1055. if (mem == NULL) {
  1056. res = -ENOMEM;
  1057. goto out;
  1058. }
  1059. /* nvme ns identify */
  1060. nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
  1061. res = nvme_trans_status_code(hdr, nvme_sc);
  1062. if (res)
  1063. goto out_dma;
  1064. if (nvme_sc) {
  1065. res = nvme_sc;
  1066. goto out_dma;
  1067. }
  1068. id_ns = mem;
  1069. flbas = (id_ns->flbas) & 0x0F;
  1070. lba_length = (1 << (id_ns->lbaf[flbas].ds));
  1071. if (llbaa == 0) {
  1072. __be32 tmp_cap = cpu_to_be32(le64_to_cpu(id_ns->ncap));
  1073. /* Byte 4 is reserved */
  1074. __be32 tmp_len = cpu_to_be32(lba_length & 0x00FFFFFF);
  1075. memcpy(resp, &tmp_cap, sizeof(u32));
  1076. memcpy(&resp[4], &tmp_len, sizeof(u32));
  1077. } else {
  1078. __be64 tmp_cap = cpu_to_be64(le64_to_cpu(id_ns->ncap));
  1079. __be32 tmp_len = cpu_to_be32(lba_length);
  1080. memcpy(resp, &tmp_cap, sizeof(u64));
  1081. /* Bytes 8, 9, 10, 11 are reserved */
  1082. memcpy(&resp[12], &tmp_len, sizeof(u32));
  1083. }
  1084. out_dma:
  1085. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem,
  1086. dma_addr);
  1087. out:
  1088. return res;
  1089. }
  1090. static int nvme_trans_fill_control_page(struct nvme_ns *ns,
  1091. struct sg_io_hdr *hdr, u8 *resp,
  1092. int len)
  1093. {
  1094. if (len < MODE_PAGE_CONTROL_LEN)
  1095. return SNTI_INTERNAL_ERROR;
  1096. resp[0] = MODE_PAGE_CONTROL;
  1097. resp[1] = MODE_PAGE_CONTROL_LEN_FIELD;
  1098. resp[2] = 0x0E; /* TST=000b, TMF_ONLY=0, DPICZ=1,
  1099. * D_SENSE=1, GLTSD=1, RLEC=0 */
  1100. resp[3] = 0x12; /* Q_ALGO_MODIFIER=1h, NUAR=0, QERR=01b */
  1101. /* Byte 4: VS=0, RAC=0, UA_INT=0, SWP=0 */
  1102. resp[5] = 0x40; /* ATO=0, TAS=1, ATMPE=0, RWWP=0, AUTOLOAD=0 */
  1103. /* resp[6] and [7] are obsolete, thus zero */
  1104. resp[8] = 0xFF; /* Busy timeout period = 0xffff */
  1105. resp[9] = 0xFF;
  1106. /* Bytes 10,11: Extended selftest completion time = 0x0000 */
  1107. return SNTI_TRANSLATION_SUCCESS;
  1108. }
  1109. static int nvme_trans_fill_caching_page(struct nvme_ns *ns,
  1110. struct sg_io_hdr *hdr,
  1111. u8 *resp, int len)
  1112. {
  1113. int res = SNTI_TRANSLATION_SUCCESS;
  1114. int nvme_sc;
  1115. struct nvme_dev *dev = ns->dev;
  1116. u32 feature_resp;
  1117. u8 vwc;
  1118. if (len < MODE_PAGE_CACHING_LEN)
  1119. return SNTI_INTERNAL_ERROR;
  1120. nvme_sc = nvme_get_features(dev, NVME_FEAT_VOLATILE_WC, 0, 0,
  1121. &feature_resp);
  1122. res = nvme_trans_status_code(hdr, nvme_sc);
  1123. if (res)
  1124. goto out;
  1125. if (nvme_sc) {
  1126. res = nvme_sc;
  1127. goto out;
  1128. }
  1129. vwc = feature_resp & 0x00000001;
  1130. resp[0] = MODE_PAGE_CACHING;
  1131. resp[1] = MODE_PAGE_CACHING_LEN_FIELD;
  1132. resp[2] = vwc << 2;
  1133. out:
  1134. return res;
  1135. }
  1136. static int nvme_trans_fill_pow_cnd_page(struct nvme_ns *ns,
  1137. struct sg_io_hdr *hdr, u8 *resp,
  1138. int len)
  1139. {
  1140. int res = SNTI_TRANSLATION_SUCCESS;
  1141. if (len < MODE_PAGE_POW_CND_LEN)
  1142. return SNTI_INTERNAL_ERROR;
  1143. resp[0] = MODE_PAGE_POWER_CONDITION;
  1144. resp[1] = MODE_PAGE_POW_CND_LEN_FIELD;
  1145. /* All other bytes are zero */
  1146. return res;
  1147. }
  1148. static int nvme_trans_fill_inf_exc_page(struct nvme_ns *ns,
  1149. struct sg_io_hdr *hdr, u8 *resp,
  1150. int len)
  1151. {
  1152. int res = SNTI_TRANSLATION_SUCCESS;
  1153. if (len < MODE_PAGE_INF_EXC_LEN)
  1154. return SNTI_INTERNAL_ERROR;
  1155. resp[0] = MODE_PAGE_INFO_EXCEP;
  1156. resp[1] = MODE_PAGE_INF_EXC_LEN_FIELD;
  1157. resp[2] = 0x88;
  1158. /* All other bytes are zero */
  1159. return res;
  1160. }
  1161. static int nvme_trans_fill_all_pages(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1162. u8 *resp, int len)
  1163. {
  1164. int res = SNTI_TRANSLATION_SUCCESS;
  1165. u16 mode_pages_offset_1 = 0;
  1166. u16 mode_pages_offset_2, mode_pages_offset_3, mode_pages_offset_4;
  1167. mode_pages_offset_2 = mode_pages_offset_1 + MODE_PAGE_CACHING_LEN;
  1168. mode_pages_offset_3 = mode_pages_offset_2 + MODE_PAGE_CONTROL_LEN;
  1169. mode_pages_offset_4 = mode_pages_offset_3 + MODE_PAGE_POW_CND_LEN;
  1170. res = nvme_trans_fill_caching_page(ns, hdr, &resp[mode_pages_offset_1],
  1171. MODE_PAGE_CACHING_LEN);
  1172. if (res != SNTI_TRANSLATION_SUCCESS)
  1173. goto out;
  1174. res = nvme_trans_fill_control_page(ns, hdr, &resp[mode_pages_offset_2],
  1175. MODE_PAGE_CONTROL_LEN);
  1176. if (res != SNTI_TRANSLATION_SUCCESS)
  1177. goto out;
  1178. res = nvme_trans_fill_pow_cnd_page(ns, hdr, &resp[mode_pages_offset_3],
  1179. MODE_PAGE_POW_CND_LEN);
  1180. if (res != SNTI_TRANSLATION_SUCCESS)
  1181. goto out;
  1182. res = nvme_trans_fill_inf_exc_page(ns, hdr, &resp[mode_pages_offset_4],
  1183. MODE_PAGE_INF_EXC_LEN);
  1184. if (res != SNTI_TRANSLATION_SUCCESS)
  1185. goto out;
  1186. out:
  1187. return res;
  1188. }
  1189. static inline int nvme_trans_get_blk_desc_len(u8 dbd, u8 llbaa)
  1190. {
  1191. if (dbd == MODE_SENSE_BLK_DESC_ENABLED) {
  1192. /* SPC-4: len = 8 x Num_of_descriptors if llbaa = 0, 16x if 1 */
  1193. return 8 * (llbaa + 1) * MODE_SENSE_BLK_DESC_COUNT;
  1194. } else {
  1195. return 0;
  1196. }
  1197. }
  1198. static int nvme_trans_mode_page_create(struct nvme_ns *ns,
  1199. struct sg_io_hdr *hdr, u8 *cmd,
  1200. u16 alloc_len, u8 cdb10,
  1201. int (*mode_page_fill_func)
  1202. (struct nvme_ns *,
  1203. struct sg_io_hdr *hdr, u8 *, int),
  1204. u16 mode_pages_tot_len)
  1205. {
  1206. int res = SNTI_TRANSLATION_SUCCESS;
  1207. int xfer_len;
  1208. u8 *response;
  1209. u8 dbd, llbaa;
  1210. u16 resp_size;
  1211. int mph_size;
  1212. u16 mode_pages_offset_1;
  1213. u16 blk_desc_len, blk_desc_offset, mode_data_length;
  1214. dbd = GET_MODE_SENSE_DBD(cmd);
  1215. llbaa = GET_MODE_SENSE_LLBAA(cmd);
  1216. mph_size = GET_MODE_SENSE_MPH_SIZE(cdb10);
  1217. blk_desc_len = nvme_trans_get_blk_desc_len(dbd, llbaa);
  1218. resp_size = mph_size + blk_desc_len + mode_pages_tot_len;
  1219. /* Refer spc4r34 Table 440 for calculation of Mode data Length field */
  1220. mode_data_length = 3 + (3 * cdb10) + blk_desc_len + mode_pages_tot_len;
  1221. blk_desc_offset = mph_size;
  1222. mode_pages_offset_1 = blk_desc_offset + blk_desc_len;
  1223. response = kmalloc(resp_size, GFP_KERNEL);
  1224. if (response == NULL) {
  1225. res = -ENOMEM;
  1226. goto out_mem;
  1227. }
  1228. memset(response, 0, resp_size);
  1229. res = nvme_trans_fill_mode_parm_hdr(&response[0], mph_size, cdb10,
  1230. llbaa, mode_data_length, blk_desc_len);
  1231. if (res != SNTI_TRANSLATION_SUCCESS)
  1232. goto out_free;
  1233. if (blk_desc_len > 0) {
  1234. res = nvme_trans_fill_blk_desc(ns, hdr,
  1235. &response[blk_desc_offset],
  1236. blk_desc_len, llbaa);
  1237. if (res != SNTI_TRANSLATION_SUCCESS)
  1238. goto out_free;
  1239. }
  1240. res = mode_page_fill_func(ns, hdr, &response[mode_pages_offset_1],
  1241. mode_pages_tot_len);
  1242. if (res != SNTI_TRANSLATION_SUCCESS)
  1243. goto out_free;
  1244. xfer_len = min(alloc_len, resp_size);
  1245. res = nvme_trans_copy_to_user(hdr, response, xfer_len);
  1246. out_free:
  1247. kfree(response);
  1248. out_mem:
  1249. return res;
  1250. }
  1251. /* Read Capacity Helper Functions */
  1252. static void nvme_trans_fill_read_cap(u8 *response, struct nvme_id_ns *id_ns,
  1253. u8 cdb16)
  1254. {
  1255. u8 flbas;
  1256. u32 lba_length;
  1257. u64 rlba;
  1258. u8 prot_en;
  1259. u8 p_type_lut[4] = {0, 0, 1, 2};
  1260. __be64 tmp_rlba;
  1261. __be32 tmp_rlba_32;
  1262. __be32 tmp_len;
  1263. flbas = (id_ns->flbas) & 0x0F;
  1264. lba_length = (1 << (id_ns->lbaf[flbas].ds));
  1265. rlba = le64_to_cpup(&id_ns->nsze) - 1;
  1266. (id_ns->dps) ? (prot_en = 0x01) : (prot_en = 0);
  1267. if (!cdb16) {
  1268. if (rlba > 0xFFFFFFFF)
  1269. rlba = 0xFFFFFFFF;
  1270. tmp_rlba_32 = cpu_to_be32(rlba);
  1271. tmp_len = cpu_to_be32(lba_length);
  1272. memcpy(response, &tmp_rlba_32, sizeof(u32));
  1273. memcpy(&response[4], &tmp_len, sizeof(u32));
  1274. } else {
  1275. tmp_rlba = cpu_to_be64(rlba);
  1276. tmp_len = cpu_to_be32(lba_length);
  1277. memcpy(response, &tmp_rlba, sizeof(u64));
  1278. memcpy(&response[8], &tmp_len, sizeof(u32));
  1279. response[12] = (p_type_lut[id_ns->dps & 0x3] << 1) | prot_en;
  1280. /* P_I_Exponent = 0x0 | LBPPBE = 0x0 */
  1281. /* LBPME = 0 | LBPRZ = 0 | LALBA = 0x00 */
  1282. /* Bytes 16-31 - Reserved */
  1283. }
  1284. }
  1285. /* Start Stop Unit Helper Functions */
  1286. static int nvme_trans_power_state(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1287. u8 pc, u8 pcmod, u8 start)
  1288. {
  1289. int res = SNTI_TRANSLATION_SUCCESS;
  1290. int nvme_sc;
  1291. struct nvme_dev *dev = ns->dev;
  1292. dma_addr_t dma_addr;
  1293. void *mem;
  1294. struct nvme_id_ctrl *id_ctrl;
  1295. int lowest_pow_st; /* max npss = lowest power consumption */
  1296. unsigned ps_desired = 0;
  1297. /* NVMe Controller Identify */
  1298. mem = dma_alloc_coherent(&dev->pci_dev->dev,
  1299. sizeof(struct nvme_id_ctrl),
  1300. &dma_addr, GFP_KERNEL);
  1301. if (mem == NULL) {
  1302. res = -ENOMEM;
  1303. goto out;
  1304. }
  1305. nvme_sc = nvme_identify(dev, 0, 1, dma_addr);
  1306. res = nvme_trans_status_code(hdr, nvme_sc);
  1307. if (res)
  1308. goto out_dma;
  1309. if (nvme_sc) {
  1310. res = nvme_sc;
  1311. goto out_dma;
  1312. }
  1313. id_ctrl = mem;
  1314. lowest_pow_st = id_ctrl->npss - 1;
  1315. switch (pc) {
  1316. case NVME_POWER_STATE_START_VALID:
  1317. /* Action unspecified if POWER CONDITION MODIFIER != 0 */
  1318. if (pcmod == 0 && start == 0x1)
  1319. ps_desired = POWER_STATE_0;
  1320. if (pcmod == 0 && start == 0x0)
  1321. ps_desired = lowest_pow_st;
  1322. break;
  1323. case NVME_POWER_STATE_ACTIVE:
  1324. /* Action unspecified if POWER CONDITION MODIFIER != 0 */
  1325. if (pcmod == 0)
  1326. ps_desired = POWER_STATE_0;
  1327. break;
  1328. case NVME_POWER_STATE_IDLE:
  1329. /* Action unspecified if POWER CONDITION MODIFIER != [0,1,2] */
  1330. /* min of desired state and (lps-1) because lps is STOP */
  1331. if (pcmod == 0x0)
  1332. ps_desired = min(POWER_STATE_1, (lowest_pow_st - 1));
  1333. else if (pcmod == 0x1)
  1334. ps_desired = min(POWER_STATE_2, (lowest_pow_st - 1));
  1335. else if (pcmod == 0x2)
  1336. ps_desired = min(POWER_STATE_3, (lowest_pow_st - 1));
  1337. break;
  1338. case NVME_POWER_STATE_STANDBY:
  1339. /* Action unspecified if POWER CONDITION MODIFIER != [0,1] */
  1340. if (pcmod == 0x0)
  1341. ps_desired = max(0, (lowest_pow_st - 2));
  1342. else if (pcmod == 0x1)
  1343. ps_desired = max(0, (lowest_pow_st - 1));
  1344. break;
  1345. case NVME_POWER_STATE_LU_CONTROL:
  1346. default:
  1347. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  1348. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  1349. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1350. break;
  1351. }
  1352. nvme_sc = nvme_set_features(dev, NVME_FEAT_POWER_MGMT, ps_desired, 0,
  1353. NULL);
  1354. res = nvme_trans_status_code(hdr, nvme_sc);
  1355. if (res)
  1356. goto out_dma;
  1357. if (nvme_sc)
  1358. res = nvme_sc;
  1359. out_dma:
  1360. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ctrl), mem,
  1361. dma_addr);
  1362. out:
  1363. return res;
  1364. }
  1365. /* Write Buffer Helper Functions */
  1366. /* Also using this for Format Unit with hdr passed as NULL, and buffer_id, 0 */
  1367. static int nvme_trans_send_fw_cmd(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1368. u8 opcode, u32 tot_len, u32 offset,
  1369. u8 buffer_id)
  1370. {
  1371. int res = SNTI_TRANSLATION_SUCCESS;
  1372. int nvme_sc;
  1373. struct nvme_dev *dev = ns->dev;
  1374. struct nvme_command c;
  1375. struct nvme_iod *iod = NULL;
  1376. unsigned length;
  1377. memset(&c, 0, sizeof(c));
  1378. c.common.opcode = opcode;
  1379. if (opcode == nvme_admin_download_fw) {
  1380. if (hdr->iovec_count > 0) {
  1381. /* Assuming SGL is not allowed for this command */
  1382. res = nvme_trans_completion(hdr,
  1383. SAM_STAT_CHECK_CONDITION,
  1384. ILLEGAL_REQUEST,
  1385. SCSI_ASC_INVALID_CDB,
  1386. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1387. goto out;
  1388. }
  1389. iod = nvme_map_user_pages(dev, DMA_TO_DEVICE,
  1390. (unsigned long)hdr->dxferp, tot_len);
  1391. if (IS_ERR(iod)) {
  1392. res = PTR_ERR(iod);
  1393. goto out;
  1394. }
  1395. length = nvme_setup_prps(dev, &c.common, iod, tot_len,
  1396. GFP_KERNEL);
  1397. if (length != tot_len) {
  1398. res = -ENOMEM;
  1399. goto out_unmap;
  1400. }
  1401. c.dlfw.numd = cpu_to_le32((tot_len/BYTES_TO_DWORDS) - 1);
  1402. c.dlfw.offset = cpu_to_le32(offset/BYTES_TO_DWORDS);
  1403. } else if (opcode == nvme_admin_activate_fw) {
  1404. u32 cdw10 = buffer_id | NVME_FWACT_REPL_ACTV;
  1405. c.common.cdw10[0] = cpu_to_le32(cdw10);
  1406. }
  1407. nvme_sc = nvme_submit_admin_cmd(dev, &c, NULL);
  1408. res = nvme_trans_status_code(hdr, nvme_sc);
  1409. if (res)
  1410. goto out_unmap;
  1411. if (nvme_sc)
  1412. res = nvme_sc;
  1413. out_unmap:
  1414. if (opcode == nvme_admin_download_fw) {
  1415. nvme_unmap_user_pages(dev, DMA_TO_DEVICE, iod);
  1416. nvme_free_iod(dev, iod);
  1417. }
  1418. out:
  1419. return res;
  1420. }
  1421. /* Mode Select Helper Functions */
  1422. static inline void nvme_trans_modesel_get_bd_len(u8 *parm_list, u8 cdb10,
  1423. u16 *bd_len, u8 *llbaa)
  1424. {
  1425. if (cdb10) {
  1426. /* 10 Byte CDB */
  1427. *bd_len = (parm_list[MODE_SELECT_10_BD_OFFSET] << 8) +
  1428. parm_list[MODE_SELECT_10_BD_OFFSET + 1];
  1429. *llbaa = parm_list[MODE_SELECT_10_LLBAA_OFFSET] &&
  1430. MODE_SELECT_10_LLBAA_MASK;
  1431. } else {
  1432. /* 6 Byte CDB */
  1433. *bd_len = parm_list[MODE_SELECT_6_BD_OFFSET];
  1434. }
  1435. }
  1436. static void nvme_trans_modesel_save_bd(struct nvme_ns *ns, u8 *parm_list,
  1437. u16 idx, u16 bd_len, u8 llbaa)
  1438. {
  1439. u16 bd_num;
  1440. bd_num = bd_len / ((llbaa == 0) ?
  1441. SHORT_DESC_BLOCK : LONG_DESC_BLOCK);
  1442. /* Store block descriptor info if a FORMAT UNIT comes later */
  1443. /* TODO Saving 1st BD info; what to do if multiple BD received? */
  1444. if (llbaa == 0) {
  1445. /* Standard Block Descriptor - spc4r34 7.5.5.1 */
  1446. ns->mode_select_num_blocks =
  1447. (parm_list[idx + 1] << 16) +
  1448. (parm_list[idx + 2] << 8) +
  1449. (parm_list[idx + 3]);
  1450. ns->mode_select_block_len =
  1451. (parm_list[idx + 5] << 16) +
  1452. (parm_list[idx + 6] << 8) +
  1453. (parm_list[idx + 7]);
  1454. } else {
  1455. /* Long LBA Block Descriptor - sbc3r27 6.4.2.3 */
  1456. ns->mode_select_num_blocks =
  1457. (((u64)parm_list[idx + 0]) << 56) +
  1458. (((u64)parm_list[idx + 1]) << 48) +
  1459. (((u64)parm_list[idx + 2]) << 40) +
  1460. (((u64)parm_list[idx + 3]) << 32) +
  1461. (((u64)parm_list[idx + 4]) << 24) +
  1462. (((u64)parm_list[idx + 5]) << 16) +
  1463. (((u64)parm_list[idx + 6]) << 8) +
  1464. ((u64)parm_list[idx + 7]);
  1465. ns->mode_select_block_len =
  1466. (parm_list[idx + 12] << 24) +
  1467. (parm_list[idx + 13] << 16) +
  1468. (parm_list[idx + 14] << 8) +
  1469. (parm_list[idx + 15]);
  1470. }
  1471. }
  1472. static u16 nvme_trans_modesel_get_mp(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1473. u8 *mode_page, u8 page_code)
  1474. {
  1475. int res = SNTI_TRANSLATION_SUCCESS;
  1476. int nvme_sc;
  1477. struct nvme_dev *dev = ns->dev;
  1478. unsigned dword11;
  1479. switch (page_code) {
  1480. case MODE_PAGE_CACHING:
  1481. dword11 = ((mode_page[2] & CACHING_MODE_PAGE_WCE_MASK) ? 1 : 0);
  1482. nvme_sc = nvme_set_features(dev, NVME_FEAT_VOLATILE_WC, dword11,
  1483. 0, NULL);
  1484. res = nvme_trans_status_code(hdr, nvme_sc);
  1485. if (res)
  1486. break;
  1487. if (nvme_sc) {
  1488. res = nvme_sc;
  1489. break;
  1490. }
  1491. break;
  1492. case MODE_PAGE_CONTROL:
  1493. break;
  1494. case MODE_PAGE_POWER_CONDITION:
  1495. /* Verify the OS is not trying to set timers */
  1496. if ((mode_page[2] & 0x01) != 0 || (mode_page[3] & 0x0F) != 0) {
  1497. res = nvme_trans_completion(hdr,
  1498. SAM_STAT_CHECK_CONDITION,
  1499. ILLEGAL_REQUEST,
  1500. SCSI_ASC_INVALID_PARAMETER,
  1501. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1502. if (!res)
  1503. res = SNTI_INTERNAL_ERROR;
  1504. break;
  1505. }
  1506. break;
  1507. default:
  1508. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  1509. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  1510. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1511. if (!res)
  1512. res = SNTI_INTERNAL_ERROR;
  1513. break;
  1514. }
  1515. return res;
  1516. }
  1517. static int nvme_trans_modesel_data(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1518. u8 *cmd, u16 parm_list_len, u8 pf,
  1519. u8 sp, u8 cdb10)
  1520. {
  1521. int res = SNTI_TRANSLATION_SUCCESS;
  1522. u8 *parm_list;
  1523. u16 bd_len;
  1524. u8 llbaa = 0;
  1525. u16 index, saved_index;
  1526. u8 page_code;
  1527. u16 mp_size;
  1528. /* Get parm list from data-in/out buffer */
  1529. parm_list = kmalloc(parm_list_len, GFP_KERNEL);
  1530. if (parm_list == NULL) {
  1531. res = -ENOMEM;
  1532. goto out;
  1533. }
  1534. res = nvme_trans_copy_from_user(hdr, parm_list, parm_list_len);
  1535. if (res != SNTI_TRANSLATION_SUCCESS)
  1536. goto out_mem;
  1537. nvme_trans_modesel_get_bd_len(parm_list, cdb10, &bd_len, &llbaa);
  1538. index = (cdb10) ? (MODE_SELECT_10_MPH_SIZE) : (MODE_SELECT_6_MPH_SIZE);
  1539. if (bd_len != 0) {
  1540. /* Block Descriptors present, parse */
  1541. nvme_trans_modesel_save_bd(ns, parm_list, index, bd_len, llbaa);
  1542. index += bd_len;
  1543. }
  1544. saved_index = index;
  1545. /* Multiple mode pages may be present; iterate through all */
  1546. /* In 1st Iteration, don't do NVME Command, only check for CDB errors */
  1547. do {
  1548. page_code = parm_list[index] & MODE_SELECT_PAGE_CODE_MASK;
  1549. mp_size = parm_list[index + 1] + 2;
  1550. if ((page_code != MODE_PAGE_CACHING) &&
  1551. (page_code != MODE_PAGE_CONTROL) &&
  1552. (page_code != MODE_PAGE_POWER_CONDITION)) {
  1553. res = nvme_trans_completion(hdr,
  1554. SAM_STAT_CHECK_CONDITION,
  1555. ILLEGAL_REQUEST,
  1556. SCSI_ASC_INVALID_CDB,
  1557. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1558. goto out_mem;
  1559. }
  1560. index += mp_size;
  1561. } while (index < parm_list_len);
  1562. /* In 2nd Iteration, do the NVME Commands */
  1563. index = saved_index;
  1564. do {
  1565. page_code = parm_list[index] & MODE_SELECT_PAGE_CODE_MASK;
  1566. mp_size = parm_list[index + 1] + 2;
  1567. res = nvme_trans_modesel_get_mp(ns, hdr, &parm_list[index],
  1568. page_code);
  1569. if (res != SNTI_TRANSLATION_SUCCESS)
  1570. break;
  1571. index += mp_size;
  1572. } while (index < parm_list_len);
  1573. out_mem:
  1574. kfree(parm_list);
  1575. out:
  1576. return res;
  1577. }
  1578. /* Format Unit Helper Functions */
  1579. static int nvme_trans_fmt_set_blk_size_count(struct nvme_ns *ns,
  1580. struct sg_io_hdr *hdr)
  1581. {
  1582. int res = SNTI_TRANSLATION_SUCCESS;
  1583. int nvme_sc;
  1584. struct nvme_dev *dev = ns->dev;
  1585. dma_addr_t dma_addr;
  1586. void *mem;
  1587. struct nvme_id_ns *id_ns;
  1588. u8 flbas;
  1589. /*
  1590. * SCSI Expects a MODE SELECT would have been issued prior to
  1591. * a FORMAT UNIT, and the block size and number would be used
  1592. * from the block descriptor in it. If a MODE SELECT had not
  1593. * been issued, FORMAT shall use the current values for both.
  1594. */
  1595. if (ns->mode_select_num_blocks == 0 || ns->mode_select_block_len == 0) {
  1596. mem = dma_alloc_coherent(&dev->pci_dev->dev,
  1597. sizeof(struct nvme_id_ns), &dma_addr, GFP_KERNEL);
  1598. if (mem == NULL) {
  1599. res = -ENOMEM;
  1600. goto out;
  1601. }
  1602. /* nvme ns identify */
  1603. nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
  1604. res = nvme_trans_status_code(hdr, nvme_sc);
  1605. if (res)
  1606. goto out_dma;
  1607. if (nvme_sc) {
  1608. res = nvme_sc;
  1609. goto out_dma;
  1610. }
  1611. id_ns = mem;
  1612. if (ns->mode_select_num_blocks == 0)
  1613. ns->mode_select_num_blocks = le64_to_cpu(id_ns->ncap);
  1614. if (ns->mode_select_block_len == 0) {
  1615. flbas = (id_ns->flbas) & 0x0F;
  1616. ns->mode_select_block_len =
  1617. (1 << (id_ns->lbaf[flbas].ds));
  1618. }
  1619. out_dma:
  1620. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns),
  1621. mem, dma_addr);
  1622. }
  1623. out:
  1624. return res;
  1625. }
  1626. static int nvme_trans_fmt_get_parm_header(struct sg_io_hdr *hdr, u8 len,
  1627. u8 format_prot_info, u8 *nvme_pf_code)
  1628. {
  1629. int res = SNTI_TRANSLATION_SUCCESS;
  1630. u8 *parm_list;
  1631. u8 pf_usage, pf_code;
  1632. parm_list = kmalloc(len, GFP_KERNEL);
  1633. if (parm_list == NULL) {
  1634. res = -ENOMEM;
  1635. goto out;
  1636. }
  1637. res = nvme_trans_copy_from_user(hdr, parm_list, len);
  1638. if (res != SNTI_TRANSLATION_SUCCESS)
  1639. goto out_mem;
  1640. if ((parm_list[FORMAT_UNIT_IMMED_OFFSET] &
  1641. FORMAT_UNIT_IMMED_MASK) != 0) {
  1642. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  1643. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  1644. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1645. goto out_mem;
  1646. }
  1647. if (len == FORMAT_UNIT_LONG_PARM_LIST_LEN &&
  1648. (parm_list[FORMAT_UNIT_PROT_INT_OFFSET] & 0x0F) != 0) {
  1649. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  1650. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  1651. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1652. goto out_mem;
  1653. }
  1654. pf_usage = parm_list[FORMAT_UNIT_PROT_FIELD_USAGE_OFFSET] &
  1655. FORMAT_UNIT_PROT_FIELD_USAGE_MASK;
  1656. pf_code = (pf_usage << 2) | format_prot_info;
  1657. switch (pf_code) {
  1658. case 0:
  1659. *nvme_pf_code = 0;
  1660. break;
  1661. case 2:
  1662. *nvme_pf_code = 1;
  1663. break;
  1664. case 3:
  1665. *nvme_pf_code = 2;
  1666. break;
  1667. case 7:
  1668. *nvme_pf_code = 3;
  1669. break;
  1670. default:
  1671. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  1672. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  1673. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1674. break;
  1675. }
  1676. out_mem:
  1677. kfree(parm_list);
  1678. out:
  1679. return res;
  1680. }
  1681. static int nvme_trans_fmt_send_cmd(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1682. u8 prot_info)
  1683. {
  1684. int res = SNTI_TRANSLATION_SUCCESS;
  1685. int nvme_sc;
  1686. struct nvme_dev *dev = ns->dev;
  1687. dma_addr_t dma_addr;
  1688. void *mem;
  1689. struct nvme_id_ns *id_ns;
  1690. u8 i;
  1691. u8 flbas, nlbaf;
  1692. u8 selected_lbaf = 0xFF;
  1693. u32 cdw10 = 0;
  1694. struct nvme_command c;
  1695. /* Loop thru LBAF's in id_ns to match reqd lbaf, put in cdw10 */
  1696. mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns),
  1697. &dma_addr, GFP_KERNEL);
  1698. if (mem == NULL) {
  1699. res = -ENOMEM;
  1700. goto out;
  1701. }
  1702. /* nvme ns identify */
  1703. nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
  1704. res = nvme_trans_status_code(hdr, nvme_sc);
  1705. if (res)
  1706. goto out_dma;
  1707. if (nvme_sc) {
  1708. res = nvme_sc;
  1709. goto out_dma;
  1710. }
  1711. id_ns = mem;
  1712. flbas = (id_ns->flbas) & 0x0F;
  1713. nlbaf = id_ns->nlbaf;
  1714. for (i = 0; i < nlbaf; i++) {
  1715. if (ns->mode_select_block_len == (1 << (id_ns->lbaf[i].ds))) {
  1716. selected_lbaf = i;
  1717. break;
  1718. }
  1719. }
  1720. if (selected_lbaf > 0x0F) {
  1721. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  1722. ILLEGAL_REQUEST, SCSI_ASC_INVALID_PARAMETER,
  1723. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1724. }
  1725. if (ns->mode_select_num_blocks != le64_to_cpu(id_ns->ncap)) {
  1726. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  1727. ILLEGAL_REQUEST, SCSI_ASC_INVALID_PARAMETER,
  1728. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1729. }
  1730. cdw10 |= prot_info << 5;
  1731. cdw10 |= selected_lbaf & 0x0F;
  1732. memset(&c, 0, sizeof(c));
  1733. c.format.opcode = nvme_admin_format_nvm;
  1734. c.format.nsid = cpu_to_le32(ns->ns_id);
  1735. c.format.cdw10 = cpu_to_le32(cdw10);
  1736. nvme_sc = nvme_submit_admin_cmd(dev, &c, NULL);
  1737. res = nvme_trans_status_code(hdr, nvme_sc);
  1738. if (res)
  1739. goto out_dma;
  1740. if (nvme_sc)
  1741. res = nvme_sc;
  1742. out_dma:
  1743. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem,
  1744. dma_addr);
  1745. out:
  1746. return res;
  1747. }
  1748. /* Read/Write Helper Functions */
  1749. static inline void nvme_trans_get_io_cdb6(u8 *cmd,
  1750. struct nvme_trans_io_cdb *cdb_info)
  1751. {
  1752. cdb_info->fua = 0;
  1753. cdb_info->prot_info = 0;
  1754. cdb_info->lba = GET_U32_FROM_CDB(cmd, IO_6_CDB_LBA_OFFSET) &
  1755. IO_6_CDB_LBA_MASK;
  1756. cdb_info->xfer_len = GET_U8_FROM_CDB(cmd, IO_6_CDB_TX_LEN_OFFSET);
  1757. /* sbc3r27 sec 5.32 - TRANSFER LEN of 0 implies a 256 Block transfer */
  1758. if (cdb_info->xfer_len == 0)
  1759. cdb_info->xfer_len = IO_6_DEFAULT_TX_LEN;
  1760. }
  1761. static inline void nvme_trans_get_io_cdb10(u8 *cmd,
  1762. struct nvme_trans_io_cdb *cdb_info)
  1763. {
  1764. cdb_info->fua = GET_U8_FROM_CDB(cmd, IO_10_CDB_FUA_OFFSET) &
  1765. IO_CDB_FUA_MASK;
  1766. cdb_info->prot_info = GET_U8_FROM_CDB(cmd, IO_10_CDB_WP_OFFSET) &
  1767. IO_CDB_WP_MASK >> IO_CDB_WP_SHIFT;
  1768. cdb_info->lba = GET_U32_FROM_CDB(cmd, IO_10_CDB_LBA_OFFSET);
  1769. cdb_info->xfer_len = GET_U16_FROM_CDB(cmd, IO_10_CDB_TX_LEN_OFFSET);
  1770. }
  1771. static inline void nvme_trans_get_io_cdb12(u8 *cmd,
  1772. struct nvme_trans_io_cdb *cdb_info)
  1773. {
  1774. cdb_info->fua = GET_U8_FROM_CDB(cmd, IO_12_CDB_FUA_OFFSET) &
  1775. IO_CDB_FUA_MASK;
  1776. cdb_info->prot_info = GET_U8_FROM_CDB(cmd, IO_12_CDB_WP_OFFSET) &
  1777. IO_CDB_WP_MASK >> IO_CDB_WP_SHIFT;
  1778. cdb_info->lba = GET_U32_FROM_CDB(cmd, IO_12_CDB_LBA_OFFSET);
  1779. cdb_info->xfer_len = GET_U32_FROM_CDB(cmd, IO_12_CDB_TX_LEN_OFFSET);
  1780. }
  1781. static inline void nvme_trans_get_io_cdb16(u8 *cmd,
  1782. struct nvme_trans_io_cdb *cdb_info)
  1783. {
  1784. cdb_info->fua = GET_U8_FROM_CDB(cmd, IO_16_CDB_FUA_OFFSET) &
  1785. IO_CDB_FUA_MASK;
  1786. cdb_info->prot_info = GET_U8_FROM_CDB(cmd, IO_16_CDB_WP_OFFSET) &
  1787. IO_CDB_WP_MASK >> IO_CDB_WP_SHIFT;
  1788. cdb_info->lba = GET_U64_FROM_CDB(cmd, IO_16_CDB_LBA_OFFSET);
  1789. cdb_info->xfer_len = GET_U32_FROM_CDB(cmd, IO_16_CDB_TX_LEN_OFFSET);
  1790. }
  1791. static inline u32 nvme_trans_io_get_num_cmds(struct sg_io_hdr *hdr,
  1792. struct nvme_trans_io_cdb *cdb_info,
  1793. u32 max_blocks)
  1794. {
  1795. /* If using iovecs, send one nvme command per vector */
  1796. if (hdr->iovec_count > 0)
  1797. return hdr->iovec_count;
  1798. else if (cdb_info->xfer_len > max_blocks)
  1799. return ((cdb_info->xfer_len - 1) / max_blocks) + 1;
  1800. else
  1801. return 1;
  1802. }
  1803. static u16 nvme_trans_io_get_control(struct nvme_ns *ns,
  1804. struct nvme_trans_io_cdb *cdb_info)
  1805. {
  1806. u16 control = 0;
  1807. /* When Protection information support is added, implement here */
  1808. if (cdb_info->fua > 0)
  1809. control |= NVME_RW_FUA;
  1810. return control;
  1811. }
  1812. static int nvme_trans_do_nvme_io(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1813. struct nvme_trans_io_cdb *cdb_info, u8 is_write)
  1814. {
  1815. int res = SNTI_TRANSLATION_SUCCESS;
  1816. int nvme_sc;
  1817. struct nvme_dev *dev = ns->dev;
  1818. struct nvme_queue *nvmeq;
  1819. u32 num_cmds;
  1820. struct nvme_iod *iod;
  1821. u64 unit_len;
  1822. u64 unit_num_blocks; /* Number of blocks to xfer in each nvme cmd */
  1823. u32 retcode;
  1824. u32 i = 0;
  1825. u64 nvme_offset = 0;
  1826. void __user *next_mapping_addr;
  1827. struct nvme_command c;
  1828. u8 opcode = (is_write ? nvme_cmd_write : nvme_cmd_read);
  1829. u16 control;
  1830. u32 max_blocks = nvme_block_nr(ns, dev->max_hw_sectors);
  1831. num_cmds = nvme_trans_io_get_num_cmds(hdr, cdb_info, max_blocks);
  1832. /*
  1833. * This loop handles two cases.
  1834. * First, when an SGL is used in the form of an iovec list:
  1835. * - Use iov_base as the next mapping address for the nvme command_id
  1836. * - Use iov_len as the data transfer length for the command.
  1837. * Second, when we have a single buffer
  1838. * - If larger than max_blocks, split into chunks, offset
  1839. * each nvme command accordingly.
  1840. */
  1841. for (i = 0; i < num_cmds; i++) {
  1842. memset(&c, 0, sizeof(c));
  1843. if (hdr->iovec_count > 0) {
  1844. struct sg_iovec sgl;
  1845. retcode = copy_from_user(&sgl, hdr->dxferp +
  1846. i * sizeof(struct sg_iovec),
  1847. sizeof(struct sg_iovec));
  1848. if (retcode)
  1849. return -EFAULT;
  1850. unit_len = sgl.iov_len;
  1851. unit_num_blocks = unit_len >> ns->lba_shift;
  1852. next_mapping_addr = sgl.iov_base;
  1853. } else {
  1854. unit_num_blocks = min((u64)max_blocks,
  1855. (cdb_info->xfer_len - nvme_offset));
  1856. unit_len = unit_num_blocks << ns->lba_shift;
  1857. next_mapping_addr = hdr->dxferp +
  1858. ((1 << ns->lba_shift) * nvme_offset);
  1859. }
  1860. c.rw.opcode = opcode;
  1861. c.rw.nsid = cpu_to_le32(ns->ns_id);
  1862. c.rw.slba = cpu_to_le64(cdb_info->lba + nvme_offset);
  1863. c.rw.length = cpu_to_le16(unit_num_blocks - 1);
  1864. control = nvme_trans_io_get_control(ns, cdb_info);
  1865. c.rw.control = cpu_to_le16(control);
  1866. iod = nvme_map_user_pages(dev,
  1867. (is_write) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
  1868. (unsigned long)next_mapping_addr, unit_len);
  1869. if (IS_ERR(iod)) {
  1870. res = PTR_ERR(iod);
  1871. goto out;
  1872. }
  1873. retcode = nvme_setup_prps(dev, &c.common, iod, unit_len,
  1874. GFP_KERNEL);
  1875. if (retcode != unit_len) {
  1876. nvme_unmap_user_pages(dev,
  1877. (is_write) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
  1878. iod);
  1879. nvme_free_iod(dev, iod);
  1880. res = -ENOMEM;
  1881. goto out;
  1882. }
  1883. nvme_offset += unit_num_blocks;
  1884. nvmeq = get_nvmeq(dev);
  1885. /*
  1886. * Since nvme_submit_sync_cmd sleeps, we can't keep
  1887. * preemption disabled. We may be preempted at any
  1888. * point, and be rescheduled to a different CPU. That
  1889. * will cause cacheline bouncing, but no additional
  1890. * races since q_lock already protects against other
  1891. * CPUs.
  1892. */
  1893. put_nvmeq(nvmeq);
  1894. nvme_sc = nvme_submit_sync_cmd(nvmeq, &c, NULL,
  1895. NVME_IO_TIMEOUT);
  1896. if (nvme_sc != NVME_SC_SUCCESS) {
  1897. nvme_unmap_user_pages(dev,
  1898. (is_write) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
  1899. iod);
  1900. nvme_free_iod(dev, iod);
  1901. res = nvme_trans_status_code(hdr, nvme_sc);
  1902. goto out;
  1903. }
  1904. nvme_unmap_user_pages(dev,
  1905. (is_write) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
  1906. iod);
  1907. nvme_free_iod(dev, iod);
  1908. }
  1909. res = nvme_trans_status_code(hdr, NVME_SC_SUCCESS);
  1910. out:
  1911. return res;
  1912. }
  1913. /* SCSI Command Translation Functions */
  1914. static int nvme_trans_io(struct nvme_ns *ns, struct sg_io_hdr *hdr, u8 is_write,
  1915. u8 *cmd)
  1916. {
  1917. int res = SNTI_TRANSLATION_SUCCESS;
  1918. struct nvme_trans_io_cdb cdb_info;
  1919. u8 opcode = cmd[0];
  1920. u64 xfer_bytes;
  1921. u64 sum_iov_len = 0;
  1922. struct sg_iovec sgl;
  1923. int i;
  1924. size_t not_copied;
  1925. /* Extract Fields from CDB */
  1926. switch (opcode) {
  1927. case WRITE_6:
  1928. case READ_6:
  1929. nvme_trans_get_io_cdb6(cmd, &cdb_info);
  1930. break;
  1931. case WRITE_10:
  1932. case READ_10:
  1933. nvme_trans_get_io_cdb10(cmd, &cdb_info);
  1934. break;
  1935. case WRITE_12:
  1936. case READ_12:
  1937. nvme_trans_get_io_cdb12(cmd, &cdb_info);
  1938. break;
  1939. case WRITE_16:
  1940. case READ_16:
  1941. nvme_trans_get_io_cdb16(cmd, &cdb_info);
  1942. break;
  1943. default:
  1944. /* Will never really reach here */
  1945. res = SNTI_INTERNAL_ERROR;
  1946. goto out;
  1947. }
  1948. /* Calculate total length of transfer (in bytes) */
  1949. if (hdr->iovec_count > 0) {
  1950. for (i = 0; i < hdr->iovec_count; i++) {
  1951. not_copied = copy_from_user(&sgl, hdr->dxferp +
  1952. i * sizeof(struct sg_iovec),
  1953. sizeof(struct sg_iovec));
  1954. if (not_copied)
  1955. return -EFAULT;
  1956. sum_iov_len += sgl.iov_len;
  1957. /* IO vector sizes should be multiples of block size */
  1958. if (sgl.iov_len % (1 << ns->lba_shift) != 0) {
  1959. res = nvme_trans_completion(hdr,
  1960. SAM_STAT_CHECK_CONDITION,
  1961. ILLEGAL_REQUEST,
  1962. SCSI_ASC_INVALID_PARAMETER,
  1963. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1964. goto out;
  1965. }
  1966. }
  1967. } else {
  1968. sum_iov_len = hdr->dxfer_len;
  1969. }
  1970. /* As Per sg ioctl howto, if the lengths differ, use the lower one */
  1971. xfer_bytes = min(((u64)hdr->dxfer_len), sum_iov_len);
  1972. /* If block count and actual data buffer size dont match, error out */
  1973. if (xfer_bytes != (cdb_info.xfer_len << ns->lba_shift)) {
  1974. res = -EINVAL;
  1975. goto out;
  1976. }
  1977. /* Check for 0 length transfer - it is not illegal */
  1978. if (cdb_info.xfer_len == 0)
  1979. goto out;
  1980. /* Send NVMe IO Command(s) */
  1981. res = nvme_trans_do_nvme_io(ns, hdr, &cdb_info, is_write);
  1982. if (res != SNTI_TRANSLATION_SUCCESS)
  1983. goto out;
  1984. out:
  1985. return res;
  1986. }
  1987. static int nvme_trans_inquiry(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1988. u8 *cmd)
  1989. {
  1990. int res = SNTI_TRANSLATION_SUCCESS;
  1991. u8 evpd;
  1992. u8 page_code;
  1993. int alloc_len;
  1994. u8 *inq_response;
  1995. evpd = GET_INQ_EVPD_BIT(cmd);
  1996. page_code = GET_INQ_PAGE_CODE(cmd);
  1997. alloc_len = GET_INQ_ALLOC_LENGTH(cmd);
  1998. inq_response = kmalloc(STANDARD_INQUIRY_LENGTH, GFP_KERNEL);
  1999. if (inq_response == NULL) {
  2000. res = -ENOMEM;
  2001. goto out_mem;
  2002. }
  2003. if (evpd == 0) {
  2004. if (page_code == INQ_STANDARD_INQUIRY_PAGE) {
  2005. res = nvme_trans_standard_inquiry_page(ns, hdr,
  2006. inq_response, alloc_len);
  2007. } else {
  2008. res = nvme_trans_completion(hdr,
  2009. SAM_STAT_CHECK_CONDITION,
  2010. ILLEGAL_REQUEST,
  2011. SCSI_ASC_INVALID_CDB,
  2012. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2013. }
  2014. } else {
  2015. switch (page_code) {
  2016. case VPD_SUPPORTED_PAGES:
  2017. res = nvme_trans_supported_vpd_pages(ns, hdr,
  2018. inq_response, alloc_len);
  2019. break;
  2020. case VPD_SERIAL_NUMBER:
  2021. res = nvme_trans_unit_serial_page(ns, hdr, inq_response,
  2022. alloc_len);
  2023. break;
  2024. case VPD_DEVICE_IDENTIFIERS:
  2025. res = nvme_trans_device_id_page(ns, hdr, inq_response,
  2026. alloc_len);
  2027. break;
  2028. case VPD_EXTENDED_INQUIRY:
  2029. res = nvme_trans_ext_inq_page(ns, hdr, alloc_len);
  2030. break;
  2031. case VPD_BLOCK_DEV_CHARACTERISTICS:
  2032. res = nvme_trans_bdev_char_page(ns, hdr, alloc_len);
  2033. break;
  2034. default:
  2035. res = nvme_trans_completion(hdr,
  2036. SAM_STAT_CHECK_CONDITION,
  2037. ILLEGAL_REQUEST,
  2038. SCSI_ASC_INVALID_CDB,
  2039. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2040. break;
  2041. }
  2042. }
  2043. kfree(inq_response);
  2044. out_mem:
  2045. return res;
  2046. }
  2047. static int nvme_trans_log_sense(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2048. u8 *cmd)
  2049. {
  2050. int res = SNTI_TRANSLATION_SUCCESS;
  2051. u16 alloc_len;
  2052. u8 sp;
  2053. u8 pc;
  2054. u8 page_code;
  2055. sp = GET_U8_FROM_CDB(cmd, LOG_SENSE_CDB_SP_OFFSET);
  2056. if (sp != LOG_SENSE_CDB_SP_NOT_ENABLED) {
  2057. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2058. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2059. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2060. goto out;
  2061. }
  2062. pc = GET_U8_FROM_CDB(cmd, LOG_SENSE_CDB_PC_OFFSET);
  2063. page_code = pc & LOG_SENSE_CDB_PAGE_CODE_MASK;
  2064. pc = (pc & LOG_SENSE_CDB_PC_MASK) >> LOG_SENSE_CDB_PC_SHIFT;
  2065. if (pc != LOG_SENSE_CDB_PC_CUMULATIVE_VALUES) {
  2066. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2067. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2068. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2069. goto out;
  2070. }
  2071. alloc_len = GET_U16_FROM_CDB(cmd, LOG_SENSE_CDB_ALLOC_LENGTH_OFFSET);
  2072. switch (page_code) {
  2073. case LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE:
  2074. res = nvme_trans_log_supp_pages(ns, hdr, alloc_len);
  2075. break;
  2076. case LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE:
  2077. res = nvme_trans_log_info_exceptions(ns, hdr, alloc_len);
  2078. break;
  2079. case LOG_PAGE_TEMPERATURE_PAGE:
  2080. res = nvme_trans_log_temperature(ns, hdr, alloc_len);
  2081. break;
  2082. default:
  2083. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2084. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2085. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2086. break;
  2087. }
  2088. out:
  2089. return res;
  2090. }
  2091. static int nvme_trans_mode_select(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2092. u8 *cmd)
  2093. {
  2094. int res = SNTI_TRANSLATION_SUCCESS;
  2095. u8 cdb10 = 0;
  2096. u16 parm_list_len;
  2097. u8 page_format;
  2098. u8 save_pages;
  2099. page_format = GET_U8_FROM_CDB(cmd, MODE_SELECT_CDB_PAGE_FORMAT_OFFSET);
  2100. page_format &= MODE_SELECT_CDB_PAGE_FORMAT_MASK;
  2101. save_pages = GET_U8_FROM_CDB(cmd, MODE_SELECT_CDB_SAVE_PAGES_OFFSET);
  2102. save_pages &= MODE_SELECT_CDB_SAVE_PAGES_MASK;
  2103. if (GET_OPCODE(cmd) == MODE_SELECT) {
  2104. parm_list_len = GET_U8_FROM_CDB(cmd,
  2105. MODE_SELECT_6_CDB_PARAM_LIST_LENGTH_OFFSET);
  2106. } else {
  2107. parm_list_len = GET_U16_FROM_CDB(cmd,
  2108. MODE_SELECT_10_CDB_PARAM_LIST_LENGTH_OFFSET);
  2109. cdb10 = 1;
  2110. }
  2111. if (parm_list_len != 0) {
  2112. /*
  2113. * According to SPC-4 r24, a paramter list length field of 0
  2114. * shall not be considered an error
  2115. */
  2116. res = nvme_trans_modesel_data(ns, hdr, cmd, parm_list_len,
  2117. page_format, save_pages, cdb10);
  2118. }
  2119. return res;
  2120. }
  2121. static int nvme_trans_mode_sense(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2122. u8 *cmd)
  2123. {
  2124. int res = SNTI_TRANSLATION_SUCCESS;
  2125. u16 alloc_len;
  2126. u8 cdb10 = 0;
  2127. u8 page_code;
  2128. u8 pc;
  2129. if (GET_OPCODE(cmd) == MODE_SENSE) {
  2130. alloc_len = GET_U8_FROM_CDB(cmd, MODE_SENSE6_ALLOC_LEN_OFFSET);
  2131. } else {
  2132. alloc_len = GET_U16_FROM_CDB(cmd,
  2133. MODE_SENSE10_ALLOC_LEN_OFFSET);
  2134. cdb10 = 1;
  2135. }
  2136. pc = GET_U8_FROM_CDB(cmd, MODE_SENSE_PAGE_CONTROL_OFFSET) &
  2137. MODE_SENSE_PAGE_CONTROL_MASK;
  2138. if (pc != MODE_SENSE_PC_CURRENT_VALUES) {
  2139. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2140. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2141. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2142. goto out;
  2143. }
  2144. page_code = GET_U8_FROM_CDB(cmd, MODE_SENSE_PAGE_CODE_OFFSET) &
  2145. MODE_SENSE_PAGE_CODE_MASK;
  2146. switch (page_code) {
  2147. case MODE_PAGE_CACHING:
  2148. res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len,
  2149. cdb10,
  2150. &nvme_trans_fill_caching_page,
  2151. MODE_PAGE_CACHING_LEN);
  2152. break;
  2153. case MODE_PAGE_CONTROL:
  2154. res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len,
  2155. cdb10,
  2156. &nvme_trans_fill_control_page,
  2157. MODE_PAGE_CONTROL_LEN);
  2158. break;
  2159. case MODE_PAGE_POWER_CONDITION:
  2160. res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len,
  2161. cdb10,
  2162. &nvme_trans_fill_pow_cnd_page,
  2163. MODE_PAGE_POW_CND_LEN);
  2164. break;
  2165. case MODE_PAGE_INFO_EXCEP:
  2166. res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len,
  2167. cdb10,
  2168. &nvme_trans_fill_inf_exc_page,
  2169. MODE_PAGE_INF_EXC_LEN);
  2170. break;
  2171. case MODE_PAGE_RETURN_ALL:
  2172. res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len,
  2173. cdb10,
  2174. &nvme_trans_fill_all_pages,
  2175. MODE_PAGE_ALL_LEN);
  2176. break;
  2177. default:
  2178. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2179. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2180. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2181. break;
  2182. }
  2183. out:
  2184. return res;
  2185. }
  2186. static int nvme_trans_read_capacity(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2187. u8 *cmd)
  2188. {
  2189. int res = SNTI_TRANSLATION_SUCCESS;
  2190. int nvme_sc;
  2191. u32 alloc_len = READ_CAP_10_RESP_SIZE;
  2192. u32 resp_size = READ_CAP_10_RESP_SIZE;
  2193. u32 xfer_len;
  2194. u8 cdb16;
  2195. struct nvme_dev *dev = ns->dev;
  2196. dma_addr_t dma_addr;
  2197. void *mem;
  2198. struct nvme_id_ns *id_ns;
  2199. u8 *response;
  2200. cdb16 = IS_READ_CAP_16(cmd);
  2201. if (cdb16) {
  2202. alloc_len = GET_READ_CAP_16_ALLOC_LENGTH(cmd);
  2203. resp_size = READ_CAP_16_RESP_SIZE;
  2204. }
  2205. mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns),
  2206. &dma_addr, GFP_KERNEL);
  2207. if (mem == NULL) {
  2208. res = -ENOMEM;
  2209. goto out;
  2210. }
  2211. /* nvme ns identify */
  2212. nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
  2213. res = nvme_trans_status_code(hdr, nvme_sc);
  2214. if (res)
  2215. goto out_dma;
  2216. if (nvme_sc) {
  2217. res = nvme_sc;
  2218. goto out_dma;
  2219. }
  2220. id_ns = mem;
  2221. response = kmalloc(resp_size, GFP_KERNEL);
  2222. if (response == NULL) {
  2223. res = -ENOMEM;
  2224. goto out_dma;
  2225. }
  2226. memset(response, 0, resp_size);
  2227. nvme_trans_fill_read_cap(response, id_ns, cdb16);
  2228. xfer_len = min(alloc_len, resp_size);
  2229. res = nvme_trans_copy_to_user(hdr, response, xfer_len);
  2230. kfree(response);
  2231. out_dma:
  2232. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem,
  2233. dma_addr);
  2234. out:
  2235. return res;
  2236. }
  2237. static int nvme_trans_report_luns(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2238. u8 *cmd)
  2239. {
  2240. int res = SNTI_TRANSLATION_SUCCESS;
  2241. int nvme_sc;
  2242. u32 alloc_len, xfer_len, resp_size;
  2243. u8 select_report;
  2244. u8 *response;
  2245. struct nvme_dev *dev = ns->dev;
  2246. dma_addr_t dma_addr;
  2247. void *mem;
  2248. struct nvme_id_ctrl *id_ctrl;
  2249. u32 ll_length, lun_id;
  2250. u8 lun_id_offset = REPORT_LUNS_FIRST_LUN_OFFSET;
  2251. __be32 tmp_len;
  2252. alloc_len = GET_REPORT_LUNS_ALLOC_LENGTH(cmd);
  2253. select_report = GET_U8_FROM_CDB(cmd, REPORT_LUNS_SR_OFFSET);
  2254. if ((select_report != ALL_LUNS_RETURNED) &&
  2255. (select_report != ALL_WELL_KNOWN_LUNS_RETURNED) &&
  2256. (select_report != RESTRICTED_LUNS_RETURNED)) {
  2257. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2258. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2259. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2260. goto out;
  2261. } else {
  2262. /* NVMe Controller Identify */
  2263. mem = dma_alloc_coherent(&dev->pci_dev->dev,
  2264. sizeof(struct nvme_id_ctrl),
  2265. &dma_addr, GFP_KERNEL);
  2266. if (mem == NULL) {
  2267. res = -ENOMEM;
  2268. goto out;
  2269. }
  2270. nvme_sc = nvme_identify(dev, 0, 1, dma_addr);
  2271. res = nvme_trans_status_code(hdr, nvme_sc);
  2272. if (res)
  2273. goto out_dma;
  2274. if (nvme_sc) {
  2275. res = nvme_sc;
  2276. goto out_dma;
  2277. }
  2278. id_ctrl = mem;
  2279. ll_length = le32_to_cpu(id_ctrl->nn) * LUN_ENTRY_SIZE;
  2280. resp_size = ll_length + LUN_DATA_HEADER_SIZE;
  2281. if (alloc_len < resp_size) {
  2282. res = nvme_trans_completion(hdr,
  2283. SAM_STAT_CHECK_CONDITION,
  2284. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2285. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2286. goto out_dma;
  2287. }
  2288. response = kmalloc(resp_size, GFP_KERNEL);
  2289. if (response == NULL) {
  2290. res = -ENOMEM;
  2291. goto out_dma;
  2292. }
  2293. memset(response, 0, resp_size);
  2294. /* The first LUN ID will always be 0 per the SAM spec */
  2295. for (lun_id = 0; lun_id < le32_to_cpu(id_ctrl->nn); lun_id++) {
  2296. /*
  2297. * Set the LUN Id and then increment to the next LUN
  2298. * location in the parameter data.
  2299. */
  2300. __be64 tmp_id = cpu_to_be64(lun_id);
  2301. memcpy(&response[lun_id_offset], &tmp_id, sizeof(u64));
  2302. lun_id_offset += LUN_ENTRY_SIZE;
  2303. }
  2304. tmp_len = cpu_to_be32(ll_length);
  2305. memcpy(response, &tmp_len, sizeof(u32));
  2306. }
  2307. xfer_len = min(alloc_len, resp_size);
  2308. res = nvme_trans_copy_to_user(hdr, response, xfer_len);
  2309. kfree(response);
  2310. out_dma:
  2311. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ctrl), mem,
  2312. dma_addr);
  2313. out:
  2314. return res;
  2315. }
  2316. static int nvme_trans_request_sense(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2317. u8 *cmd)
  2318. {
  2319. int res = SNTI_TRANSLATION_SUCCESS;
  2320. u8 alloc_len, xfer_len, resp_size;
  2321. u8 desc_format;
  2322. u8 *response;
  2323. alloc_len = GET_REQUEST_SENSE_ALLOC_LENGTH(cmd);
  2324. desc_format = GET_U8_FROM_CDB(cmd, REQUEST_SENSE_DESC_OFFSET);
  2325. desc_format &= REQUEST_SENSE_DESC_MASK;
  2326. resp_size = ((desc_format) ? (DESC_FMT_SENSE_DATA_SIZE) :
  2327. (FIXED_FMT_SENSE_DATA_SIZE));
  2328. response = kmalloc(resp_size, GFP_KERNEL);
  2329. if (response == NULL) {
  2330. res = -ENOMEM;
  2331. goto out;
  2332. }
  2333. memset(response, 0, resp_size);
  2334. if (desc_format == DESCRIPTOR_FORMAT_SENSE_DATA_TYPE) {
  2335. /* Descriptor Format Sense Data */
  2336. response[0] = DESC_FORMAT_SENSE_DATA;
  2337. response[1] = NO_SENSE;
  2338. /* TODO How is LOW POWER CONDITION ON handled? (byte 2) */
  2339. response[2] = SCSI_ASC_NO_SENSE;
  2340. response[3] = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  2341. /* SDAT_OVFL = 0 | Additional Sense Length = 0 */
  2342. } else {
  2343. /* Fixed Format Sense Data */
  2344. response[0] = FIXED_SENSE_DATA;
  2345. /* Byte 1 = Obsolete */
  2346. response[2] = NO_SENSE; /* FM, EOM, ILI, SDAT_OVFL = 0 */
  2347. /* Bytes 3-6 - Information - set to zero */
  2348. response[7] = FIXED_SENSE_DATA_ADD_LENGTH;
  2349. /* Bytes 8-11 - Cmd Specific Information - set to zero */
  2350. response[12] = SCSI_ASC_NO_SENSE;
  2351. response[13] = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  2352. /* Byte 14 = Field Replaceable Unit Code = 0 */
  2353. /* Bytes 15-17 - SKSV=0; Sense Key Specific = 0 */
  2354. }
  2355. xfer_len = min(alloc_len, resp_size);
  2356. res = nvme_trans_copy_to_user(hdr, response, xfer_len);
  2357. kfree(response);
  2358. out:
  2359. return res;
  2360. }
  2361. static int nvme_trans_security_protocol(struct nvme_ns *ns,
  2362. struct sg_io_hdr *hdr,
  2363. u8 *cmd)
  2364. {
  2365. return nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2366. ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_COMMAND,
  2367. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2368. }
  2369. static int nvme_trans_start_stop(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2370. u8 *cmd)
  2371. {
  2372. int res = SNTI_TRANSLATION_SUCCESS;
  2373. int nvme_sc;
  2374. struct nvme_queue *nvmeq;
  2375. struct nvme_command c;
  2376. u8 immed, pcmod, pc, no_flush, start;
  2377. immed = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_IMMED_OFFSET);
  2378. pcmod = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_POWER_COND_MOD_OFFSET);
  2379. pc = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_POWER_COND_OFFSET);
  2380. no_flush = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_NO_FLUSH_OFFSET);
  2381. start = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_START_OFFSET);
  2382. immed &= START_STOP_UNIT_CDB_IMMED_MASK;
  2383. pcmod &= START_STOP_UNIT_CDB_POWER_COND_MOD_MASK;
  2384. pc = (pc & START_STOP_UNIT_CDB_POWER_COND_MASK) >> NIBBLE_SHIFT;
  2385. no_flush &= START_STOP_UNIT_CDB_NO_FLUSH_MASK;
  2386. start &= START_STOP_UNIT_CDB_START_MASK;
  2387. if (immed != 0) {
  2388. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2389. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2390. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2391. } else {
  2392. if (no_flush == 0) {
  2393. /* Issue NVME FLUSH command prior to START STOP UNIT */
  2394. memset(&c, 0, sizeof(c));
  2395. c.common.opcode = nvme_cmd_flush;
  2396. c.common.nsid = cpu_to_le32(ns->ns_id);
  2397. nvmeq = get_nvmeq(ns->dev);
  2398. put_nvmeq(nvmeq);
  2399. nvme_sc = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT);
  2400. res = nvme_trans_status_code(hdr, nvme_sc);
  2401. if (res)
  2402. goto out;
  2403. if (nvme_sc) {
  2404. res = nvme_sc;
  2405. goto out;
  2406. }
  2407. }
  2408. /* Setup the expected power state transition */
  2409. res = nvme_trans_power_state(ns, hdr, pc, pcmod, start);
  2410. }
  2411. out:
  2412. return res;
  2413. }
  2414. static int nvme_trans_synchronize_cache(struct nvme_ns *ns,
  2415. struct sg_io_hdr *hdr, u8 *cmd)
  2416. {
  2417. int res = SNTI_TRANSLATION_SUCCESS;
  2418. int nvme_sc;
  2419. struct nvme_command c;
  2420. struct nvme_queue *nvmeq;
  2421. memset(&c, 0, sizeof(c));
  2422. c.common.opcode = nvme_cmd_flush;
  2423. c.common.nsid = cpu_to_le32(ns->ns_id);
  2424. nvmeq = get_nvmeq(ns->dev);
  2425. put_nvmeq(nvmeq);
  2426. nvme_sc = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT);
  2427. res = nvme_trans_status_code(hdr, nvme_sc);
  2428. if (res)
  2429. goto out;
  2430. if (nvme_sc)
  2431. res = nvme_sc;
  2432. out:
  2433. return res;
  2434. }
  2435. static int nvme_trans_format_unit(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2436. u8 *cmd)
  2437. {
  2438. int res = SNTI_TRANSLATION_SUCCESS;
  2439. u8 parm_hdr_len = 0;
  2440. u8 nvme_pf_code = 0;
  2441. u8 format_prot_info, long_list, format_data;
  2442. format_prot_info = GET_U8_FROM_CDB(cmd,
  2443. FORMAT_UNIT_CDB_FORMAT_PROT_INFO_OFFSET);
  2444. long_list = GET_U8_FROM_CDB(cmd, FORMAT_UNIT_CDB_LONG_LIST_OFFSET);
  2445. format_data = GET_U8_FROM_CDB(cmd, FORMAT_UNIT_CDB_FORMAT_DATA_OFFSET);
  2446. format_prot_info = (format_prot_info &
  2447. FORMAT_UNIT_CDB_FORMAT_PROT_INFO_MASK) >>
  2448. FORMAT_UNIT_CDB_FORMAT_PROT_INFO_SHIFT;
  2449. long_list &= FORMAT_UNIT_CDB_LONG_LIST_MASK;
  2450. format_data &= FORMAT_UNIT_CDB_FORMAT_DATA_MASK;
  2451. if (format_data != 0) {
  2452. if (format_prot_info != 0) {
  2453. if (long_list == 0)
  2454. parm_hdr_len = FORMAT_UNIT_SHORT_PARM_LIST_LEN;
  2455. else
  2456. parm_hdr_len = FORMAT_UNIT_LONG_PARM_LIST_LEN;
  2457. }
  2458. } else if (format_data == 0 && format_prot_info != 0) {
  2459. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2460. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2461. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2462. goto out;
  2463. }
  2464. /* Get parm header from data-in/out buffer */
  2465. /*
  2466. * According to the translation spec, the only fields in the parameter
  2467. * list we are concerned with are in the header. So allocate only that.
  2468. */
  2469. if (parm_hdr_len > 0) {
  2470. res = nvme_trans_fmt_get_parm_header(hdr, parm_hdr_len,
  2471. format_prot_info, &nvme_pf_code);
  2472. if (res != SNTI_TRANSLATION_SUCCESS)
  2473. goto out;
  2474. }
  2475. /* Attempt to activate any previously downloaded firmware image */
  2476. res = nvme_trans_send_fw_cmd(ns, hdr, nvme_admin_activate_fw, 0, 0, 0);
  2477. /* Determine Block size and count and send format command */
  2478. res = nvme_trans_fmt_set_blk_size_count(ns, hdr);
  2479. if (res != SNTI_TRANSLATION_SUCCESS)
  2480. goto out;
  2481. res = nvme_trans_fmt_send_cmd(ns, hdr, nvme_pf_code);
  2482. out:
  2483. return res;
  2484. }
  2485. static int nvme_trans_test_unit_ready(struct nvme_ns *ns,
  2486. struct sg_io_hdr *hdr,
  2487. u8 *cmd)
  2488. {
  2489. int res = SNTI_TRANSLATION_SUCCESS;
  2490. struct nvme_dev *dev = ns->dev;
  2491. if (!(readl(&dev->bar->csts) & NVME_CSTS_RDY))
  2492. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2493. NOT_READY, SCSI_ASC_LUN_NOT_READY,
  2494. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2495. else
  2496. res = nvme_trans_completion(hdr, SAM_STAT_GOOD, NO_SENSE, 0, 0);
  2497. return res;
  2498. }
  2499. static int nvme_trans_write_buffer(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2500. u8 *cmd)
  2501. {
  2502. int res = SNTI_TRANSLATION_SUCCESS;
  2503. u32 buffer_offset, parm_list_length;
  2504. u8 buffer_id, mode;
  2505. parm_list_length =
  2506. GET_U24_FROM_CDB(cmd, WRITE_BUFFER_CDB_PARM_LIST_LENGTH_OFFSET);
  2507. if (parm_list_length % BYTES_TO_DWORDS != 0) {
  2508. /* NVMe expects Firmware file to be a whole number of DWORDS */
  2509. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2510. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2511. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2512. goto out;
  2513. }
  2514. buffer_id = GET_U8_FROM_CDB(cmd, WRITE_BUFFER_CDB_BUFFER_ID_OFFSET);
  2515. if (buffer_id > NVME_MAX_FIRMWARE_SLOT) {
  2516. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2517. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2518. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2519. goto out;
  2520. }
  2521. mode = GET_U8_FROM_CDB(cmd, WRITE_BUFFER_CDB_MODE_OFFSET) &
  2522. WRITE_BUFFER_CDB_MODE_MASK;
  2523. buffer_offset =
  2524. GET_U24_FROM_CDB(cmd, WRITE_BUFFER_CDB_BUFFER_OFFSET_OFFSET);
  2525. switch (mode) {
  2526. case DOWNLOAD_SAVE_ACTIVATE:
  2527. res = nvme_trans_send_fw_cmd(ns, hdr, nvme_admin_download_fw,
  2528. parm_list_length, buffer_offset,
  2529. buffer_id);
  2530. if (res != SNTI_TRANSLATION_SUCCESS)
  2531. goto out;
  2532. res = nvme_trans_send_fw_cmd(ns, hdr, nvme_admin_activate_fw,
  2533. parm_list_length, buffer_offset,
  2534. buffer_id);
  2535. break;
  2536. case DOWNLOAD_SAVE_DEFER_ACTIVATE:
  2537. res = nvme_trans_send_fw_cmd(ns, hdr, nvme_admin_download_fw,
  2538. parm_list_length, buffer_offset,
  2539. buffer_id);
  2540. break;
  2541. case ACTIVATE_DEFERRED_MICROCODE:
  2542. res = nvme_trans_send_fw_cmd(ns, hdr, nvme_admin_activate_fw,
  2543. parm_list_length, buffer_offset,
  2544. buffer_id);
  2545. break;
  2546. default:
  2547. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2548. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2549. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2550. break;
  2551. }
  2552. out:
  2553. return res;
  2554. }
  2555. struct scsi_unmap_blk_desc {
  2556. __be64 slba;
  2557. __be32 nlb;
  2558. u32 resv;
  2559. };
  2560. struct scsi_unmap_parm_list {
  2561. __be16 unmap_data_len;
  2562. __be16 unmap_blk_desc_data_len;
  2563. u32 resv;
  2564. struct scsi_unmap_blk_desc desc[0];
  2565. };
  2566. static int nvme_trans_unmap(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2567. u8 *cmd)
  2568. {
  2569. struct nvme_dev *dev = ns->dev;
  2570. struct scsi_unmap_parm_list *plist;
  2571. struct nvme_dsm_range *range;
  2572. struct nvme_queue *nvmeq;
  2573. struct nvme_command c;
  2574. int i, nvme_sc, res = -ENOMEM;
  2575. u16 ndesc, list_len;
  2576. dma_addr_t dma_addr;
  2577. list_len = GET_U16_FROM_CDB(cmd, UNMAP_CDB_PARAM_LIST_LENGTH_OFFSET);
  2578. if (!list_len)
  2579. return -EINVAL;
  2580. plist = kmalloc(list_len, GFP_KERNEL);
  2581. if (!plist)
  2582. return -ENOMEM;
  2583. res = nvme_trans_copy_from_user(hdr, plist, list_len);
  2584. if (res != SNTI_TRANSLATION_SUCCESS)
  2585. goto out;
  2586. ndesc = be16_to_cpu(plist->unmap_blk_desc_data_len) >> 4;
  2587. if (!ndesc || ndesc > 256) {
  2588. res = -EINVAL;
  2589. goto out;
  2590. }
  2591. range = dma_alloc_coherent(&dev->pci_dev->dev, ndesc * sizeof(*range),
  2592. &dma_addr, GFP_KERNEL);
  2593. if (!range)
  2594. goto out;
  2595. for (i = 0; i < ndesc; i++) {
  2596. range[i].nlb = cpu_to_le32(be32_to_cpu(plist->desc[i].nlb));
  2597. range[i].slba = cpu_to_le64(be64_to_cpu(plist->desc[i].slba));
  2598. range[i].cattr = 0;
  2599. }
  2600. memset(&c, 0, sizeof(c));
  2601. c.dsm.opcode = nvme_cmd_dsm;
  2602. c.dsm.nsid = cpu_to_le32(ns->ns_id);
  2603. c.dsm.prp1 = cpu_to_le64(dma_addr);
  2604. c.dsm.nr = cpu_to_le32(ndesc - 1);
  2605. c.dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
  2606. nvmeq = get_nvmeq(dev);
  2607. put_nvmeq(nvmeq);
  2608. nvme_sc = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT);
  2609. res = nvme_trans_status_code(hdr, nvme_sc);
  2610. dma_free_coherent(&dev->pci_dev->dev, ndesc * sizeof(*range),
  2611. range, dma_addr);
  2612. out:
  2613. kfree(plist);
  2614. return res;
  2615. }
  2616. static int nvme_scsi_translate(struct nvme_ns *ns, struct sg_io_hdr *hdr)
  2617. {
  2618. u8 cmd[BLK_MAX_CDB];
  2619. int retcode;
  2620. unsigned int opcode;
  2621. if (hdr->cmdp == NULL)
  2622. return -EMSGSIZE;
  2623. if (copy_from_user(cmd, hdr->cmdp, hdr->cmd_len))
  2624. return -EFAULT;
  2625. opcode = cmd[0];
  2626. switch (opcode) {
  2627. case READ_6:
  2628. case READ_10:
  2629. case READ_12:
  2630. case READ_16:
  2631. retcode = nvme_trans_io(ns, hdr, 0, cmd);
  2632. break;
  2633. case WRITE_6:
  2634. case WRITE_10:
  2635. case WRITE_12:
  2636. case WRITE_16:
  2637. retcode = nvme_trans_io(ns, hdr, 1, cmd);
  2638. break;
  2639. case INQUIRY:
  2640. retcode = nvme_trans_inquiry(ns, hdr, cmd);
  2641. break;
  2642. case LOG_SENSE:
  2643. retcode = nvme_trans_log_sense(ns, hdr, cmd);
  2644. break;
  2645. case MODE_SELECT:
  2646. case MODE_SELECT_10:
  2647. retcode = nvme_trans_mode_select(ns, hdr, cmd);
  2648. break;
  2649. case MODE_SENSE:
  2650. case MODE_SENSE_10:
  2651. retcode = nvme_trans_mode_sense(ns, hdr, cmd);
  2652. break;
  2653. case READ_CAPACITY:
  2654. retcode = nvme_trans_read_capacity(ns, hdr, cmd);
  2655. break;
  2656. case SERVICE_ACTION_IN:
  2657. if (IS_READ_CAP_16(cmd))
  2658. retcode = nvme_trans_read_capacity(ns, hdr, cmd);
  2659. else
  2660. goto out;
  2661. break;
  2662. case REPORT_LUNS:
  2663. retcode = nvme_trans_report_luns(ns, hdr, cmd);
  2664. break;
  2665. case REQUEST_SENSE:
  2666. retcode = nvme_trans_request_sense(ns, hdr, cmd);
  2667. break;
  2668. case SECURITY_PROTOCOL_IN:
  2669. case SECURITY_PROTOCOL_OUT:
  2670. retcode = nvme_trans_security_protocol(ns, hdr, cmd);
  2671. break;
  2672. case START_STOP:
  2673. retcode = nvme_trans_start_stop(ns, hdr, cmd);
  2674. break;
  2675. case SYNCHRONIZE_CACHE:
  2676. retcode = nvme_trans_synchronize_cache(ns, hdr, cmd);
  2677. break;
  2678. case FORMAT_UNIT:
  2679. retcode = nvme_trans_format_unit(ns, hdr, cmd);
  2680. break;
  2681. case TEST_UNIT_READY:
  2682. retcode = nvme_trans_test_unit_ready(ns, hdr, cmd);
  2683. break;
  2684. case WRITE_BUFFER:
  2685. retcode = nvme_trans_write_buffer(ns, hdr, cmd);
  2686. break;
  2687. case UNMAP:
  2688. retcode = nvme_trans_unmap(ns, hdr, cmd);
  2689. break;
  2690. default:
  2691. out:
  2692. retcode = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2693. ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_COMMAND,
  2694. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2695. break;
  2696. }
  2697. return retcode;
  2698. }
  2699. int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr)
  2700. {
  2701. struct sg_io_hdr hdr;
  2702. int retcode;
  2703. if (!capable(CAP_SYS_ADMIN))
  2704. return -EACCES;
  2705. if (copy_from_user(&hdr, u_hdr, sizeof(hdr)))
  2706. return -EFAULT;
  2707. if (hdr.interface_id != 'S')
  2708. return -EINVAL;
  2709. if (hdr.cmd_len > BLK_MAX_CDB)
  2710. return -EINVAL;
  2711. retcode = nvme_scsi_translate(ns, &hdr);
  2712. if (retcode < 0)
  2713. return retcode;
  2714. if (retcode > 0)
  2715. retcode = SNTI_TRANSLATION_SUCCESS;
  2716. if (copy_to_user(u_hdr, &hdr, sizeof(sg_io_hdr_t)) > 0)
  2717. return -EFAULT;
  2718. return retcode;
  2719. }
  2720. int nvme_sg_get_version_num(int __user *ip)
  2721. {
  2722. return put_user(sg_version_num, ip);
  2723. }