sata_rcar.c 23 KB

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  1. /*
  2. * Renesas R-Car SATA driver
  3. *
  4. * Author: Vladimir Barinov <source@cogentembedded.com>
  5. * Copyright (C) 2013 Cogent Embedded, Inc.
  6. * Copyright (C) 2013 Renesas Solutions Corp.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/ata.h>
  16. #include <linux/libata.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/clk.h>
  19. #include <linux/err.h>
  20. #define DRV_NAME "sata_rcar"
  21. /* SH-Navi2G/ATAPI-ATA compatible task registers */
  22. #define DATA_REG 0x100
  23. #define SDEVCON_REG 0x138
  24. /* SH-Navi2G/ATAPI module compatible control registers */
  25. #define ATAPI_CONTROL1_REG 0x180
  26. #define ATAPI_STATUS_REG 0x184
  27. #define ATAPI_INT_ENABLE_REG 0x188
  28. #define ATAPI_DTB_ADR_REG 0x198
  29. #define ATAPI_DMA_START_ADR_REG 0x19C
  30. #define ATAPI_DMA_TRANS_CNT_REG 0x1A0
  31. #define ATAPI_CONTROL2_REG 0x1A4
  32. #define ATAPI_SIG_ST_REG 0x1B0
  33. #define ATAPI_BYTE_SWAP_REG 0x1BC
  34. /* ATAPI control 1 register (ATAPI_CONTROL1) bits */
  35. #define ATAPI_CONTROL1_ISM BIT(16)
  36. #define ATAPI_CONTROL1_DTA32M BIT(11)
  37. #define ATAPI_CONTROL1_RESET BIT(7)
  38. #define ATAPI_CONTROL1_DESE BIT(3)
  39. #define ATAPI_CONTROL1_RW BIT(2)
  40. #define ATAPI_CONTROL1_STOP BIT(1)
  41. #define ATAPI_CONTROL1_START BIT(0)
  42. /* ATAPI status register (ATAPI_STATUS) bits */
  43. #define ATAPI_STATUS_SATAINT BIT(11)
  44. #define ATAPI_STATUS_DNEND BIT(6)
  45. #define ATAPI_STATUS_DEVTRM BIT(5)
  46. #define ATAPI_STATUS_DEVINT BIT(4)
  47. #define ATAPI_STATUS_ERR BIT(2)
  48. #define ATAPI_STATUS_NEND BIT(1)
  49. #define ATAPI_STATUS_ACT BIT(0)
  50. /* Interrupt enable register (ATAPI_INT_ENABLE) bits */
  51. #define ATAPI_INT_ENABLE_SATAINT BIT(11)
  52. #define ATAPI_INT_ENABLE_DNEND BIT(6)
  53. #define ATAPI_INT_ENABLE_DEVTRM BIT(5)
  54. #define ATAPI_INT_ENABLE_DEVINT BIT(4)
  55. #define ATAPI_INT_ENABLE_ERR BIT(2)
  56. #define ATAPI_INT_ENABLE_NEND BIT(1)
  57. #define ATAPI_INT_ENABLE_ACT BIT(0)
  58. /* Access control registers for physical layer control register */
  59. #define SATAPHYADDR_REG 0x200
  60. #define SATAPHYWDATA_REG 0x204
  61. #define SATAPHYACCEN_REG 0x208
  62. #define SATAPHYRESET_REG 0x20C
  63. #define SATAPHYRDATA_REG 0x210
  64. #define SATAPHYACK_REG 0x214
  65. /* Physical layer control address command register (SATAPHYADDR) bits */
  66. #define SATAPHYADDR_PHYRATEMODE BIT(10)
  67. #define SATAPHYADDR_PHYCMD_READ BIT(9)
  68. #define SATAPHYADDR_PHYCMD_WRITE BIT(8)
  69. /* Physical layer control enable register (SATAPHYACCEN) bits */
  70. #define SATAPHYACCEN_PHYLANE BIT(0)
  71. /* Physical layer control reset register (SATAPHYRESET) bits */
  72. #define SATAPHYRESET_PHYRST BIT(1)
  73. #define SATAPHYRESET_PHYSRES BIT(0)
  74. /* Physical layer control acknowledge register (SATAPHYACK) bits */
  75. #define SATAPHYACK_PHYACK BIT(0)
  76. /* Serial-ATA HOST control registers */
  77. #define BISTCONF_REG 0x102C
  78. #define SDATA_REG 0x1100
  79. #define SSDEVCON_REG 0x1204
  80. #define SCRSSTS_REG 0x1400
  81. #define SCRSERR_REG 0x1404
  82. #define SCRSCON_REG 0x1408
  83. #define SCRSACT_REG 0x140C
  84. #define SATAINTSTAT_REG 0x1508
  85. #define SATAINTMASK_REG 0x150C
  86. /* SATA INT status register (SATAINTSTAT) bits */
  87. #define SATAINTSTAT_SERR BIT(3)
  88. #define SATAINTSTAT_ATA BIT(0)
  89. /* SATA INT mask register (SATAINTSTAT) bits */
  90. #define SATAINTMASK_SERRMSK BIT(3)
  91. #define SATAINTMASK_ERRMSK BIT(2)
  92. #define SATAINTMASK_ERRCRTMSK BIT(1)
  93. #define SATAINTMASK_ATAMSK BIT(0)
  94. #define SATA_RCAR_INT_MASK (SATAINTMASK_SERRMSK | \
  95. SATAINTMASK_ATAMSK)
  96. /* Physical Layer Control Registers */
  97. #define SATAPCTLR1_REG 0x43
  98. #define SATAPCTLR2_REG 0x52
  99. #define SATAPCTLR3_REG 0x5A
  100. #define SATAPCTLR4_REG 0x60
  101. /* Descriptor table word 0 bit (when DTA32M = 1) */
  102. #define SATA_RCAR_DTEND BIT(0)
  103. struct sata_rcar_priv {
  104. void __iomem *base;
  105. struct clk *clk;
  106. };
  107. static void sata_rcar_phy_initialize(struct sata_rcar_priv *priv)
  108. {
  109. /* idle state */
  110. iowrite32(0, priv->base + SATAPHYADDR_REG);
  111. /* reset */
  112. iowrite32(SATAPHYRESET_PHYRST, priv->base + SATAPHYRESET_REG);
  113. udelay(10);
  114. /* deassert reset */
  115. iowrite32(0, priv->base + SATAPHYRESET_REG);
  116. }
  117. static void sata_rcar_phy_write(struct sata_rcar_priv *priv, u16 reg, u32 val,
  118. int group)
  119. {
  120. int timeout;
  121. /* deassert reset */
  122. iowrite32(0, priv->base + SATAPHYRESET_REG);
  123. /* lane 1 */
  124. iowrite32(SATAPHYACCEN_PHYLANE, priv->base + SATAPHYACCEN_REG);
  125. /* write phy register value */
  126. iowrite32(val, priv->base + SATAPHYWDATA_REG);
  127. /* set register group */
  128. if (group)
  129. reg |= SATAPHYADDR_PHYRATEMODE;
  130. /* write command */
  131. iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, priv->base + SATAPHYADDR_REG);
  132. /* wait for ack */
  133. for (timeout = 0; timeout < 100; timeout++) {
  134. val = ioread32(priv->base + SATAPHYACK_REG);
  135. if (val & SATAPHYACK_PHYACK)
  136. break;
  137. }
  138. if (timeout >= 100)
  139. pr_err("%s timeout\n", __func__);
  140. /* idle state */
  141. iowrite32(0, priv->base + SATAPHYADDR_REG);
  142. }
  143. static void sata_rcar_freeze(struct ata_port *ap)
  144. {
  145. struct sata_rcar_priv *priv = ap->host->private_data;
  146. /* mask */
  147. iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
  148. ata_sff_freeze(ap);
  149. }
  150. static void sata_rcar_thaw(struct ata_port *ap)
  151. {
  152. struct sata_rcar_priv *priv = ap->host->private_data;
  153. /* ack */
  154. iowrite32(~SATA_RCAR_INT_MASK, priv->base + SATAINTSTAT_REG);
  155. ata_sff_thaw(ap);
  156. /* unmask */
  157. iowrite32(0x7ff & ~SATA_RCAR_INT_MASK, priv->base + SATAINTMASK_REG);
  158. }
  159. static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count)
  160. {
  161. u16 *ptr = buffer;
  162. while (count--) {
  163. u16 data = ioread32(reg);
  164. *ptr++ = data;
  165. }
  166. }
  167. static void sata_rcar_iowrite16_rep(void __iomem *reg, void *buffer, int count)
  168. {
  169. const u16 *ptr = buffer;
  170. while (count--)
  171. iowrite32(*ptr++, reg);
  172. }
  173. static u8 sata_rcar_check_status(struct ata_port *ap)
  174. {
  175. return ioread32(ap->ioaddr.status_addr);
  176. }
  177. static u8 sata_rcar_check_altstatus(struct ata_port *ap)
  178. {
  179. return ioread32(ap->ioaddr.altstatus_addr);
  180. }
  181. static void sata_rcar_set_devctl(struct ata_port *ap, u8 ctl)
  182. {
  183. iowrite32(ctl, ap->ioaddr.ctl_addr);
  184. }
  185. static void sata_rcar_dev_select(struct ata_port *ap, unsigned int device)
  186. {
  187. iowrite32(ATA_DEVICE_OBS, ap->ioaddr.device_addr);
  188. ata_sff_pause(ap); /* needed; also flushes, for mmio */
  189. }
  190. static unsigned int sata_rcar_ata_devchk(struct ata_port *ap,
  191. unsigned int device)
  192. {
  193. struct ata_ioports *ioaddr = &ap->ioaddr;
  194. u8 nsect, lbal;
  195. sata_rcar_dev_select(ap, device);
  196. iowrite32(0x55, ioaddr->nsect_addr);
  197. iowrite32(0xaa, ioaddr->lbal_addr);
  198. iowrite32(0xaa, ioaddr->nsect_addr);
  199. iowrite32(0x55, ioaddr->lbal_addr);
  200. iowrite32(0x55, ioaddr->nsect_addr);
  201. iowrite32(0xaa, ioaddr->lbal_addr);
  202. nsect = ioread32(ioaddr->nsect_addr);
  203. lbal = ioread32(ioaddr->lbal_addr);
  204. if (nsect == 0x55 && lbal == 0xaa)
  205. return 1; /* found a device */
  206. return 0; /* nothing found */
  207. }
  208. static int sata_rcar_wait_after_reset(struct ata_link *link,
  209. unsigned long deadline)
  210. {
  211. struct ata_port *ap = link->ap;
  212. ata_msleep(ap, ATA_WAIT_AFTER_RESET);
  213. return ata_sff_wait_ready(link, deadline);
  214. }
  215. static int sata_rcar_bus_softreset(struct ata_port *ap, unsigned long deadline)
  216. {
  217. struct ata_ioports *ioaddr = &ap->ioaddr;
  218. DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
  219. /* software reset. causes dev0 to be selected */
  220. iowrite32(ap->ctl, ioaddr->ctl_addr);
  221. udelay(20);
  222. iowrite32(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
  223. udelay(20);
  224. iowrite32(ap->ctl, ioaddr->ctl_addr);
  225. ap->last_ctl = ap->ctl;
  226. /* wait the port to become ready */
  227. return sata_rcar_wait_after_reset(&ap->link, deadline);
  228. }
  229. static int sata_rcar_softreset(struct ata_link *link, unsigned int *classes,
  230. unsigned long deadline)
  231. {
  232. struct ata_port *ap = link->ap;
  233. unsigned int devmask = 0;
  234. int rc;
  235. u8 err;
  236. /* determine if device 0 is present */
  237. if (sata_rcar_ata_devchk(ap, 0))
  238. devmask |= 1 << 0;
  239. /* issue bus reset */
  240. DPRINTK("about to softreset, devmask=%x\n", devmask);
  241. rc = sata_rcar_bus_softreset(ap, deadline);
  242. /* if link is occupied, -ENODEV too is an error */
  243. if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
  244. ata_link_err(link, "SRST failed (errno=%d)\n", rc);
  245. return rc;
  246. }
  247. /* determine by signature whether we have ATA or ATAPI devices */
  248. classes[0] = ata_sff_dev_classify(&link->device[0], devmask, &err);
  249. DPRINTK("classes[0]=%u\n", classes[0]);
  250. return 0;
  251. }
  252. static void sata_rcar_tf_load(struct ata_port *ap,
  253. const struct ata_taskfile *tf)
  254. {
  255. struct ata_ioports *ioaddr = &ap->ioaddr;
  256. unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
  257. if (tf->ctl != ap->last_ctl) {
  258. iowrite32(tf->ctl, ioaddr->ctl_addr);
  259. ap->last_ctl = tf->ctl;
  260. ata_wait_idle(ap);
  261. }
  262. if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
  263. iowrite32(tf->hob_feature, ioaddr->feature_addr);
  264. iowrite32(tf->hob_nsect, ioaddr->nsect_addr);
  265. iowrite32(tf->hob_lbal, ioaddr->lbal_addr);
  266. iowrite32(tf->hob_lbam, ioaddr->lbam_addr);
  267. iowrite32(tf->hob_lbah, ioaddr->lbah_addr);
  268. VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
  269. tf->hob_feature,
  270. tf->hob_nsect,
  271. tf->hob_lbal,
  272. tf->hob_lbam,
  273. tf->hob_lbah);
  274. }
  275. if (is_addr) {
  276. iowrite32(tf->feature, ioaddr->feature_addr);
  277. iowrite32(tf->nsect, ioaddr->nsect_addr);
  278. iowrite32(tf->lbal, ioaddr->lbal_addr);
  279. iowrite32(tf->lbam, ioaddr->lbam_addr);
  280. iowrite32(tf->lbah, ioaddr->lbah_addr);
  281. VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
  282. tf->feature,
  283. tf->nsect,
  284. tf->lbal,
  285. tf->lbam,
  286. tf->lbah);
  287. }
  288. if (tf->flags & ATA_TFLAG_DEVICE) {
  289. iowrite32(tf->device, ioaddr->device_addr);
  290. VPRINTK("device 0x%X\n", tf->device);
  291. }
  292. ata_wait_idle(ap);
  293. }
  294. static void sata_rcar_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
  295. {
  296. struct ata_ioports *ioaddr = &ap->ioaddr;
  297. tf->command = sata_rcar_check_status(ap);
  298. tf->feature = ioread32(ioaddr->error_addr);
  299. tf->nsect = ioread32(ioaddr->nsect_addr);
  300. tf->lbal = ioread32(ioaddr->lbal_addr);
  301. tf->lbam = ioread32(ioaddr->lbam_addr);
  302. tf->lbah = ioread32(ioaddr->lbah_addr);
  303. tf->device = ioread32(ioaddr->device_addr);
  304. if (tf->flags & ATA_TFLAG_LBA48) {
  305. iowrite32(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
  306. tf->hob_feature = ioread32(ioaddr->error_addr);
  307. tf->hob_nsect = ioread32(ioaddr->nsect_addr);
  308. tf->hob_lbal = ioread32(ioaddr->lbal_addr);
  309. tf->hob_lbam = ioread32(ioaddr->lbam_addr);
  310. tf->hob_lbah = ioread32(ioaddr->lbah_addr);
  311. iowrite32(tf->ctl, ioaddr->ctl_addr);
  312. ap->last_ctl = tf->ctl;
  313. }
  314. }
  315. static void sata_rcar_exec_command(struct ata_port *ap,
  316. const struct ata_taskfile *tf)
  317. {
  318. DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
  319. iowrite32(tf->command, ap->ioaddr.command_addr);
  320. ata_sff_pause(ap);
  321. }
  322. static unsigned int sata_rcar_data_xfer(struct ata_device *dev,
  323. unsigned char *buf,
  324. unsigned int buflen, int rw)
  325. {
  326. struct ata_port *ap = dev->link->ap;
  327. void __iomem *data_addr = ap->ioaddr.data_addr;
  328. unsigned int words = buflen >> 1;
  329. /* Transfer multiple of 2 bytes */
  330. if (rw == READ)
  331. sata_rcar_ioread16_rep(data_addr, buf, words);
  332. else
  333. sata_rcar_iowrite16_rep(data_addr, buf, words);
  334. /* Transfer trailing byte, if any. */
  335. if (unlikely(buflen & 0x01)) {
  336. unsigned char pad[2] = { };
  337. /* Point buf to the tail of buffer */
  338. buf += buflen - 1;
  339. /*
  340. * Use io*16_rep() accessors here as well to avoid pointlessly
  341. * swapping bytes to and from on the big endian machines...
  342. */
  343. if (rw == READ) {
  344. sata_rcar_ioread16_rep(data_addr, pad, 1);
  345. *buf = pad[0];
  346. } else {
  347. pad[0] = *buf;
  348. sata_rcar_iowrite16_rep(data_addr, pad, 1);
  349. }
  350. words++;
  351. }
  352. return words << 1;
  353. }
  354. static void sata_rcar_drain_fifo(struct ata_queued_cmd *qc)
  355. {
  356. int count;
  357. struct ata_port *ap;
  358. /* We only need to flush incoming data when a command was running */
  359. if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
  360. return;
  361. ap = qc->ap;
  362. /* Drain up to 64K of data before we give up this recovery method */
  363. for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) &&
  364. count < 65536; count += 2)
  365. ioread32(ap->ioaddr.data_addr);
  366. /* Can become DEBUG later */
  367. if (count)
  368. ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
  369. }
  370. static int sata_rcar_scr_read(struct ata_link *link, unsigned int sc_reg,
  371. u32 *val)
  372. {
  373. if (sc_reg > SCR_ACTIVE)
  374. return -EINVAL;
  375. *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg << 2));
  376. return 0;
  377. }
  378. static int sata_rcar_scr_write(struct ata_link *link, unsigned int sc_reg,
  379. u32 val)
  380. {
  381. if (sc_reg > SCR_ACTIVE)
  382. return -EINVAL;
  383. iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg << 2));
  384. return 0;
  385. }
  386. static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc)
  387. {
  388. struct ata_port *ap = qc->ap;
  389. struct ata_bmdma_prd *prd = ap->bmdma_prd;
  390. struct scatterlist *sg;
  391. unsigned int si, pi;
  392. pi = 0;
  393. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  394. u32 addr, sg_len, len;
  395. /*
  396. * Note: h/w doesn't support 64-bit, so we unconditionally
  397. * truncate dma_addr_t to u32.
  398. */
  399. addr = (u32)sg_dma_address(sg);
  400. sg_len = sg_dma_len(sg);
  401. /* H/w transfer count is only 29 bits long, let's be careful */
  402. while (sg_len) {
  403. len = sg_len;
  404. if (len > 0x1ffffffe)
  405. len = 0x1ffffffe;
  406. prd[pi].addr = cpu_to_le32(addr);
  407. prd[pi].flags_len = cpu_to_le32(len);
  408. VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
  409. pi++;
  410. sg_len -= len;
  411. addr += len;
  412. }
  413. }
  414. /* end-of-table flag */
  415. prd[pi - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND);
  416. }
  417. static void sata_rcar_qc_prep(struct ata_queued_cmd *qc)
  418. {
  419. if (!(qc->flags & ATA_QCFLAG_DMAMAP))
  420. return;
  421. sata_rcar_bmdma_fill_sg(qc);
  422. }
  423. static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc)
  424. {
  425. struct ata_port *ap = qc->ap;
  426. unsigned int rw = qc->tf.flags & ATA_TFLAG_WRITE;
  427. u32 dmactl;
  428. struct sata_rcar_priv *priv = ap->host->private_data;
  429. /* load PRD table addr. */
  430. mb(); /* make sure PRD table writes are visible to controller */
  431. iowrite32(ap->bmdma_prd_dma, priv->base + ATAPI_DTB_ADR_REG);
  432. /* specify data direction, triple-check start bit is clear */
  433. dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG);
  434. dmactl &= ~(ATAPI_CONTROL1_RW | ATAPI_CONTROL1_STOP);
  435. if (dmactl & ATAPI_CONTROL1_START) {
  436. dmactl &= ~ATAPI_CONTROL1_START;
  437. dmactl |= ATAPI_CONTROL1_STOP;
  438. }
  439. if (!rw)
  440. dmactl |= ATAPI_CONTROL1_RW;
  441. iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG);
  442. /* issue r/w command */
  443. ap->ops->sff_exec_command(ap, &qc->tf);
  444. }
  445. static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc)
  446. {
  447. struct ata_port *ap = qc->ap;
  448. u32 dmactl;
  449. struct sata_rcar_priv *priv = ap->host->private_data;
  450. /* start host DMA transaction */
  451. dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG);
  452. dmactl |= ATAPI_CONTROL1_START;
  453. iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG);
  454. }
  455. static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc)
  456. {
  457. struct ata_port *ap = qc->ap;
  458. struct sata_rcar_priv *priv = ap->host->private_data;
  459. u32 dmactl;
  460. /* force termination of DMA transfer if active */
  461. dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG);
  462. if (dmactl & ATAPI_CONTROL1_START) {
  463. dmactl &= ~ATAPI_CONTROL1_START;
  464. dmactl |= ATAPI_CONTROL1_STOP;
  465. iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG);
  466. }
  467. /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
  468. ata_sff_dma_pause(ap);
  469. }
  470. static u8 sata_rcar_bmdma_status(struct ata_port *ap)
  471. {
  472. struct sata_rcar_priv *priv = ap->host->private_data;
  473. u32 status;
  474. u8 host_stat = 0;
  475. status = ioread32(priv->base + ATAPI_STATUS_REG);
  476. if (status & ATAPI_STATUS_DEVINT)
  477. host_stat |= ATA_DMA_INTR;
  478. if (status & ATAPI_STATUS_ACT)
  479. host_stat |= ATA_DMA_ACTIVE;
  480. return host_stat;
  481. }
  482. static struct scsi_host_template sata_rcar_sht = {
  483. ATA_BMDMA_SHT(DRV_NAME),
  484. };
  485. static struct ata_port_operations sata_rcar_port_ops = {
  486. .inherits = &ata_bmdma_port_ops,
  487. .freeze = sata_rcar_freeze,
  488. .thaw = sata_rcar_thaw,
  489. .softreset = sata_rcar_softreset,
  490. .scr_read = sata_rcar_scr_read,
  491. .scr_write = sata_rcar_scr_write,
  492. .sff_dev_select = sata_rcar_dev_select,
  493. .sff_set_devctl = sata_rcar_set_devctl,
  494. .sff_check_status = sata_rcar_check_status,
  495. .sff_check_altstatus = sata_rcar_check_altstatus,
  496. .sff_tf_load = sata_rcar_tf_load,
  497. .sff_tf_read = sata_rcar_tf_read,
  498. .sff_exec_command = sata_rcar_exec_command,
  499. .sff_data_xfer = sata_rcar_data_xfer,
  500. .sff_drain_fifo = sata_rcar_drain_fifo,
  501. .qc_prep = sata_rcar_qc_prep,
  502. .bmdma_setup = sata_rcar_bmdma_setup,
  503. .bmdma_start = sata_rcar_bmdma_start,
  504. .bmdma_stop = sata_rcar_bmdma_stop,
  505. .bmdma_status = sata_rcar_bmdma_status,
  506. };
  507. static int sata_rcar_serr_interrupt(struct ata_port *ap)
  508. {
  509. struct sata_rcar_priv *priv = ap->host->private_data;
  510. struct ata_eh_info *ehi = &ap->link.eh_info;
  511. int freeze = 0;
  512. int handled = 0;
  513. u32 serror;
  514. serror = ioread32(priv->base + SCRSERR_REG);
  515. if (!serror)
  516. return 0;
  517. DPRINTK("SError @host_intr: 0x%x\n", serror);
  518. /* first, analyze and record host port events */
  519. ata_ehi_clear_desc(ehi);
  520. if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) {
  521. /* Setup a soft-reset EH action */
  522. ata_ehi_hotplugged(ehi);
  523. ata_ehi_push_desc(ehi, "%s", "hotplug");
  524. freeze = serror & SERR_COMM_WAKE ? 0 : 1;
  525. handled = 1;
  526. }
  527. /* freeze or abort */
  528. if (freeze)
  529. ata_port_freeze(ap);
  530. else
  531. ata_port_abort(ap);
  532. return handled;
  533. }
  534. static int sata_rcar_ata_interrupt(struct ata_port *ap)
  535. {
  536. struct ata_queued_cmd *qc;
  537. int handled = 0;
  538. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  539. if (qc)
  540. handled |= ata_bmdma_port_intr(ap, qc);
  541. return handled;
  542. }
  543. static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance)
  544. {
  545. struct ata_host *host = dev_instance;
  546. struct sata_rcar_priv *priv = host->private_data;
  547. struct ata_port *ap;
  548. unsigned int handled = 0;
  549. u32 sataintstat;
  550. unsigned long flags;
  551. spin_lock_irqsave(&host->lock, flags);
  552. sataintstat = ioread32(priv->base + SATAINTSTAT_REG);
  553. if (!sataintstat)
  554. goto done;
  555. /* ack */
  556. iowrite32(sataintstat & ~SATA_RCAR_INT_MASK,
  557. priv->base + SATAINTSTAT_REG);
  558. ap = host->ports[0];
  559. if (sataintstat & SATAINTSTAT_ATA)
  560. handled |= sata_rcar_ata_interrupt(ap);
  561. if (sataintstat & SATAINTSTAT_SERR)
  562. handled |= sata_rcar_serr_interrupt(ap);
  563. done:
  564. spin_unlock_irqrestore(&host->lock, flags);
  565. return IRQ_RETVAL(handled);
  566. }
  567. static void sata_rcar_setup_port(struct ata_host *host)
  568. {
  569. struct ata_port *ap = host->ports[0];
  570. struct ata_ioports *ioaddr = &ap->ioaddr;
  571. struct sata_rcar_priv *priv = host->private_data;
  572. ap->ops = &sata_rcar_port_ops;
  573. ap->pio_mask = ATA_PIO4;
  574. ap->udma_mask = ATA_UDMA6;
  575. ap->flags |= ATA_FLAG_SATA;
  576. ioaddr->cmd_addr = priv->base + SDATA_REG;
  577. ioaddr->ctl_addr = priv->base + SSDEVCON_REG;
  578. ioaddr->scr_addr = priv->base + SCRSSTS_REG;
  579. ioaddr->altstatus_addr = ioaddr->ctl_addr;
  580. ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2);
  581. ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << 2);
  582. ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << 2);
  583. ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << 2);
  584. ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << 2);
  585. ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << 2);
  586. ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << 2);
  587. ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << 2);
  588. ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << 2);
  589. ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << 2);
  590. }
  591. static void sata_rcar_init_controller(struct ata_host *host)
  592. {
  593. struct sata_rcar_priv *priv = host->private_data;
  594. u32 val;
  595. /* reset and setup phy */
  596. sata_rcar_phy_initialize(priv);
  597. sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0);
  598. sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1);
  599. sata_rcar_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0);
  600. sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0);
  601. sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1);
  602. sata_rcar_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0);
  603. /* SATA-IP reset state */
  604. val = ioread32(priv->base + ATAPI_CONTROL1_REG);
  605. val |= ATAPI_CONTROL1_RESET;
  606. iowrite32(val, priv->base + ATAPI_CONTROL1_REG);
  607. /* ISM mode, PRD mode, DTEND flag at bit 0 */
  608. val = ioread32(priv->base + ATAPI_CONTROL1_REG);
  609. val |= ATAPI_CONTROL1_ISM;
  610. val |= ATAPI_CONTROL1_DESE;
  611. val |= ATAPI_CONTROL1_DTA32M;
  612. iowrite32(val, priv->base + ATAPI_CONTROL1_REG);
  613. /* Release the SATA-IP from the reset state */
  614. val = ioread32(priv->base + ATAPI_CONTROL1_REG);
  615. val &= ~ATAPI_CONTROL1_RESET;
  616. iowrite32(val, priv->base + ATAPI_CONTROL1_REG);
  617. /* ack and mask */
  618. iowrite32(0, priv->base + SATAINTSTAT_REG);
  619. iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
  620. /* enable interrupts */
  621. iowrite32(ATAPI_INT_ENABLE_SATAINT, priv->base + ATAPI_INT_ENABLE_REG);
  622. }
  623. static int sata_rcar_probe(struct platform_device *pdev)
  624. {
  625. struct ata_host *host;
  626. struct sata_rcar_priv *priv;
  627. struct resource *mem;
  628. int irq;
  629. int ret = 0;
  630. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  631. if (mem == NULL)
  632. return -EINVAL;
  633. irq = platform_get_irq(pdev, 0);
  634. if (irq <= 0)
  635. return -EINVAL;
  636. priv = devm_kzalloc(&pdev->dev, sizeof(struct sata_rcar_priv),
  637. GFP_KERNEL);
  638. if (!priv)
  639. return -ENOMEM;
  640. priv->clk = devm_clk_get(&pdev->dev, NULL);
  641. if (IS_ERR(priv->clk)) {
  642. dev_err(&pdev->dev, "failed to get access to sata clock\n");
  643. return PTR_ERR(priv->clk);
  644. }
  645. clk_enable(priv->clk);
  646. host = ata_host_alloc(&pdev->dev, 1);
  647. if (!host) {
  648. dev_err(&pdev->dev, "ata_host_alloc failed\n");
  649. ret = -ENOMEM;
  650. goto cleanup;
  651. }
  652. host->private_data = priv;
  653. priv->base = devm_ioremap_resource(&pdev->dev, mem);
  654. if (IS_ERR(priv->base)) {
  655. ret = PTR_ERR(priv->base);
  656. goto cleanup;
  657. }
  658. /* setup port */
  659. sata_rcar_setup_port(host);
  660. /* initialize host controller */
  661. sata_rcar_init_controller(host);
  662. ret = ata_host_activate(host, irq, sata_rcar_interrupt, 0,
  663. &sata_rcar_sht);
  664. if (!ret)
  665. return 0;
  666. cleanup:
  667. clk_disable(priv->clk);
  668. return ret;
  669. }
  670. static int sata_rcar_remove(struct platform_device *pdev)
  671. {
  672. struct ata_host *host = dev_get_drvdata(&pdev->dev);
  673. struct sata_rcar_priv *priv = host->private_data;
  674. ata_host_detach(host);
  675. /* disable interrupts */
  676. iowrite32(0, priv->base + ATAPI_INT_ENABLE_REG);
  677. /* ack and mask */
  678. iowrite32(0, priv->base + SATAINTSTAT_REG);
  679. iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
  680. clk_disable(priv->clk);
  681. return 0;
  682. }
  683. #ifdef CONFIG_PM
  684. static int sata_rcar_suspend(struct device *dev)
  685. {
  686. struct ata_host *host = dev_get_drvdata(dev);
  687. struct sata_rcar_priv *priv = host->private_data;
  688. int ret;
  689. ret = ata_host_suspend(host, PMSG_SUSPEND);
  690. if (!ret) {
  691. /* disable interrupts */
  692. iowrite32(0, priv->base + ATAPI_INT_ENABLE_REG);
  693. /* mask */
  694. iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
  695. clk_disable(priv->clk);
  696. }
  697. return ret;
  698. }
  699. static int sata_rcar_resume(struct device *dev)
  700. {
  701. struct ata_host *host = dev_get_drvdata(dev);
  702. struct sata_rcar_priv *priv = host->private_data;
  703. clk_enable(priv->clk);
  704. /* ack and mask */
  705. iowrite32(0, priv->base + SATAINTSTAT_REG);
  706. iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
  707. /* enable interrupts */
  708. iowrite32(ATAPI_INT_ENABLE_SATAINT, priv->base + ATAPI_INT_ENABLE_REG);
  709. ata_host_resume(host);
  710. return 0;
  711. }
  712. static const struct dev_pm_ops sata_rcar_pm_ops = {
  713. .suspend = sata_rcar_suspend,
  714. .resume = sata_rcar_resume,
  715. };
  716. #endif
  717. static struct of_device_id sata_rcar_match[] = {
  718. { .compatible = "renesas,rcar-sata", },
  719. {},
  720. };
  721. MODULE_DEVICE_TABLE(of, sata_rcar_match);
  722. static struct platform_driver sata_rcar_driver = {
  723. .probe = sata_rcar_probe,
  724. .remove = sata_rcar_remove,
  725. .driver = {
  726. .name = DRV_NAME,
  727. .owner = THIS_MODULE,
  728. .of_match_table = sata_rcar_match,
  729. #ifdef CONFIG_PM
  730. .pm = &sata_rcar_pm_ops,
  731. #endif
  732. },
  733. };
  734. module_platform_driver(sata_rcar_driver);
  735. MODULE_LICENSE("GPL");
  736. MODULE_AUTHOR("Vladimir Barinov");
  737. MODULE_DESCRIPTION("Renesas R-Car SATA controller low level driver");