pci-p5ioc2.c 6.5 KB

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  1. /*
  2. * Support PCI/PCIe on PowerNV platforms
  3. *
  4. * Currently supports only P5IOC2
  5. *
  6. * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * as published by the Free Software Foundation; either version
  11. * 2 of the License, or (at your option) any later version.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/pci.h>
  15. #include <linux/delay.h>
  16. #include <linux/string.h>
  17. #include <linux/init.h>
  18. #include <linux/bootmem.h>
  19. #include <linux/irq.h>
  20. #include <linux/io.h>
  21. #include <linux/msi.h>
  22. #include <asm/sections.h>
  23. #include <asm/io.h>
  24. #include <asm/prom.h>
  25. #include <asm/pci-bridge.h>
  26. #include <asm/machdep.h>
  27. #include <asm/msi_bitmap.h>
  28. #include <asm/ppc-pci.h>
  29. #include <asm/opal.h>
  30. #include <asm/iommu.h>
  31. #include <asm/tce.h>
  32. #include "powernv.h"
  33. #include "pci.h"
  34. /* For now, use a fixed amount of TCE memory for each p5ioc2
  35. * hub, 16M will do
  36. */
  37. #define P5IOC2_TCE_MEMORY 0x01000000
  38. #ifdef CONFIG_PCI_MSI
  39. static int pnv_pci_p5ioc2_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
  40. unsigned int hwirq, unsigned int virq,
  41. unsigned int is_64, struct msi_msg *msg)
  42. {
  43. if (WARN_ON(!is_64))
  44. return -ENXIO;
  45. msg->data = hwirq - phb->msi_base;
  46. msg->address_hi = 0x10000000;
  47. msg->address_lo = 0;
  48. return 0;
  49. }
  50. static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb)
  51. {
  52. unsigned int count;
  53. const __be32 *prop = of_get_property(phb->hose->dn,
  54. "ibm,opal-msi-ranges", NULL);
  55. if (!prop)
  56. return;
  57. /* Don't do MSI's on p5ioc2 PCI-X are they are not properly
  58. * verified in HW
  59. */
  60. if (of_device_is_compatible(phb->hose->dn, "ibm,p5ioc2-pcix"))
  61. return;
  62. phb->msi_base = be32_to_cpup(prop);
  63. count = be32_to_cpup(prop + 1);
  64. if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
  65. pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
  66. phb->hose->global_number);
  67. return;
  68. }
  69. phb->msi_setup = pnv_pci_p5ioc2_msi_setup;
  70. phb->msi32_support = 0;
  71. pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
  72. count, phb->msi_base);
  73. }
  74. #else
  75. static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb) { }
  76. #endif /* CONFIG_PCI_MSI */
  77. static void pnv_pci_p5ioc2_dma_dev_setup(struct pnv_phb *phb,
  78. struct pci_dev *pdev)
  79. {
  80. if (phb->p5ioc2.iommu_table.it_map == NULL)
  81. iommu_init_table(&phb->p5ioc2.iommu_table, phb->hose->node);
  82. set_iommu_table_base(&pdev->dev, &phb->p5ioc2.iommu_table);
  83. }
  84. static void __init pnv_pci_init_p5ioc2_phb(struct device_node *np,
  85. void *tce_mem, u64 tce_size)
  86. {
  87. struct pnv_phb *phb;
  88. const u64 *prop64;
  89. u64 phb_id;
  90. int64_t rc;
  91. static int primary = 1;
  92. pr_info(" Initializing p5ioc2 PHB %s\n", np->full_name);
  93. prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
  94. if (!prop64) {
  95. pr_err(" Missing \"ibm,opal-phbid\" property !\n");
  96. return;
  97. }
  98. phb_id = be64_to_cpup(prop64);
  99. pr_devel(" PHB-ID : 0x%016llx\n", phb_id);
  100. pr_devel(" TCE AT : 0x%016lx\n", __pa(tce_mem));
  101. pr_devel(" TCE SZ : 0x%016llx\n", tce_size);
  102. rc = opal_pci_set_phb_tce_memory(phb_id, __pa(tce_mem), tce_size);
  103. if (rc != OPAL_SUCCESS) {
  104. pr_err(" Failed to set TCE memory, OPAL error %lld\n", rc);
  105. return;
  106. }
  107. phb = alloc_bootmem(sizeof(struct pnv_phb));
  108. if (phb) {
  109. memset(phb, 0, sizeof(struct pnv_phb));
  110. phb->hose = pcibios_alloc_controller(np);
  111. }
  112. if (!phb || !phb->hose) {
  113. pr_err(" Failed to allocate PCI controller\n");
  114. return;
  115. }
  116. spin_lock_init(&phb->lock);
  117. phb->hose->first_busno = 0;
  118. phb->hose->last_busno = 0xff;
  119. phb->hose->private_data = phb;
  120. phb->opal_id = phb_id;
  121. phb->type = PNV_PHB_P5IOC2;
  122. phb->model = PNV_PHB_MODEL_P5IOC2;
  123. phb->regs = of_iomap(np, 0);
  124. if (phb->regs == NULL)
  125. pr_err(" Failed to map registers !\n");
  126. else {
  127. pr_devel(" P_BUID = 0x%08x\n", in_be32(phb->regs + 0x100));
  128. pr_devel(" P_IOSZ = 0x%08x\n", in_be32(phb->regs + 0x1b0));
  129. pr_devel(" P_IO_ST = 0x%08x\n", in_be32(phb->regs + 0x1e0));
  130. pr_devel(" P_MEM1_H = 0x%08x\n", in_be32(phb->regs + 0x1a0));
  131. pr_devel(" P_MEM1_L = 0x%08x\n", in_be32(phb->regs + 0x190));
  132. pr_devel(" P_MSZ1_L = 0x%08x\n", in_be32(phb->regs + 0x1c0));
  133. pr_devel(" P_MEM_ST = 0x%08x\n", in_be32(phb->regs + 0x1d0));
  134. pr_devel(" P_MEM2_H = 0x%08x\n", in_be32(phb->regs + 0x2c0));
  135. pr_devel(" P_MEM2_L = 0x%08x\n", in_be32(phb->regs + 0x2b0));
  136. pr_devel(" P_MSZ2_H = 0x%08x\n", in_be32(phb->regs + 0x2d0));
  137. pr_devel(" P_MSZ2_L = 0x%08x\n", in_be32(phb->regs + 0x2e0));
  138. }
  139. /* Interpret the "ranges" property */
  140. /* This also maps the I/O region and sets isa_io/mem_base */
  141. pci_process_bridge_OF_ranges(phb->hose, np, primary);
  142. primary = 0;
  143. phb->hose->ops = &pnv_pci_ops;
  144. /* Setup MSI support */
  145. pnv_pci_init_p5ioc2_msis(phb);
  146. /* Setup TCEs */
  147. phb->dma_dev_setup = pnv_pci_p5ioc2_dma_dev_setup;
  148. pnv_pci_setup_iommu_table(&phb->p5ioc2.iommu_table,
  149. tce_mem, tce_size, 0);
  150. }
  151. void __init pnv_pci_init_p5ioc2_hub(struct device_node *np)
  152. {
  153. struct device_node *phbn;
  154. const u64 *prop64;
  155. u64 hub_id;
  156. void *tce_mem;
  157. uint64_t tce_per_phb;
  158. int64_t rc;
  159. int phb_count = 0;
  160. pr_info("Probing p5ioc2 IO-Hub %s\n", np->full_name);
  161. prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
  162. if (!prop64) {
  163. pr_err(" Missing \"ibm,opal-hubid\" property !\n");
  164. return;
  165. }
  166. hub_id = be64_to_cpup(prop64);
  167. pr_info(" HUB-ID : 0x%016llx\n", hub_id);
  168. /* Currently allocate 16M of TCE memory for every Hub
  169. *
  170. * XXX TODO: Make it chip local if possible
  171. */
  172. tce_mem = __alloc_bootmem(P5IOC2_TCE_MEMORY, P5IOC2_TCE_MEMORY,
  173. __pa(MAX_DMA_ADDRESS));
  174. if (!tce_mem) {
  175. pr_err(" Failed to allocate TCE Memory !\n");
  176. return;
  177. }
  178. pr_debug(" TCE : 0x%016lx..0x%016lx\n",
  179. __pa(tce_mem), __pa(tce_mem) + P5IOC2_TCE_MEMORY - 1);
  180. rc = opal_pci_set_hub_tce_memory(hub_id, __pa(tce_mem),
  181. P5IOC2_TCE_MEMORY);
  182. if (rc != OPAL_SUCCESS) {
  183. pr_err(" Failed to allocate TCE memory, OPAL error %lld\n", rc);
  184. return;
  185. }
  186. /* Count child PHBs */
  187. for_each_child_of_node(np, phbn) {
  188. if (of_device_is_compatible(phbn, "ibm,p5ioc2-pcix") ||
  189. of_device_is_compatible(phbn, "ibm,p5ioc2-pciex"))
  190. phb_count++;
  191. }
  192. /* Calculate how much TCE space we can give per PHB */
  193. tce_per_phb = __rounddown_pow_of_two(P5IOC2_TCE_MEMORY / phb_count);
  194. pr_info(" Allocating %lld MB of TCE memory per PHB\n",
  195. tce_per_phb >> 20);
  196. /* Initialize PHBs */
  197. for_each_child_of_node(np, phbn) {
  198. if (of_device_is_compatible(phbn, "ibm,p5ioc2-pcix") ||
  199. of_device_is_compatible(phbn, "ibm,p5ioc2-pciex")) {
  200. pnv_pci_init_p5ioc2_phb(phbn, tce_mem, tce_per_phb);
  201. tce_mem += tce_per_phb;
  202. }
  203. }
  204. }