io.h 25 KB

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  1. #ifndef _ASM_POWERPC_IO_H
  2. #define _ASM_POWERPC_IO_H
  3. #ifdef __KERNEL__
  4. #define ARCH_HAS_IOREMAP_WC
  5. /*
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. */
  11. /* Check of existence of legacy devices */
  12. extern int check_legacy_ioport(unsigned long base_port);
  13. #define I8042_DATA_REG 0x60
  14. #define FDC_BASE 0x3f0
  15. #if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
  16. extern struct pci_dev *isa_bridge_pcidev;
  17. /*
  18. * has legacy ISA devices ?
  19. */
  20. #define arch_has_dev_port() (isa_bridge_pcidev != NULL)
  21. #endif
  22. #include <linux/device.h>
  23. #include <linux/io.h>
  24. #include <linux/compiler.h>
  25. #include <asm/page.h>
  26. #include <asm/byteorder.h>
  27. #include <asm/synch.h>
  28. #include <asm/delay.h>
  29. #include <asm/mmu.h>
  30. #include <asm-generic/iomap.h>
  31. #ifdef CONFIG_PPC64
  32. #include <asm/paca.h>
  33. #endif
  34. #define SIO_CONFIG_RA 0x398
  35. #define SIO_CONFIG_RD 0x399
  36. #define SLOW_DOWN_IO
  37. /* 32 bits uses slightly different variables for the various IO
  38. * bases. Most of this file only uses _IO_BASE though which we
  39. * define properly based on the platform
  40. */
  41. #ifndef CONFIG_PCI
  42. #define _IO_BASE 0
  43. #define _ISA_MEM_BASE 0
  44. #define PCI_DRAM_OFFSET 0
  45. #elif defined(CONFIG_PPC32)
  46. #define _IO_BASE isa_io_base
  47. #define _ISA_MEM_BASE isa_mem_base
  48. #define PCI_DRAM_OFFSET pci_dram_offset
  49. #else
  50. #define _IO_BASE pci_io_base
  51. #define _ISA_MEM_BASE isa_mem_base
  52. #define PCI_DRAM_OFFSET 0
  53. #endif
  54. extern unsigned long isa_io_base;
  55. extern unsigned long pci_io_base;
  56. extern unsigned long pci_dram_offset;
  57. extern resource_size_t isa_mem_base;
  58. #if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO)
  59. #error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits
  60. #endif
  61. /*
  62. *
  63. * Low level MMIO accessors
  64. *
  65. * This provides the non-bus specific accessors to MMIO. Those are PowerPC
  66. * specific and thus shouldn't be used in generic code. The accessors
  67. * provided here are:
  68. *
  69. * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
  70. * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
  71. * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
  72. *
  73. * Those operate directly on a kernel virtual address. Note that the prototype
  74. * for the out_* accessors has the arguments in opposite order from the usual
  75. * linux PCI accessors. Unlike those, they take the address first and the value
  76. * next.
  77. *
  78. * Note: I might drop the _ns suffix on the stream operations soon as it is
  79. * simply normal for stream operations to not swap in the first place.
  80. *
  81. */
  82. #ifdef CONFIG_PPC64
  83. #define IO_SET_SYNC_FLAG() do { local_paca->io_sync = 1; } while(0)
  84. #else
  85. #define IO_SET_SYNC_FLAG()
  86. #endif
  87. /* gcc 4.0 and older doesn't have 'Z' constraint */
  88. #if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0)
  89. #define DEF_MMIO_IN_LE(name, size, insn) \
  90. static inline u##size name(const volatile u##size __iomem *addr) \
  91. { \
  92. u##size ret; \
  93. __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync" \
  94. : "=r" (ret) : "r" (addr), "m" (*addr) : "memory"); \
  95. return ret; \
  96. }
  97. #define DEF_MMIO_OUT_LE(name, size, insn) \
  98. static inline void name(volatile u##size __iomem *addr, u##size val) \
  99. { \
  100. __asm__ __volatile__("sync;"#insn" %1,0,%2" \
  101. : "=m" (*addr) : "r" (val), "r" (addr) : "memory"); \
  102. IO_SET_SYNC_FLAG(); \
  103. }
  104. #else /* newer gcc */
  105. #define DEF_MMIO_IN_LE(name, size, insn) \
  106. static inline u##size name(const volatile u##size __iomem *addr) \
  107. { \
  108. u##size ret; \
  109. __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \
  110. : "=r" (ret) : "Z" (*addr) : "memory"); \
  111. return ret; \
  112. }
  113. #define DEF_MMIO_OUT_LE(name, size, insn) \
  114. static inline void name(volatile u##size __iomem *addr, u##size val) \
  115. { \
  116. __asm__ __volatile__("sync;"#insn" %1,%y0" \
  117. : "=Z" (*addr) : "r" (val) : "memory"); \
  118. IO_SET_SYNC_FLAG(); \
  119. }
  120. #endif
  121. #define DEF_MMIO_IN_BE(name, size, insn) \
  122. static inline u##size name(const volatile u##size __iomem *addr) \
  123. { \
  124. u##size ret; \
  125. __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
  126. : "=r" (ret) : "m" (*addr) : "memory"); \
  127. return ret; \
  128. }
  129. #define DEF_MMIO_OUT_BE(name, size, insn) \
  130. static inline void name(volatile u##size __iomem *addr, u##size val) \
  131. { \
  132. __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \
  133. : "=m" (*addr) : "r" (val) : "memory"); \
  134. IO_SET_SYNC_FLAG(); \
  135. }
  136. DEF_MMIO_IN_BE(in_8, 8, lbz);
  137. DEF_MMIO_IN_BE(in_be16, 16, lhz);
  138. DEF_MMIO_IN_BE(in_be32, 32, lwz);
  139. DEF_MMIO_IN_LE(in_le16, 16, lhbrx);
  140. DEF_MMIO_IN_LE(in_le32, 32, lwbrx);
  141. DEF_MMIO_OUT_BE(out_8, 8, stb);
  142. DEF_MMIO_OUT_BE(out_be16, 16, sth);
  143. DEF_MMIO_OUT_BE(out_be32, 32, stw);
  144. DEF_MMIO_OUT_LE(out_le16, 16, sthbrx);
  145. DEF_MMIO_OUT_LE(out_le32, 32, stwbrx);
  146. #ifdef __powerpc64__
  147. DEF_MMIO_OUT_BE(out_be64, 64, std);
  148. DEF_MMIO_IN_BE(in_be64, 64, ld);
  149. /* There is no asm instructions for 64 bits reverse loads and stores */
  150. static inline u64 in_le64(const volatile u64 __iomem *addr)
  151. {
  152. return swab64(in_be64(addr));
  153. }
  154. static inline void out_le64(volatile u64 __iomem *addr, u64 val)
  155. {
  156. out_be64(addr, swab64(val));
  157. }
  158. #endif /* __powerpc64__ */
  159. /*
  160. * Low level IO stream instructions are defined out of line for now
  161. */
  162. extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
  163. extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
  164. extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
  165. extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
  166. extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
  167. extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
  168. /* The _ns naming is historical and will be removed. For now, just #define
  169. * the non _ns equivalent names
  170. */
  171. #define _insw _insw_ns
  172. #define _insl _insl_ns
  173. #define _outsw _outsw_ns
  174. #define _outsl _outsl_ns
  175. /*
  176. * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
  177. */
  178. extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
  179. extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
  180. unsigned long n);
  181. extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
  182. unsigned long n);
  183. /*
  184. *
  185. * PCI and standard ISA accessors
  186. *
  187. * Those are globally defined linux accessors for devices on PCI or ISA
  188. * busses. They follow the Linux defined semantics. The current implementation
  189. * for PowerPC is as close as possible to the x86 version of these, and thus
  190. * provides fairly heavy weight barriers for the non-raw versions
  191. *
  192. * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_IO
  193. * allowing the platform to provide its own implementation of some or all
  194. * of the accessors.
  195. */
  196. /*
  197. * Include the EEH definitions when EEH is enabled only so they don't get
  198. * in the way when building for 32 bits
  199. */
  200. #ifdef CONFIG_EEH
  201. #include <asm/eeh.h>
  202. #endif
  203. /* Shortcut to the MMIO argument pointer */
  204. #define PCI_IO_ADDR volatile void __iomem *
  205. /* Indirect IO address tokens:
  206. *
  207. * When CONFIG_PPC_INDIRECT_IO is set, the platform can provide hooks
  208. * on all IOs. (Note that this is all 64 bits only for now)
  209. *
  210. * To help platforms who may need to differenciate MMIO addresses in
  211. * their hooks, a bitfield is reserved for use by the platform near the
  212. * top of MMIO addresses (not PIO, those have to cope the hard way).
  213. *
  214. * This bit field is 12 bits and is at the top of the IO virtual
  215. * addresses PCI_IO_INDIRECT_TOKEN_MASK.
  216. *
  217. * The kernel virtual space is thus:
  218. *
  219. * 0xD000000000000000 : vmalloc
  220. * 0xD000080000000000 : PCI PHB IO space
  221. * 0xD000080080000000 : ioremap
  222. * 0xD0000fffffffffff : end of ioremap region
  223. *
  224. * Since the top 4 bits are reserved as the region ID, we use thus
  225. * the next 12 bits and keep 4 bits available for the future if the
  226. * virtual address space is ever to be extended.
  227. *
  228. * The direct IO mapping operations will then mask off those bits
  229. * before doing the actual access, though that only happen when
  230. * CONFIG_PPC_INDIRECT_IO is set, thus be careful when you use that
  231. * mechanism
  232. */
  233. #ifdef CONFIG_PPC_INDIRECT_IO
  234. #define PCI_IO_IND_TOKEN_MASK 0x0fff000000000000ul
  235. #define PCI_IO_IND_TOKEN_SHIFT 48
  236. #define PCI_FIX_ADDR(addr) \
  237. ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
  238. #define PCI_GET_ADDR_TOKEN(addr) \
  239. (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
  240. PCI_IO_IND_TOKEN_SHIFT)
  241. #define PCI_SET_ADDR_TOKEN(addr, token) \
  242. do { \
  243. unsigned long __a = (unsigned long)(addr); \
  244. __a &= ~PCI_IO_IND_TOKEN_MASK; \
  245. __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \
  246. (addr) = (void __iomem *)__a; \
  247. } while(0)
  248. #else
  249. #define PCI_FIX_ADDR(addr) (addr)
  250. #endif
  251. /*
  252. * Non ordered and non-swapping "raw" accessors
  253. */
  254. static inline unsigned char __raw_readb(const volatile void __iomem *addr)
  255. {
  256. return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
  257. }
  258. static inline unsigned short __raw_readw(const volatile void __iomem *addr)
  259. {
  260. return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
  261. }
  262. static inline unsigned int __raw_readl(const volatile void __iomem *addr)
  263. {
  264. return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
  265. }
  266. static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
  267. {
  268. *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
  269. }
  270. static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
  271. {
  272. *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
  273. }
  274. static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
  275. {
  276. *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
  277. }
  278. #ifdef __powerpc64__
  279. static inline unsigned long __raw_readq(const volatile void __iomem *addr)
  280. {
  281. return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
  282. }
  283. static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
  284. {
  285. *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
  286. }
  287. #endif /* __powerpc64__ */
  288. /*
  289. *
  290. * PCI PIO and MMIO accessors.
  291. *
  292. *
  293. * On 32 bits, PIO operations have a recovery mechanism in case they trigger
  294. * machine checks (which they occasionally do when probing non existing
  295. * IO ports on some platforms, like PowerMac and 8xx).
  296. * I always found it to be of dubious reliability and I am tempted to get
  297. * rid of it one of these days. So if you think it's important to keep it,
  298. * please voice up asap. We never had it for 64 bits and I do not intend
  299. * to port it over
  300. */
  301. #ifdef CONFIG_PPC32
  302. #define __do_in_asm(name, op) \
  303. static inline unsigned int name(unsigned int port) \
  304. { \
  305. unsigned int x; \
  306. __asm__ __volatile__( \
  307. "sync\n" \
  308. "0:" op " %0,0,%1\n" \
  309. "1: twi 0,%0,0\n" \
  310. "2: isync\n" \
  311. "3: nop\n" \
  312. "4:\n" \
  313. ".section .fixup,\"ax\"\n" \
  314. "5: li %0,-1\n" \
  315. " b 4b\n" \
  316. ".previous\n" \
  317. ".section __ex_table,\"a\"\n" \
  318. " .align 2\n" \
  319. " .long 0b,5b\n" \
  320. " .long 1b,5b\n" \
  321. " .long 2b,5b\n" \
  322. " .long 3b,5b\n" \
  323. ".previous" \
  324. : "=&r" (x) \
  325. : "r" (port + _IO_BASE) \
  326. : "memory"); \
  327. return x; \
  328. }
  329. #define __do_out_asm(name, op) \
  330. static inline void name(unsigned int val, unsigned int port) \
  331. { \
  332. __asm__ __volatile__( \
  333. "sync\n" \
  334. "0:" op " %0,0,%1\n" \
  335. "1: sync\n" \
  336. "2:\n" \
  337. ".section __ex_table,\"a\"\n" \
  338. " .align 2\n" \
  339. " .long 0b,2b\n" \
  340. " .long 1b,2b\n" \
  341. ".previous" \
  342. : : "r" (val), "r" (port + _IO_BASE) \
  343. : "memory"); \
  344. }
  345. __do_in_asm(_rec_inb, "lbzx")
  346. __do_in_asm(_rec_inw, "lhbrx")
  347. __do_in_asm(_rec_inl, "lwbrx")
  348. __do_out_asm(_rec_outb, "stbx")
  349. __do_out_asm(_rec_outw, "sthbrx")
  350. __do_out_asm(_rec_outl, "stwbrx")
  351. #endif /* CONFIG_PPC32 */
  352. /* The "__do_*" operations below provide the actual "base" implementation
  353. * for each of the defined accessors. Some of them use the out_* functions
  354. * directly, some of them still use EEH, though we might change that in the
  355. * future. Those macros below provide the necessary argument swapping and
  356. * handling of the IO base for PIO.
  357. *
  358. * They are themselves used by the macros that define the actual accessors
  359. * and can be used by the hooks if any.
  360. *
  361. * Note that PIO operations are always defined in terms of their corresonding
  362. * MMIO operations. That allows platforms like iSeries who want to modify the
  363. * behaviour of both to only hook on the MMIO version and get both. It's also
  364. * possible to hook directly at the toplevel PIO operation if they have to
  365. * be handled differently
  366. */
  367. #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val)
  368. #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val)
  369. #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val)
  370. #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val)
  371. #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
  372. #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
  373. #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
  374. #ifdef CONFIG_EEH
  375. #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
  376. #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
  377. #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
  378. #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr))
  379. #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
  380. #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
  381. #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
  382. #else /* CONFIG_EEH */
  383. #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
  384. #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
  385. #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
  386. #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
  387. #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
  388. #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
  389. #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
  390. #endif /* !defined(CONFIG_EEH) */
  391. #ifdef CONFIG_PPC32
  392. #define __do_outb(val, port) _rec_outb(val, port)
  393. #define __do_outw(val, port) _rec_outw(val, port)
  394. #define __do_outl(val, port) _rec_outl(val, port)
  395. #define __do_inb(port) _rec_inb(port)
  396. #define __do_inw(port) _rec_inw(port)
  397. #define __do_inl(port) _rec_inl(port)
  398. #else /* CONFIG_PPC32 */
  399. #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
  400. #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port);
  401. #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port);
  402. #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port);
  403. #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port);
  404. #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port);
  405. #endif /* !CONFIG_PPC32 */
  406. #ifdef CONFIG_EEH
  407. #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
  408. #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
  409. #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
  410. #else /* CONFIG_EEH */
  411. #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
  412. #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
  413. #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
  414. #endif /* !CONFIG_EEH */
  415. #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
  416. #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
  417. #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
  418. #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
  419. #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
  420. #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
  421. #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
  422. #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
  423. #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
  424. #define __do_memset_io(addr, c, n) \
  425. _memset_io(PCI_FIX_ADDR(addr), c, n)
  426. #define __do_memcpy_toio(dst, src, n) \
  427. _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
  428. #ifdef CONFIG_EEH
  429. #define __do_memcpy_fromio(dst, src, n) \
  430. eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
  431. #else /* CONFIG_EEH */
  432. #define __do_memcpy_fromio(dst, src, n) \
  433. _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
  434. #endif /* !CONFIG_EEH */
  435. #ifdef CONFIG_PPC_INDIRECT_PIO
  436. #define DEF_PCI_HOOK_pio(x) x
  437. #else
  438. #define DEF_PCI_HOOK_pio(x) NULL
  439. #endif
  440. #ifdef CONFIG_PPC_INDIRECT_MMIO
  441. #define DEF_PCI_HOOK_mem(x) x
  442. #else
  443. #define DEF_PCI_HOOK_mem(x) NULL
  444. #endif
  445. /* Structure containing all the hooks */
  446. extern struct ppc_pci_io {
  447. #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at;
  448. #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at;
  449. #include <asm/io-defs.h>
  450. #undef DEF_PCI_AC_RET
  451. #undef DEF_PCI_AC_NORET
  452. } ppc_pci_io;
  453. /* The inline wrappers */
  454. #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
  455. static inline ret name at \
  456. { \
  457. if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
  458. return ppc_pci_io.name al; \
  459. return __do_##name al; \
  460. }
  461. #define DEF_PCI_AC_NORET(name, at, al, space, aa) \
  462. static inline void name at \
  463. { \
  464. if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
  465. ppc_pci_io.name al; \
  466. else \
  467. __do_##name al; \
  468. }
  469. #include <asm/io-defs.h>
  470. #undef DEF_PCI_AC_RET
  471. #undef DEF_PCI_AC_NORET
  472. /* Some drivers check for the presence of readq & writeq with
  473. * a #ifdef, so we make them happy here.
  474. */
  475. #ifdef __powerpc64__
  476. #define readq readq
  477. #define writeq writeq
  478. #endif
  479. /*
  480. * Convert a physical pointer to a virtual kernel pointer for /dev/mem
  481. * access
  482. */
  483. #define xlate_dev_mem_ptr(p) __va(p)
  484. /*
  485. * Convert a virtual cached pointer to an uncached pointer
  486. */
  487. #define xlate_dev_kmem_ptr(p) p
  488. /*
  489. * We don't do relaxed operations yet, at least not with this semantic
  490. */
  491. #define readb_relaxed(addr) readb(addr)
  492. #define readw_relaxed(addr) readw(addr)
  493. #define readl_relaxed(addr) readl(addr)
  494. #define readq_relaxed(addr) readq(addr)
  495. #ifdef CONFIG_PPC32
  496. #define mmiowb()
  497. #else
  498. /*
  499. * Enforce synchronisation of stores vs. spin_unlock
  500. * (this does it explicitly, though our implementation of spin_unlock
  501. * does it implicitely too)
  502. */
  503. static inline void mmiowb(void)
  504. {
  505. unsigned long tmp;
  506. __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)"
  507. : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync))
  508. : "memory");
  509. }
  510. #endif /* !CONFIG_PPC32 */
  511. static inline void iosync(void)
  512. {
  513. __asm__ __volatile__ ("sync" : : : "memory");
  514. }
  515. /* Enforce in-order execution of data I/O.
  516. * No distinction between read/write on PPC; use eieio for all three.
  517. * Those are fairly week though. They don't provide a barrier between
  518. * MMIO and cacheable storage nor do they provide a barrier vs. locks,
  519. * they only provide barriers between 2 __raw MMIO operations and
  520. * possibly break write combining.
  521. */
  522. #define iobarrier_rw() eieio()
  523. #define iobarrier_r() eieio()
  524. #define iobarrier_w() eieio()
  525. /*
  526. * output pause versions need a delay at least for the
  527. * w83c105 ide controller in a p610.
  528. */
  529. #define inb_p(port) inb(port)
  530. #define outb_p(val, port) (udelay(1), outb((val), (port)))
  531. #define inw_p(port) inw(port)
  532. #define outw_p(val, port) (udelay(1), outw((val), (port)))
  533. #define inl_p(port) inl(port)
  534. #define outl_p(val, port) (udelay(1), outl((val), (port)))
  535. #define IO_SPACE_LIMIT ~(0UL)
  536. /**
  537. * ioremap - map bus memory into CPU space
  538. * @address: bus address of the memory
  539. * @size: size of the resource to map
  540. *
  541. * ioremap performs a platform specific sequence of operations to
  542. * make bus memory CPU accessible via the readb/readw/readl/writeb/
  543. * writew/writel functions and the other mmio helpers. The returned
  544. * address is not guaranteed to be usable directly as a virtual
  545. * address.
  546. *
  547. * We provide a few variations of it:
  548. *
  549. * * ioremap is the standard one and provides non-cacheable guarded mappings
  550. * and can be hooked by the platform via ppc_md
  551. *
  552. * * ioremap_prot allows to specify the page flags as an argument and can
  553. * also be hooked by the platform via ppc_md.
  554. *
  555. * * ioremap_nocache is identical to ioremap
  556. *
  557. * * ioremap_wc enables write combining
  558. *
  559. * * iounmap undoes such a mapping and can be hooked
  560. *
  561. * * __ioremap_at (and the pending __iounmap_at) are low level functions to
  562. * create hand-made mappings for use only by the PCI code and cannot
  563. * currently be hooked. Must be page aligned.
  564. *
  565. * * __ioremap is the low level implementation used by ioremap and
  566. * ioremap_prot and cannot be hooked (but can be used by a hook on one
  567. * of the previous ones)
  568. *
  569. * * __ioremap_caller is the same as above but takes an explicit caller
  570. * reference rather than using __builtin_return_address(0)
  571. *
  572. * * __iounmap, is the low level implementation used by iounmap and cannot
  573. * be hooked (but can be used by a hook on iounmap)
  574. *
  575. */
  576. extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
  577. extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
  578. unsigned long flags);
  579. extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
  580. #define ioremap_nocache(addr, size) ioremap((addr), (size))
  581. extern void iounmap(volatile void __iomem *addr);
  582. extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
  583. unsigned long flags);
  584. extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
  585. unsigned long flags, void *caller);
  586. extern void __iounmap(volatile void __iomem *addr);
  587. extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
  588. unsigned long size, unsigned long flags);
  589. extern void __iounmap_at(void *ea, unsigned long size);
  590. /*
  591. * When CONFIG_PPC_INDIRECT_IO is set, we use the generic iomap implementation
  592. * which needs some additional definitions here. They basically allow PIO
  593. * space overall to be 1GB. This will work as long as we never try to use
  594. * iomap to map MMIO below 1GB which should be fine on ppc64
  595. */
  596. #define HAVE_ARCH_PIO_SIZE 1
  597. #define PIO_OFFSET 0x00000000UL
  598. #define PIO_MASK (FULL_IO_SIZE - 1)
  599. #define PIO_RESERVED (FULL_IO_SIZE)
  600. #define mmio_read16be(addr) readw_be(addr)
  601. #define mmio_read32be(addr) readl_be(addr)
  602. #define mmio_write16be(val, addr) writew_be(val, addr)
  603. #define mmio_write32be(val, addr) writel_be(val, addr)
  604. #define mmio_insb(addr, dst, count) readsb(addr, dst, count)
  605. #define mmio_insw(addr, dst, count) readsw(addr, dst, count)
  606. #define mmio_insl(addr, dst, count) readsl(addr, dst, count)
  607. #define mmio_outsb(addr, src, count) writesb(addr, src, count)
  608. #define mmio_outsw(addr, src, count) writesw(addr, src, count)
  609. #define mmio_outsl(addr, src, count) writesl(addr, src, count)
  610. /**
  611. * virt_to_phys - map virtual addresses to physical
  612. * @address: address to remap
  613. *
  614. * The returned physical address is the physical (CPU) mapping for
  615. * the memory address given. It is only valid to use this function on
  616. * addresses directly mapped or allocated via kmalloc.
  617. *
  618. * This function does not give bus mappings for DMA transfers. In
  619. * almost all conceivable cases a device driver should not be using
  620. * this function
  621. */
  622. static inline unsigned long virt_to_phys(volatile void * address)
  623. {
  624. return __pa((unsigned long)address);
  625. }
  626. /**
  627. * phys_to_virt - map physical address to virtual
  628. * @address: address to remap
  629. *
  630. * The returned virtual address is a current CPU mapping for
  631. * the memory address given. It is only valid to use this function on
  632. * addresses that have a kernel mapping
  633. *
  634. * This function does not handle bus mappings for DMA transfers. In
  635. * almost all conceivable cases a device driver should not be using
  636. * this function
  637. */
  638. static inline void * phys_to_virt(unsigned long address)
  639. {
  640. return (void *)__va(address);
  641. }
  642. /*
  643. * Change "struct page" to physical address.
  644. */
  645. #define page_to_phys(page) ((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT)
  646. /*
  647. * 32 bits still uses virt_to_bus() for it's implementation of DMA
  648. * mappings se we have to keep it defined here. We also have some old
  649. * drivers (shame shame shame) that use bus_to_virt() and haven't been
  650. * fixed yet so I need to define it here.
  651. */
  652. #ifdef CONFIG_PPC32
  653. static inline unsigned long virt_to_bus(volatile void * address)
  654. {
  655. if (address == NULL)
  656. return 0;
  657. return __pa(address) + PCI_DRAM_OFFSET;
  658. }
  659. static inline void * bus_to_virt(unsigned long address)
  660. {
  661. if (address == 0)
  662. return NULL;
  663. return __va(address - PCI_DRAM_OFFSET);
  664. }
  665. #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
  666. #endif /* CONFIG_PPC32 */
  667. /* access ports */
  668. #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
  669. #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
  670. #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
  671. #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
  672. #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v))
  673. #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
  674. /* Clear and set bits in one shot. These macros can be used to clear and
  675. * set multiple bits in a register using a single read-modify-write. These
  676. * macros can also be used to set a multiple-bit bit pattern using a mask,
  677. * by specifying the mask in the 'clear' parameter and the new bit pattern
  678. * in the 'set' parameter.
  679. */
  680. #define clrsetbits(type, addr, clear, set) \
  681. out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
  682. #ifdef __powerpc64__
  683. #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
  684. #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
  685. #endif
  686. #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
  687. #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
  688. #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
  689. #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
  690. #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
  691. void __iomem *devm_ioremap_prot(struct device *dev, resource_size_t offset,
  692. size_t size, unsigned long flags);
  693. #endif /* __KERNEL__ */
  694. #endif /* _ASM_POWERPC_IO_H */