irq.c 13 KB

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  1. /*
  2. * Code to handle x86 style IRQs plus some generic interrupt stuff.
  3. *
  4. * Copyright (C) 1992 Linus Torvalds
  5. * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
  6. * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
  7. * Copyright (C) 1999-2000 Grant Grundler
  8. * Copyright (c) 2005 Matthew Wilcox
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2, or (at your option)
  13. * any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23. */
  24. #include <linux/bitops.h>
  25. #include <linux/errno.h>
  26. #include <linux/init.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/kernel_stat.h>
  29. #include <linux/seq_file.h>
  30. #include <linux/spinlock.h>
  31. #include <linux/types.h>
  32. #include <asm/io.h>
  33. #include <asm/smp.h>
  34. #undef PARISC_IRQ_CR16_COUNTS
  35. extern irqreturn_t timer_interrupt(int, void *);
  36. extern irqreturn_t ipi_interrupt(int, void *);
  37. #define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq))
  38. /* Bits in EIEM correlate with cpu_irq_action[].
  39. ** Numbered *Big Endian*! (ie bit 0 is MSB)
  40. */
  41. static volatile unsigned long cpu_eiem = 0;
  42. /*
  43. ** local ACK bitmap ... habitually set to 1, but reset to zero
  44. ** between ->ack() and ->end() of the interrupt to prevent
  45. ** re-interruption of a processing interrupt.
  46. */
  47. static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL;
  48. static void cpu_mask_irq(struct irq_data *d)
  49. {
  50. unsigned long eirr_bit = EIEM_MASK(d->irq);
  51. cpu_eiem &= ~eirr_bit;
  52. /* Do nothing on the other CPUs. If they get this interrupt,
  53. * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
  54. * handle it, and the set_eiem() at the bottom will ensure it
  55. * then gets disabled */
  56. }
  57. static void __cpu_unmask_irq(unsigned int irq)
  58. {
  59. unsigned long eirr_bit = EIEM_MASK(irq);
  60. cpu_eiem |= eirr_bit;
  61. /* This is just a simple NOP IPI. But what it does is cause
  62. * all the other CPUs to do a set_eiem(cpu_eiem) at the end
  63. * of the interrupt handler */
  64. smp_send_all_nop();
  65. }
  66. static void cpu_unmask_irq(struct irq_data *d)
  67. {
  68. __cpu_unmask_irq(d->irq);
  69. }
  70. void cpu_ack_irq(struct irq_data *d)
  71. {
  72. unsigned long mask = EIEM_MASK(d->irq);
  73. int cpu = smp_processor_id();
  74. /* Clear in EIEM so we can no longer process */
  75. per_cpu(local_ack_eiem, cpu) &= ~mask;
  76. /* disable the interrupt */
  77. set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
  78. /* and now ack it */
  79. mtctl(mask, 23);
  80. }
  81. void cpu_eoi_irq(struct irq_data *d)
  82. {
  83. unsigned long mask = EIEM_MASK(d->irq);
  84. int cpu = smp_processor_id();
  85. /* set it in the eiems---it's no longer in process */
  86. per_cpu(local_ack_eiem, cpu) |= mask;
  87. /* enable the interrupt */
  88. set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
  89. }
  90. #ifdef CONFIG_SMP
  91. int cpu_check_affinity(struct irq_data *d, const struct cpumask *dest)
  92. {
  93. int cpu_dest;
  94. /* timer and ipi have to always be received on all CPUs */
  95. if (irqd_is_per_cpu(d))
  96. return -EINVAL;
  97. /* whatever mask they set, we just allow one CPU */
  98. cpu_dest = first_cpu(*dest);
  99. return cpu_dest;
  100. }
  101. static int cpu_set_affinity_irq(struct irq_data *d, const struct cpumask *dest,
  102. bool force)
  103. {
  104. int cpu_dest;
  105. cpu_dest = cpu_check_affinity(d, dest);
  106. if (cpu_dest < 0)
  107. return -1;
  108. cpumask_copy(d->affinity, dest);
  109. return 0;
  110. }
  111. #endif
  112. static struct irq_chip cpu_interrupt_type = {
  113. .name = "CPU",
  114. .irq_mask = cpu_mask_irq,
  115. .irq_unmask = cpu_unmask_irq,
  116. .irq_ack = cpu_ack_irq,
  117. .irq_eoi = cpu_eoi_irq,
  118. #ifdef CONFIG_SMP
  119. .irq_set_affinity = cpu_set_affinity_irq,
  120. #endif
  121. /* XXX: Needs to be written. We managed without it so far, but
  122. * we really ought to write it.
  123. */
  124. .irq_retrigger = NULL,
  125. };
  126. DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
  127. #define irq_stats(x) (&per_cpu(irq_stat, x))
  128. /*
  129. * /proc/interrupts printing for arch specific interrupts
  130. */
  131. int arch_show_interrupts(struct seq_file *p, int prec)
  132. {
  133. int j;
  134. #ifdef CONFIG_DEBUG_STACKOVERFLOW
  135. seq_printf(p, "%*s: ", prec, "STK");
  136. for_each_online_cpu(j)
  137. seq_printf(p, "%10u ", irq_stats(j)->kernel_stack_usage);
  138. seq_printf(p, " Kernel stack usage\n");
  139. #endif
  140. #ifdef CONFIG_SMP
  141. seq_printf(p, "%*s: ", prec, "RES");
  142. for_each_online_cpu(j)
  143. seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
  144. seq_printf(p, " Rescheduling interrupts\n");
  145. seq_printf(p, "%*s: ", prec, "CAL");
  146. for_each_online_cpu(j)
  147. seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
  148. seq_printf(p, " Function call interrupts\n");
  149. #endif
  150. seq_printf(p, "%*s: ", prec, "TLB");
  151. for_each_online_cpu(j)
  152. seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
  153. seq_printf(p, " TLB shootdowns\n");
  154. return 0;
  155. }
  156. int show_interrupts(struct seq_file *p, void *v)
  157. {
  158. int i = *(loff_t *) v, j;
  159. unsigned long flags;
  160. if (i == 0) {
  161. seq_puts(p, " ");
  162. for_each_online_cpu(j)
  163. seq_printf(p, " CPU%d", j);
  164. #ifdef PARISC_IRQ_CR16_COUNTS
  165. seq_printf(p, " [min/avg/max] (CPU cycle counts)");
  166. #endif
  167. seq_putc(p, '\n');
  168. }
  169. if (i < NR_IRQS) {
  170. struct irq_desc *desc = irq_to_desc(i);
  171. struct irqaction *action;
  172. raw_spin_lock_irqsave(&desc->lock, flags);
  173. action = desc->action;
  174. if (!action)
  175. goto skip;
  176. seq_printf(p, "%3d: ", i);
  177. #ifdef CONFIG_SMP
  178. for_each_online_cpu(j)
  179. seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
  180. #else
  181. seq_printf(p, "%10u ", kstat_irqs(i));
  182. #endif
  183. seq_printf(p, " %14s", irq_desc_get_chip(desc)->name);
  184. #ifndef PARISC_IRQ_CR16_COUNTS
  185. seq_printf(p, " %s", action->name);
  186. while ((action = action->next))
  187. seq_printf(p, ", %s", action->name);
  188. #else
  189. for ( ;action; action = action->next) {
  190. unsigned int k, avg, min, max;
  191. min = max = action->cr16_hist[0];
  192. for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
  193. int hist = action->cr16_hist[k];
  194. if (hist) {
  195. avg += hist;
  196. } else
  197. break;
  198. if (hist > max) max = hist;
  199. if (hist < min) min = hist;
  200. }
  201. avg /= k;
  202. seq_printf(p, " %s[%d/%d/%d]", action->name,
  203. min,avg,max);
  204. }
  205. #endif
  206. seq_putc(p, '\n');
  207. skip:
  208. raw_spin_unlock_irqrestore(&desc->lock, flags);
  209. }
  210. if (i == NR_IRQS)
  211. arch_show_interrupts(p, 3);
  212. return 0;
  213. }
  214. /*
  215. ** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
  216. ** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
  217. **
  218. ** To use txn_XXX() interfaces, get a Virtual IRQ first.
  219. ** Then use that to get the Transaction address and data.
  220. */
  221. int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data)
  222. {
  223. if (irq_has_action(irq))
  224. return -EBUSY;
  225. if (irq_get_chip(irq) != &cpu_interrupt_type)
  226. return -EBUSY;
  227. /* for iosapic interrupts */
  228. if (type) {
  229. irq_set_chip_and_handler(irq, type, handle_percpu_irq);
  230. irq_set_chip_data(irq, data);
  231. __cpu_unmask_irq(irq);
  232. }
  233. return 0;
  234. }
  235. int txn_claim_irq(int irq)
  236. {
  237. return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq;
  238. }
  239. /*
  240. * The bits_wide parameter accommodates the limitations of the HW/SW which
  241. * use these bits:
  242. * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
  243. * V-class (EPIC): 6 bits
  244. * N/L/A-class (iosapic): 8 bits
  245. * PCI 2.2 MSI: 16 bits
  246. * Some PCI devices: 32 bits (Symbios SCSI/ATM/HyperFabric)
  247. *
  248. * On the service provider side:
  249. * o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register)
  250. * o PA 2.0 wide mode 6-bits (per processor)
  251. * o IA64 8-bits (0-256 total)
  252. *
  253. * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
  254. * by the processor...and the N/L-class I/O subsystem supports more bits than
  255. * PA2.0 has. The first case is the problem.
  256. */
  257. int txn_alloc_irq(unsigned int bits_wide)
  258. {
  259. int irq;
  260. /* never return irq 0 cause that's the interval timer */
  261. for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) {
  262. if (cpu_claim_irq(irq, NULL, NULL) < 0)
  263. continue;
  264. if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide))
  265. continue;
  266. return irq;
  267. }
  268. /* unlikely, but be prepared */
  269. return -1;
  270. }
  271. unsigned long txn_affinity_addr(unsigned int irq, int cpu)
  272. {
  273. #ifdef CONFIG_SMP
  274. struct irq_data *d = irq_get_irq_data(irq);
  275. cpumask_copy(d->affinity, cpumask_of(cpu));
  276. #endif
  277. return per_cpu(cpu_data, cpu).txn_addr;
  278. }
  279. unsigned long txn_alloc_addr(unsigned int virt_irq)
  280. {
  281. static int next_cpu = -1;
  282. next_cpu++; /* assign to "next" CPU we want this bugger on */
  283. /* validate entry */
  284. while ((next_cpu < nr_cpu_ids) &&
  285. (!per_cpu(cpu_data, next_cpu).txn_addr ||
  286. !cpu_online(next_cpu)))
  287. next_cpu++;
  288. if (next_cpu >= nr_cpu_ids)
  289. next_cpu = 0; /* nothing else, assign monarch */
  290. return txn_affinity_addr(virt_irq, next_cpu);
  291. }
  292. unsigned int txn_alloc_data(unsigned int virt_irq)
  293. {
  294. return virt_irq - CPU_IRQ_BASE;
  295. }
  296. static inline int eirr_to_irq(unsigned long eirr)
  297. {
  298. int bit = fls_long(eirr);
  299. return (BITS_PER_LONG - bit) + TIMER_IRQ;
  300. }
  301. int sysctl_panic_on_stackoverflow = 1;
  302. static inline void stack_overflow_check(struct pt_regs *regs)
  303. {
  304. #ifdef CONFIG_DEBUG_STACKOVERFLOW
  305. #define STACK_MARGIN (256*6)
  306. /* Our stack starts directly behind the thread_info struct. */
  307. unsigned long stack_start = (unsigned long) current_thread_info();
  308. unsigned long sp = regs->gr[30];
  309. unsigned long stack_usage;
  310. unsigned int *last_usage;
  311. /* if sr7 != 0, we interrupted a userspace process which we do not want
  312. * to check for stack overflow. We will only check the kernel stack. */
  313. if (regs->sr[7])
  314. return;
  315. /* calculate kernel stack usage */
  316. stack_usage = sp - stack_start;
  317. last_usage = &per_cpu(irq_stat.kernel_stack_usage, smp_processor_id());
  318. if (unlikely(stack_usage > *last_usage))
  319. *last_usage = stack_usage;
  320. if (likely(stack_usage < (THREAD_SIZE - STACK_MARGIN)))
  321. return;
  322. pr_emerg("stackcheck: %s will most likely overflow kernel stack "
  323. "(sp:%lx, stk bottom-top:%lx-%lx)\n",
  324. current->comm, sp, stack_start, stack_start + THREAD_SIZE);
  325. if (sysctl_panic_on_stackoverflow)
  326. panic("low stack detected by irq handler - check messages\n");
  327. #endif
  328. }
  329. #ifdef CONFIG_IRQSTACKS
  330. DEFINE_PER_CPU(union irq_stack_union, irq_stack_union);
  331. static void execute_on_irq_stack(void *func, unsigned long param1)
  332. {
  333. unsigned long *irq_stack_start;
  334. unsigned long irq_stack;
  335. int cpu = smp_processor_id();
  336. irq_stack_start = &per_cpu(irq_stack_union, cpu).stack[0];
  337. irq_stack = (unsigned long) irq_stack_start;
  338. irq_stack = ALIGN(irq_stack, 16); /* align for stack frame usage */
  339. BUG_ON(*irq_stack_start); /* report bug if we were called recursive. */
  340. *irq_stack_start = 1;
  341. /* This is where we switch to the IRQ stack. */
  342. call_on_stack(param1, func, irq_stack);
  343. *irq_stack_start = 0;
  344. }
  345. #endif /* CONFIG_IRQSTACKS */
  346. /* ONLY called from entry.S:intr_extint() */
  347. void do_cpu_irq_mask(struct pt_regs *regs)
  348. {
  349. struct pt_regs *old_regs;
  350. unsigned long eirr_val;
  351. int irq, cpu = smp_processor_id();
  352. #ifdef CONFIG_SMP
  353. struct irq_desc *desc;
  354. cpumask_t dest;
  355. #endif
  356. old_regs = set_irq_regs(regs);
  357. local_irq_disable();
  358. irq_enter();
  359. eirr_val = mfctl(23) & cpu_eiem & per_cpu(local_ack_eiem, cpu);
  360. if (!eirr_val)
  361. goto set_out;
  362. irq = eirr_to_irq(eirr_val);
  363. #ifdef CONFIG_SMP
  364. desc = irq_to_desc(irq);
  365. cpumask_copy(&dest, desc->irq_data.affinity);
  366. if (irqd_is_per_cpu(&desc->irq_data) &&
  367. !cpu_isset(smp_processor_id(), dest)) {
  368. int cpu = first_cpu(dest);
  369. printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n",
  370. irq, smp_processor_id(), cpu);
  371. gsc_writel(irq + CPU_IRQ_BASE,
  372. per_cpu(cpu_data, cpu).hpa);
  373. goto set_out;
  374. }
  375. #endif
  376. stack_overflow_check(regs);
  377. #ifdef CONFIG_IRQSTACKS
  378. execute_on_irq_stack(&generic_handle_irq, irq);
  379. #else
  380. generic_handle_irq(irq);
  381. #endif /* CONFIG_IRQSTACKS */
  382. out:
  383. irq_exit();
  384. set_irq_regs(old_regs);
  385. return;
  386. set_out:
  387. set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
  388. goto out;
  389. }
  390. static struct irqaction timer_action = {
  391. .handler = timer_interrupt,
  392. .name = "timer",
  393. .flags = IRQF_TIMER | IRQF_PERCPU | IRQF_IRQPOLL,
  394. };
  395. #ifdef CONFIG_SMP
  396. static struct irqaction ipi_action = {
  397. .handler = ipi_interrupt,
  398. .name = "IPI",
  399. .flags = IRQF_PERCPU,
  400. };
  401. #endif
  402. static void claim_cpu_irqs(void)
  403. {
  404. int i;
  405. for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
  406. irq_set_chip_and_handler(i, &cpu_interrupt_type,
  407. handle_percpu_irq);
  408. }
  409. irq_set_handler(TIMER_IRQ, handle_percpu_irq);
  410. setup_irq(TIMER_IRQ, &timer_action);
  411. #ifdef CONFIG_SMP
  412. irq_set_handler(IPI_IRQ, handle_percpu_irq);
  413. setup_irq(IPI_IRQ, &ipi_action);
  414. #endif
  415. }
  416. void __init init_IRQ(void)
  417. {
  418. local_irq_disable(); /* PARANOID - should already be disabled */
  419. mtctl(~0UL, 23); /* EIRR : clear all pending external intr */
  420. #ifdef CONFIG_SMP
  421. if (!cpu_eiem) {
  422. claim_cpu_irqs();
  423. cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ);
  424. }
  425. #else
  426. claim_cpu_irqs();
  427. cpu_eiem = EIEM_MASK(TIMER_IRQ);
  428. #endif
  429. set_eiem(cpu_eiem); /* EIEM : enable all external intr */
  430. }