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  1. /*
  2. * Linux/PA-RISC Project (http://www.parisc-linux.org/)
  3. *
  4. * kernel entry points (interruptions, system call wrappers)
  5. * Copyright (C) 1999,2000 Philipp Rumpf
  6. * Copyright (C) 1999 SuSE GmbH Nuernberg
  7. * Copyright (C) 2000 Hewlett-Packard (John Marvin)
  8. * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2, or (at your option)
  13. * any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23. */
  24. #include <asm/asm-offsets.h>
  25. /* we have the following possibilities to act on an interruption:
  26. * - handle in assembly and use shadowed registers only
  27. * - save registers to kernel stack and handle in assembly or C */
  28. #include <asm/psw.h>
  29. #include <asm/cache.h> /* for L1_CACHE_SHIFT */
  30. #include <asm/assembly.h> /* for LDREG/STREG defines */
  31. #include <asm/pgtable.h>
  32. #include <asm/signal.h>
  33. #include <asm/unistd.h>
  34. #include <asm/thread_info.h>
  35. #include <linux/linkage.h>
  36. #ifdef CONFIG_64BIT
  37. .level 2.0w
  38. #else
  39. .level 2.0
  40. #endif
  41. .import pa_dbit_lock,data
  42. /* space_to_prot macro creates a prot id from a space id */
  43. #if (SPACEID_SHIFT) == 0
  44. .macro space_to_prot spc prot
  45. depd,z \spc,62,31,\prot
  46. .endm
  47. #else
  48. .macro space_to_prot spc prot
  49. extrd,u \spc,(64 - (SPACEID_SHIFT)),32,\prot
  50. .endm
  51. #endif
  52. /* Switch to virtual mapping, trashing only %r1 */
  53. .macro virt_map
  54. /* pcxt_ssm_bug */
  55. rsm PSW_SM_I, %r0 /* barrier for "Relied upon Translation */
  56. mtsp %r0, %sr4
  57. mtsp %r0, %sr5
  58. mfsp %sr7, %r1
  59. or,= %r0,%r1,%r0 /* Only save sr7 in sr3 if sr7 != 0 */
  60. mtsp %r1, %sr3
  61. tovirt_r1 %r29
  62. load32 KERNEL_PSW, %r1
  63. rsm PSW_SM_QUIET,%r0 /* second "heavy weight" ctl op */
  64. mtsp %r0, %sr6
  65. mtsp %r0, %sr7
  66. mtctl %r0, %cr17 /* Clear IIASQ tail */
  67. mtctl %r0, %cr17 /* Clear IIASQ head */
  68. mtctl %r1, %ipsw
  69. load32 4f, %r1
  70. mtctl %r1, %cr18 /* Set IIAOQ tail */
  71. ldo 4(%r1), %r1
  72. mtctl %r1, %cr18 /* Set IIAOQ head */
  73. rfir
  74. nop
  75. 4:
  76. .endm
  77. /*
  78. * The "get_stack" macros are responsible for determining the
  79. * kernel stack value.
  80. *
  81. * If sr7 == 0
  82. * Already using a kernel stack, so call the
  83. * get_stack_use_r30 macro to push a pt_regs structure
  84. * on the stack, and store registers there.
  85. * else
  86. * Need to set up a kernel stack, so call the
  87. * get_stack_use_cr30 macro to set up a pointer
  88. * to the pt_regs structure contained within the
  89. * task pointer pointed to by cr30. Set the stack
  90. * pointer to point to the end of the task structure.
  91. *
  92. * Note that we use shadowed registers for temps until
  93. * we can save %r26 and %r29. %r26 is used to preserve
  94. * %r8 (a shadowed register) which temporarily contained
  95. * either the fault type ("code") or the eirr. We need
  96. * to use a non-shadowed register to carry the value over
  97. * the rfir in virt_map. We use %r26 since this value winds
  98. * up being passed as the argument to either do_cpu_irq_mask
  99. * or handle_interruption. %r29 is used to hold a pointer
  100. * the register save area, and once again, it needs to
  101. * be a non-shadowed register so that it survives the rfir.
  102. *
  103. * N.B. TASK_SZ_ALGN and PT_SZ_ALGN include space for a stack frame.
  104. */
  105. .macro get_stack_use_cr30
  106. /* we save the registers in the task struct */
  107. mfctl %cr30, %r1
  108. tophys %r1,%r9
  109. LDREG TI_TASK(%r9), %r1 /* thread_info -> task_struct */
  110. tophys %r1,%r9
  111. ldo TASK_REGS(%r9),%r9
  112. STREG %r30, PT_GR30(%r9)
  113. STREG %r29,PT_GR29(%r9)
  114. STREG %r26,PT_GR26(%r9)
  115. copy %r9,%r29
  116. mfctl %cr30, %r1
  117. ldo THREAD_SZ_ALGN(%r1), %r30
  118. .endm
  119. .macro get_stack_use_r30
  120. /* we put a struct pt_regs on the stack and save the registers there */
  121. tophys %r30,%r9
  122. STREG %r30,PT_GR30(%r9)
  123. ldo PT_SZ_ALGN(%r30),%r30
  124. STREG %r29,PT_GR29(%r9)
  125. STREG %r26,PT_GR26(%r9)
  126. copy %r9,%r29
  127. .endm
  128. .macro rest_stack
  129. LDREG PT_GR1(%r29), %r1
  130. LDREG PT_GR30(%r29),%r30
  131. LDREG PT_GR29(%r29),%r29
  132. .endm
  133. /* default interruption handler
  134. * (calls traps.c:handle_interruption) */
  135. .macro def code
  136. b intr_save
  137. ldi \code, %r8
  138. .align 32
  139. .endm
  140. /* Interrupt interruption handler
  141. * (calls irq.c:do_cpu_irq_mask) */
  142. .macro extint code
  143. b intr_extint
  144. mfsp %sr7,%r16
  145. .align 32
  146. .endm
  147. .import os_hpmc, code
  148. /* HPMC handler */
  149. .macro hpmc code
  150. nop /* must be a NOP, will be patched later */
  151. load32 PA(os_hpmc), %r3
  152. bv,n 0(%r3)
  153. nop
  154. .word 0 /* checksum (will be patched) */
  155. .word PA(os_hpmc) /* address of handler */
  156. .word 0 /* length of handler */
  157. .endm
  158. /*
  159. * Performance Note: Instructions will be moved up into
  160. * this part of the code later on, once we are sure
  161. * that the tlb miss handlers are close to final form.
  162. */
  163. /* Register definitions for tlb miss handler macros */
  164. va = r8 /* virtual address for which the trap occurred */
  165. spc = r24 /* space for which the trap occurred */
  166. #ifndef CONFIG_64BIT
  167. /*
  168. * itlb miss interruption handler (parisc 1.1 - 32 bit)
  169. */
  170. .macro itlb_11 code
  171. mfctl %pcsq, spc
  172. b itlb_miss_11
  173. mfctl %pcoq, va
  174. .align 32
  175. .endm
  176. #endif
  177. /*
  178. * itlb miss interruption handler (parisc 2.0)
  179. */
  180. .macro itlb_20 code
  181. mfctl %pcsq, spc
  182. #ifdef CONFIG_64BIT
  183. b itlb_miss_20w
  184. #else
  185. b itlb_miss_20
  186. #endif
  187. mfctl %pcoq, va
  188. .align 32
  189. .endm
  190. #ifndef CONFIG_64BIT
  191. /*
  192. * naitlb miss interruption handler (parisc 1.1 - 32 bit)
  193. */
  194. .macro naitlb_11 code
  195. mfctl %isr,spc
  196. b naitlb_miss_11
  197. mfctl %ior,va
  198. .align 32
  199. .endm
  200. #endif
  201. /*
  202. * naitlb miss interruption handler (parisc 2.0)
  203. */
  204. .macro naitlb_20 code
  205. mfctl %isr,spc
  206. #ifdef CONFIG_64BIT
  207. b naitlb_miss_20w
  208. #else
  209. b naitlb_miss_20
  210. #endif
  211. mfctl %ior,va
  212. .align 32
  213. .endm
  214. #ifndef CONFIG_64BIT
  215. /*
  216. * dtlb miss interruption handler (parisc 1.1 - 32 bit)
  217. */
  218. .macro dtlb_11 code
  219. mfctl %isr, spc
  220. b dtlb_miss_11
  221. mfctl %ior, va
  222. .align 32
  223. .endm
  224. #endif
  225. /*
  226. * dtlb miss interruption handler (parisc 2.0)
  227. */
  228. .macro dtlb_20 code
  229. mfctl %isr, spc
  230. #ifdef CONFIG_64BIT
  231. b dtlb_miss_20w
  232. #else
  233. b dtlb_miss_20
  234. #endif
  235. mfctl %ior, va
  236. .align 32
  237. .endm
  238. #ifndef CONFIG_64BIT
  239. /* nadtlb miss interruption handler (parisc 1.1 - 32 bit) */
  240. .macro nadtlb_11 code
  241. mfctl %isr,spc
  242. b nadtlb_miss_11
  243. mfctl %ior,va
  244. .align 32
  245. .endm
  246. #endif
  247. /* nadtlb miss interruption handler (parisc 2.0) */
  248. .macro nadtlb_20 code
  249. mfctl %isr,spc
  250. #ifdef CONFIG_64BIT
  251. b nadtlb_miss_20w
  252. #else
  253. b nadtlb_miss_20
  254. #endif
  255. mfctl %ior,va
  256. .align 32
  257. .endm
  258. #ifndef CONFIG_64BIT
  259. /*
  260. * dirty bit trap interruption handler (parisc 1.1 - 32 bit)
  261. */
  262. .macro dbit_11 code
  263. mfctl %isr,spc
  264. b dbit_trap_11
  265. mfctl %ior,va
  266. .align 32
  267. .endm
  268. #endif
  269. /*
  270. * dirty bit trap interruption handler (parisc 2.0)
  271. */
  272. .macro dbit_20 code
  273. mfctl %isr,spc
  274. #ifdef CONFIG_64BIT
  275. b dbit_trap_20w
  276. #else
  277. b dbit_trap_20
  278. #endif
  279. mfctl %ior,va
  280. .align 32
  281. .endm
  282. /* In LP64, the space contains part of the upper 32 bits of the
  283. * fault. We have to extract this and place it in the va,
  284. * zeroing the corresponding bits in the space register */
  285. .macro space_adjust spc,va,tmp
  286. #ifdef CONFIG_64BIT
  287. extrd,u \spc,63,SPACEID_SHIFT,\tmp
  288. depd %r0,63,SPACEID_SHIFT,\spc
  289. depd \tmp,31,SPACEID_SHIFT,\va
  290. #endif
  291. .endm
  292. .import swapper_pg_dir,code
  293. /* Get the pgd. For faults on space zero (kernel space), this
  294. * is simply swapper_pg_dir. For user space faults, the
  295. * pgd is stored in %cr25 */
  296. .macro get_pgd spc,reg
  297. ldil L%PA(swapper_pg_dir),\reg
  298. ldo R%PA(swapper_pg_dir)(\reg),\reg
  299. or,COND(=) %r0,\spc,%r0
  300. mfctl %cr25,\reg
  301. .endm
  302. /*
  303. space_check(spc,tmp,fault)
  304. spc - The space we saw the fault with.
  305. tmp - The place to store the current space.
  306. fault - Function to call on failure.
  307. Only allow faults on different spaces from the
  308. currently active one if we're the kernel
  309. */
  310. .macro space_check spc,tmp,fault
  311. mfsp %sr7,\tmp
  312. or,COND(<>) %r0,\spc,%r0 /* user may execute gateway page
  313. * as kernel, so defeat the space
  314. * check if it is */
  315. copy \spc,\tmp
  316. or,COND(=) %r0,\tmp,%r0 /* nullify if executing as kernel */
  317. cmpb,COND(<>),n \tmp,\spc,\fault
  318. .endm
  319. /* Look up a PTE in a 2-Level scheme (faulting at each
  320. * level if the entry isn't present
  321. *
  322. * NOTE: we use ldw even for LP64, since the short pointers
  323. * can address up to 1TB
  324. */
  325. .macro L2_ptep pmd,pte,index,va,fault
  326. #if PT_NLEVELS == 3
  327. extru \va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index
  328. #else
  329. # if defined(CONFIG_64BIT)
  330. extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
  331. #else
  332. # if PAGE_SIZE > 4096
  333. extru \va,31-ASM_PGDIR_SHIFT,32-ASM_PGDIR_SHIFT,\index
  334. # else
  335. extru \va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
  336. # endif
  337. # endif
  338. #endif
  339. dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */
  340. copy %r0,\pte
  341. ldw,s \index(\pmd),\pmd
  342. bb,>=,n \pmd,_PxD_PRESENT_BIT,\fault
  343. dep %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */
  344. copy \pmd,%r9
  345. SHLREG %r9,PxD_VALUE_SHIFT,\pmd
  346. extru \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
  347. dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */
  348. shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd
  349. LDREG %r0(\pmd),\pte /* pmd is now pte */
  350. bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault
  351. .endm
  352. /* Look up PTE in a 3-Level scheme.
  353. *
  354. * Here we implement a Hybrid L2/L3 scheme: we allocate the
  355. * first pmd adjacent to the pgd. This means that we can
  356. * subtract a constant offset to get to it. The pmd and pgd
  357. * sizes are arranged so that a single pmd covers 4GB (giving
  358. * a full LP64 process access to 8TB) so our lookups are
  359. * effectively L2 for the first 4GB of the kernel (i.e. for
  360. * all ILP32 processes and all the kernel for machines with
  361. * under 4GB of memory) */
  362. .macro L3_ptep pgd,pte,index,va,fault
  363. #if PT_NLEVELS == 3 /* we might have a 2-Level scheme, e.g. with 16kb page size */
  364. extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
  365. copy %r0,\pte
  366. extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
  367. ldw,s \index(\pgd),\pgd
  368. extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
  369. bb,>=,n \pgd,_PxD_PRESENT_BIT,\fault
  370. extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
  371. shld \pgd,PxD_VALUE_SHIFT,\index
  372. extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
  373. copy \index,\pgd
  374. extrd,u,*<> \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
  375. ldo ASM_PGD_PMD_OFFSET(\pgd),\pgd
  376. #endif
  377. L2_ptep \pgd,\pte,\index,\va,\fault
  378. .endm
  379. /* Set the _PAGE_ACCESSED bit of the PTE. Be clever and
  380. * don't needlessly dirty the cache line if it was already set */
  381. .macro update_ptep ptep,pte,tmp,tmp1
  382. ldi _PAGE_ACCESSED,\tmp1
  383. or \tmp1,\pte,\tmp
  384. and,COND(<>) \tmp1,\pte,%r0
  385. STREG \tmp,0(\ptep)
  386. .endm
  387. /* Set the dirty bit (and accessed bit). No need to be
  388. * clever, this is only used from the dirty fault */
  389. .macro update_dirty ptep,pte,tmp
  390. ldi _PAGE_ACCESSED|_PAGE_DIRTY,\tmp
  391. or \tmp,\pte,\pte
  392. STREG \pte,0(\ptep)
  393. .endm
  394. /* bitshift difference between a PFN (based on kernel's PAGE_SIZE)
  395. * to a CPU TLB 4k PFN (4k => 12 bits to shift) */
  396. #define PAGE_ADD_SHIFT (PAGE_SHIFT-12)
  397. /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
  398. .macro convert_for_tlb_insert20 pte
  399. extrd,u \pte,(63-ASM_PFN_PTE_SHIFT)+(63-58)+PAGE_ADD_SHIFT,\
  400. 64-PAGE_SHIFT-PAGE_ADD_SHIFT,\pte
  401. depdi _PAGE_SIZE_ENCODING_DEFAULT,63,\
  402. (63-58)+PAGE_ADD_SHIFT,\pte
  403. .endm
  404. /* Convert the pte and prot to tlb insertion values. How
  405. * this happens is quite subtle, read below */
  406. .macro make_insert_tlb spc,pte,prot
  407. space_to_prot \spc \prot /* create prot id from space */
  408. /* The following is the real subtlety. This is depositing
  409. * T <-> _PAGE_REFTRAP
  410. * D <-> _PAGE_DIRTY
  411. * B <-> _PAGE_DMB (memory break)
  412. *
  413. * Then incredible subtlety: The access rights are
  414. * _PAGE_GATEWAY, _PAGE_EXEC and _PAGE_WRITE
  415. * See 3-14 of the parisc 2.0 manual
  416. *
  417. * Finally, _PAGE_READ goes in the top bit of PL1 (so we
  418. * trigger an access rights trap in user space if the user
  419. * tries to read an unreadable page */
  420. depd \pte,8,7,\prot
  421. /* PAGE_USER indicates the page can be read with user privileges,
  422. * so deposit X1|11 to PL1|PL2 (remember the upper bit of PL1
  423. * contains _PAGE_READ) */
  424. extrd,u,*= \pte,_PAGE_USER_BIT+32,1,%r0
  425. depdi 7,11,3,\prot
  426. /* If we're a gateway page, drop PL2 back to zero for promotion
  427. * to kernel privilege (so we can execute the page as kernel).
  428. * Any privilege promotion page always denys read and write */
  429. extrd,u,*= \pte,_PAGE_GATEWAY_BIT+32,1,%r0
  430. depd %r0,11,2,\prot /* If Gateway, Set PL2 to 0 */
  431. /* Enforce uncacheable pages.
  432. * This should ONLY be use for MMIO on PA 2.0 machines.
  433. * Memory/DMA is cache coherent on all PA2.0 machines we support
  434. * (that means T-class is NOT supported) and the memory controllers
  435. * on most of those machines only handles cache transactions.
  436. */
  437. extrd,u,*= \pte,_PAGE_NO_CACHE_BIT+32,1,%r0
  438. depdi 1,12,1,\prot
  439. /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
  440. convert_for_tlb_insert20 \pte
  441. .endm
  442. /* Identical macro to make_insert_tlb above, except it
  443. * makes the tlb entry for the differently formatted pa11
  444. * insertion instructions */
  445. .macro make_insert_tlb_11 spc,pte,prot
  446. zdep \spc,30,15,\prot
  447. dep \pte,8,7,\prot
  448. extru,= \pte,_PAGE_NO_CACHE_BIT,1,%r0
  449. depi 1,12,1,\prot
  450. extru,= \pte,_PAGE_USER_BIT,1,%r0
  451. depi 7,11,3,\prot /* Set for user space (1 rsvd for read) */
  452. extru,= \pte,_PAGE_GATEWAY_BIT,1,%r0
  453. depi 0,11,2,\prot /* If Gateway, Set PL2 to 0 */
  454. /* Get rid of prot bits and convert to page addr for iitlba */
  455. depi 0,31,ASM_PFN_PTE_SHIFT,\pte
  456. SHRREG \pte,(ASM_PFN_PTE_SHIFT-(31-26)),\pte
  457. .endm
  458. /* This is for ILP32 PA2.0 only. The TLB insertion needs
  459. * to extend into I/O space if the address is 0xfXXXXXXX
  460. * so we extend the f's into the top word of the pte in
  461. * this case */
  462. .macro f_extend pte,tmp
  463. extrd,s \pte,42,4,\tmp
  464. addi,<> 1,\tmp,%r0
  465. extrd,s \pte,63,25,\pte
  466. .endm
  467. /* The alias region is an 8MB aligned 16MB to do clear and
  468. * copy user pages at addresses congruent with the user
  469. * virtual address.
  470. *
  471. * To use the alias page, you set %r26 up with the to TLB
  472. * entry (identifying the physical page) and %r23 up with
  473. * the from tlb entry (or nothing if only a to entry---for
  474. * clear_user_page_asm) */
  475. .macro do_alias spc,tmp,tmp1,va,pte,prot,fault,patype
  476. cmpib,COND(<>),n 0,\spc,\fault
  477. ldil L%(TMPALIAS_MAP_START),\tmp
  478. #if defined(CONFIG_64BIT) && (TMPALIAS_MAP_START >= 0x80000000)
  479. /* on LP64, ldi will sign extend into the upper 32 bits,
  480. * which is behaviour we don't want */
  481. depdi 0,31,32,\tmp
  482. #endif
  483. copy \va,\tmp1
  484. depi 0,31,23,\tmp1
  485. cmpb,COND(<>),n \tmp,\tmp1,\fault
  486. mfctl %cr19,\tmp /* iir */
  487. /* get the opcode (first six bits) into \tmp */
  488. extrw,u \tmp,5,6,\tmp
  489. /*
  490. * Only setting the T bit prevents data cache movein
  491. * Setting access rights to zero prevents instruction cache movein
  492. *
  493. * Note subtlety here: _PAGE_GATEWAY, _PAGE_EXEC and _PAGE_WRITE go
  494. * to type field and _PAGE_READ goes to top bit of PL1
  495. */
  496. ldi (_PAGE_REFTRAP|_PAGE_READ|_PAGE_WRITE),\prot
  497. /*
  498. * so if the opcode is one (i.e. this is a memory management
  499. * instruction) nullify the next load so \prot is only T.
  500. * Otherwise this is a normal data operation
  501. */
  502. cmpiclr,= 0x01,\tmp,%r0
  503. ldi (_PAGE_DIRTY|_PAGE_READ|_PAGE_WRITE),\prot
  504. .ifc \patype,20
  505. depd,z \prot,8,7,\prot
  506. .else
  507. .ifc \patype,11
  508. depw,z \prot,8,7,\prot
  509. .else
  510. .error "undefined PA type to do_alias"
  511. .endif
  512. .endif
  513. /*
  514. * OK, it is in the temp alias region, check whether "from" or "to".
  515. * Check "subtle" note in pacache.S re: r23/r26.
  516. */
  517. #ifdef CONFIG_64BIT
  518. extrd,u,*= \va,41,1,%r0
  519. #else
  520. extrw,u,= \va,9,1,%r0
  521. #endif
  522. or,COND(tr) %r23,%r0,\pte
  523. or %r26,%r0,\pte
  524. .endm
  525. /*
  526. * Align fault_vector_20 on 4K boundary so that both
  527. * fault_vector_11 and fault_vector_20 are on the
  528. * same page. This is only necessary as long as we
  529. * write protect the kernel text, which we may stop
  530. * doing once we use large page translations to cover
  531. * the static part of the kernel address space.
  532. */
  533. .text
  534. .align 4096
  535. ENTRY(fault_vector_20)
  536. /* First vector is invalid (0) */
  537. .ascii "cows can fly"
  538. .byte 0
  539. .align 32
  540. hpmc 1
  541. def 2
  542. def 3
  543. extint 4
  544. def 5
  545. itlb_20 6
  546. def 7
  547. def 8
  548. def 9
  549. def 10
  550. def 11
  551. def 12
  552. def 13
  553. def 14
  554. dtlb_20 15
  555. naitlb_20 16
  556. nadtlb_20 17
  557. def 18
  558. def 19
  559. dbit_20 20
  560. def 21
  561. def 22
  562. def 23
  563. def 24
  564. def 25
  565. def 26
  566. def 27
  567. def 28
  568. def 29
  569. def 30
  570. def 31
  571. END(fault_vector_20)
  572. #ifndef CONFIG_64BIT
  573. .align 2048
  574. ENTRY(fault_vector_11)
  575. /* First vector is invalid (0) */
  576. .ascii "cows can fly"
  577. .byte 0
  578. .align 32
  579. hpmc 1
  580. def 2
  581. def 3
  582. extint 4
  583. def 5
  584. itlb_11 6
  585. def 7
  586. def 8
  587. def 9
  588. def 10
  589. def 11
  590. def 12
  591. def 13
  592. def 14
  593. dtlb_11 15
  594. naitlb_11 16
  595. nadtlb_11 17
  596. def 18
  597. def 19
  598. dbit_11 20
  599. def 21
  600. def 22
  601. def 23
  602. def 24
  603. def 25
  604. def 26
  605. def 27
  606. def 28
  607. def 29
  608. def 30
  609. def 31
  610. END(fault_vector_11)
  611. #endif
  612. /* Fault vector is separately protected and *must* be on its own page */
  613. .align PAGE_SIZE
  614. ENTRY(end_fault_vector)
  615. .import handle_interruption,code
  616. .import do_cpu_irq_mask,code
  617. /*
  618. * Child Returns here
  619. *
  620. * copy_thread moved args into task save area.
  621. */
  622. ENTRY(ret_from_kernel_thread)
  623. /* Call schedule_tail first though */
  624. BL schedule_tail, %r2
  625. nop
  626. LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
  627. LDREG TASK_PT_GR25(%r1), %r26
  628. #ifdef CONFIG_64BIT
  629. LDREG TASK_PT_GR27(%r1), %r27
  630. #endif
  631. LDREG TASK_PT_GR26(%r1), %r1
  632. ble 0(%sr7, %r1)
  633. copy %r31, %r2
  634. b finish_child_return
  635. nop
  636. ENDPROC(ret_from_kernel_thread)
  637. /*
  638. * struct task_struct *_switch_to(struct task_struct *prev,
  639. * struct task_struct *next)
  640. *
  641. * switch kernel stacks and return prev */
  642. ENTRY(_switch_to)
  643. STREG %r2, -RP_OFFSET(%r30)
  644. callee_save_float
  645. callee_save
  646. load32 _switch_to_ret, %r2
  647. STREG %r2, TASK_PT_KPC(%r26)
  648. LDREG TASK_PT_KPC(%r25), %r2
  649. STREG %r30, TASK_PT_KSP(%r26)
  650. LDREG TASK_PT_KSP(%r25), %r30
  651. LDREG TASK_THREAD_INFO(%r25), %r25
  652. bv %r0(%r2)
  653. mtctl %r25,%cr30
  654. _switch_to_ret:
  655. mtctl %r0, %cr0 /* Needed for single stepping */
  656. callee_rest
  657. callee_rest_float
  658. LDREG -RP_OFFSET(%r30), %r2
  659. bv %r0(%r2)
  660. copy %r26, %r28
  661. ENDPROC(_switch_to)
  662. /*
  663. * Common rfi return path for interruptions, kernel execve, and
  664. * sys_rt_sigreturn (sometimes). The sys_rt_sigreturn syscall will
  665. * return via this path if the signal was received when the process
  666. * was running; if the process was blocked on a syscall then the
  667. * normal syscall_exit path is used. All syscalls for traced
  668. * proceses exit via intr_restore.
  669. *
  670. * XXX If any syscalls that change a processes space id ever exit
  671. * this way, then we will need to copy %sr3 in to PT_SR[3..7], and
  672. * adjust IASQ[0..1].
  673. *
  674. */
  675. .align PAGE_SIZE
  676. ENTRY(syscall_exit_rfi)
  677. mfctl %cr30,%r16
  678. LDREG TI_TASK(%r16), %r16 /* thread_info -> task_struct */
  679. ldo TASK_REGS(%r16),%r16
  680. /* Force iaoq to userspace, as the user has had access to our current
  681. * context via sigcontext. Also Filter the PSW for the same reason.
  682. */
  683. LDREG PT_IAOQ0(%r16),%r19
  684. depi 3,31,2,%r19
  685. STREG %r19,PT_IAOQ0(%r16)
  686. LDREG PT_IAOQ1(%r16),%r19
  687. depi 3,31,2,%r19
  688. STREG %r19,PT_IAOQ1(%r16)
  689. LDREG PT_PSW(%r16),%r19
  690. load32 USER_PSW_MASK,%r1
  691. #ifdef CONFIG_64BIT
  692. load32 USER_PSW_HI_MASK,%r20
  693. depd %r20,31,32,%r1
  694. #endif
  695. and %r19,%r1,%r19 /* Mask out bits that user shouldn't play with */
  696. load32 USER_PSW,%r1
  697. or %r19,%r1,%r19 /* Make sure default USER_PSW bits are set */
  698. STREG %r19,PT_PSW(%r16)
  699. /*
  700. * If we aren't being traced, we never saved space registers
  701. * (we don't store them in the sigcontext), so set them
  702. * to "proper" values now (otherwise we'll wind up restoring
  703. * whatever was last stored in the task structure, which might
  704. * be inconsistent if an interrupt occurred while on the gateway
  705. * page). Note that we may be "trashing" values the user put in
  706. * them, but we don't support the user changing them.
  707. */
  708. STREG %r0,PT_SR2(%r16)
  709. mfsp %sr3,%r19
  710. STREG %r19,PT_SR0(%r16)
  711. STREG %r19,PT_SR1(%r16)
  712. STREG %r19,PT_SR3(%r16)
  713. STREG %r19,PT_SR4(%r16)
  714. STREG %r19,PT_SR5(%r16)
  715. STREG %r19,PT_SR6(%r16)
  716. STREG %r19,PT_SR7(%r16)
  717. intr_return:
  718. /* check for reschedule */
  719. mfctl %cr30,%r1
  720. LDREG TI_FLAGS(%r1),%r19 /* sched.h: TIF_NEED_RESCHED */
  721. bb,<,n %r19,31-TIF_NEED_RESCHED,intr_do_resched /* forward */
  722. .import do_notify_resume,code
  723. intr_check_sig:
  724. /* As above */
  725. mfctl %cr30,%r1
  726. LDREG TI_FLAGS(%r1),%r19
  727. ldi (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME), %r20
  728. and,COND(<>) %r19, %r20, %r0
  729. b,n intr_restore /* skip past if we've nothing to do */
  730. /* This check is critical to having LWS
  731. * working. The IASQ is zero on the gateway
  732. * page and we cannot deliver any signals until
  733. * we get off the gateway page.
  734. *
  735. * Only do signals if we are returning to user space
  736. */
  737. LDREG PT_IASQ0(%r16), %r20
  738. cmpib,COND(=),n 0,%r20,intr_restore /* backward */
  739. LDREG PT_IASQ1(%r16), %r20
  740. cmpib,COND(=),n 0,%r20,intr_restore /* backward */
  741. /* NOTE: We need to enable interrupts if we have to deliver
  742. * signals. We used to do this earlier but it caused kernel
  743. * stack overflows. */
  744. ssm PSW_SM_I, %r0
  745. copy %r0, %r25 /* long in_syscall = 0 */
  746. #ifdef CONFIG_64BIT
  747. ldo -16(%r30),%r29 /* Reference param save area */
  748. #endif
  749. BL do_notify_resume,%r2
  750. copy %r16, %r26 /* struct pt_regs *regs */
  751. b,n intr_check_sig
  752. intr_restore:
  753. copy %r16,%r29
  754. ldo PT_FR31(%r29),%r1
  755. rest_fp %r1
  756. rest_general %r29
  757. /* inverse of virt_map */
  758. pcxt_ssm_bug
  759. rsm PSW_SM_QUIET,%r0 /* prepare for rfi */
  760. tophys_r1 %r29
  761. /* Restore space id's and special cr's from PT_REGS
  762. * structure pointed to by r29
  763. */
  764. rest_specials %r29
  765. /* IMPORTANT: rest_stack restores r29 last (we are using it)!
  766. * It also restores r1 and r30.
  767. */
  768. rest_stack
  769. rfi
  770. nop
  771. #ifndef CONFIG_PREEMPT
  772. # define intr_do_preempt intr_restore
  773. #endif /* !CONFIG_PREEMPT */
  774. .import schedule,code
  775. intr_do_resched:
  776. /* Only call schedule on return to userspace. If we're returning
  777. * to kernel space, we may schedule if CONFIG_PREEMPT, otherwise
  778. * we jump back to intr_restore.
  779. */
  780. LDREG PT_IASQ0(%r16), %r20
  781. cmpib,COND(=) 0, %r20, intr_do_preempt
  782. nop
  783. LDREG PT_IASQ1(%r16), %r20
  784. cmpib,COND(=) 0, %r20, intr_do_preempt
  785. nop
  786. /* NOTE: We need to enable interrupts if we schedule. We used
  787. * to do this earlier but it caused kernel stack overflows. */
  788. ssm PSW_SM_I, %r0
  789. #ifdef CONFIG_64BIT
  790. ldo -16(%r30),%r29 /* Reference param save area */
  791. #endif
  792. ldil L%intr_check_sig, %r2
  793. #ifndef CONFIG_64BIT
  794. b schedule
  795. #else
  796. load32 schedule, %r20
  797. bv %r0(%r20)
  798. #endif
  799. ldo R%intr_check_sig(%r2), %r2
  800. /* preempt the current task on returning to kernel
  801. * mode from an interrupt, iff need_resched is set,
  802. * and preempt_count is 0. otherwise, we continue on
  803. * our merry way back to the current running task.
  804. */
  805. #ifdef CONFIG_PREEMPT
  806. .import preempt_schedule_irq,code
  807. intr_do_preempt:
  808. rsm PSW_SM_I, %r0 /* disable interrupts */
  809. /* current_thread_info()->preempt_count */
  810. mfctl %cr30, %r1
  811. LDREG TI_PRE_COUNT(%r1), %r19
  812. cmpib,COND(<>) 0, %r19, intr_restore /* if preempt_count > 0 */
  813. nop /* prev insn branched backwards */
  814. /* check if we interrupted a critical path */
  815. LDREG PT_PSW(%r16), %r20
  816. bb,<,n %r20, 31 - PSW_SM_I, intr_restore
  817. nop
  818. BL preempt_schedule_irq, %r2
  819. nop
  820. b,n intr_restore /* ssm PSW_SM_I done by intr_restore */
  821. #endif /* CONFIG_PREEMPT */
  822. /*
  823. * External interrupts.
  824. */
  825. intr_extint:
  826. cmpib,COND(=),n 0,%r16,1f
  827. get_stack_use_cr30
  828. b,n 2f
  829. 1:
  830. get_stack_use_r30
  831. 2:
  832. save_specials %r29
  833. virt_map
  834. save_general %r29
  835. ldo PT_FR0(%r29), %r24
  836. save_fp %r24
  837. loadgp
  838. copy %r29, %r26 /* arg0 is pt_regs */
  839. copy %r29, %r16 /* save pt_regs */
  840. ldil L%intr_return, %r2
  841. #ifdef CONFIG_64BIT
  842. ldo -16(%r30),%r29 /* Reference param save area */
  843. #endif
  844. b do_cpu_irq_mask
  845. ldo R%intr_return(%r2), %r2 /* return to intr_return, not here */
  846. ENDPROC(syscall_exit_rfi)
  847. /* Generic interruptions (illegal insn, unaligned, page fault, etc) */
  848. ENTRY(intr_save) /* for os_hpmc */
  849. mfsp %sr7,%r16
  850. cmpib,COND(=),n 0,%r16,1f
  851. get_stack_use_cr30
  852. b 2f
  853. copy %r8,%r26
  854. 1:
  855. get_stack_use_r30
  856. copy %r8,%r26
  857. 2:
  858. save_specials %r29
  859. /* If this trap is a itlb miss, skip saving/adjusting isr/ior */
  860. /*
  861. * FIXME: 1) Use a #define for the hardwired "6" below (and in
  862. * traps.c.
  863. * 2) Once we start executing code above 4 Gb, we need
  864. * to adjust iasq/iaoq here in the same way we
  865. * adjust isr/ior below.
  866. */
  867. cmpib,COND(=),n 6,%r26,skip_save_ior
  868. mfctl %cr20, %r16 /* isr */
  869. nop /* serialize mfctl on PA 2.0 to avoid 4 cycle penalty */
  870. mfctl %cr21, %r17 /* ior */
  871. #ifdef CONFIG_64BIT
  872. /*
  873. * If the interrupted code was running with W bit off (32 bit),
  874. * clear the b bits (bits 0 & 1) in the ior.
  875. * save_specials left ipsw value in r8 for us to test.
  876. */
  877. extrd,u,*<> %r8,PSW_W_BIT,1,%r0
  878. depdi 0,1,2,%r17
  879. /*
  880. * FIXME: This code has hardwired assumptions about the split
  881. * between space bits and offset bits. This will change
  882. * when we allow alternate page sizes.
  883. */
  884. /* adjust isr/ior. */
  885. extrd,u %r16,63,SPACEID_SHIFT,%r1 /* get high bits from isr for ior */
  886. depd %r1,31,SPACEID_SHIFT,%r17 /* deposit them into ior */
  887. depdi 0,63,SPACEID_SHIFT,%r16 /* clear them from isr */
  888. #endif
  889. STREG %r16, PT_ISR(%r29)
  890. STREG %r17, PT_IOR(%r29)
  891. skip_save_ior:
  892. virt_map
  893. save_general %r29
  894. ldo PT_FR0(%r29), %r25
  895. save_fp %r25
  896. loadgp
  897. copy %r29, %r25 /* arg1 is pt_regs */
  898. #ifdef CONFIG_64BIT
  899. ldo -16(%r30),%r29 /* Reference param save area */
  900. #endif
  901. ldil L%intr_check_sig, %r2
  902. copy %r25, %r16 /* save pt_regs */
  903. b handle_interruption
  904. ldo R%intr_check_sig(%r2), %r2
  905. ENDPROC(intr_save)
  906. /*
  907. * Note for all tlb miss handlers:
  908. *
  909. * cr24 contains a pointer to the kernel address space
  910. * page directory.
  911. *
  912. * cr25 contains a pointer to the current user address
  913. * space page directory.
  914. *
  915. * sr3 will contain the space id of the user address space
  916. * of the current running thread while that thread is
  917. * running in the kernel.
  918. */
  919. /*
  920. * register number allocations. Note that these are all
  921. * in the shadowed registers
  922. */
  923. t0 = r1 /* temporary register 0 */
  924. va = r8 /* virtual address for which the trap occurred */
  925. t1 = r9 /* temporary register 1 */
  926. pte = r16 /* pte/phys page # */
  927. prot = r17 /* prot bits */
  928. spc = r24 /* space for which the trap occurred */
  929. ptp = r25 /* page directory/page table pointer */
  930. #ifdef CONFIG_64BIT
  931. dtlb_miss_20w:
  932. space_adjust spc,va,t0
  933. get_pgd spc,ptp
  934. space_check spc,t0,dtlb_fault
  935. L3_ptep ptp,pte,t0,va,dtlb_check_alias_20w
  936. update_ptep ptp,pte,t0,t1
  937. make_insert_tlb spc,pte,prot
  938. idtlbt pte,prot
  939. rfir
  940. nop
  941. dtlb_check_alias_20w:
  942. do_alias spc,t0,t1,va,pte,prot,dtlb_fault,20
  943. idtlbt pte,prot
  944. rfir
  945. nop
  946. nadtlb_miss_20w:
  947. space_adjust spc,va,t0
  948. get_pgd spc,ptp
  949. space_check spc,t0,nadtlb_fault
  950. L3_ptep ptp,pte,t0,va,nadtlb_check_alias_20w
  951. update_ptep ptp,pte,t0,t1
  952. make_insert_tlb spc,pte,prot
  953. idtlbt pte,prot
  954. rfir
  955. nop
  956. nadtlb_check_alias_20w:
  957. do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,20
  958. idtlbt pte,prot
  959. rfir
  960. nop
  961. #else
  962. dtlb_miss_11:
  963. get_pgd spc,ptp
  964. space_check spc,t0,dtlb_fault
  965. L2_ptep ptp,pte,t0,va,dtlb_check_alias_11
  966. update_ptep ptp,pte,t0,t1
  967. make_insert_tlb_11 spc,pte,prot
  968. mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
  969. mtsp spc,%sr1
  970. idtlba pte,(%sr1,va)
  971. idtlbp prot,(%sr1,va)
  972. mtsp t0, %sr1 /* Restore sr1 */
  973. rfir
  974. nop
  975. dtlb_check_alias_11:
  976. do_alias spc,t0,t1,va,pte,prot,dtlb_fault,11
  977. idtlba pte,(va)
  978. idtlbp prot,(va)
  979. rfir
  980. nop
  981. nadtlb_miss_11:
  982. get_pgd spc,ptp
  983. space_check spc,t0,nadtlb_fault
  984. L2_ptep ptp,pte,t0,va,nadtlb_check_alias_11
  985. update_ptep ptp,pte,t0,t1
  986. make_insert_tlb_11 spc,pte,prot
  987. mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
  988. mtsp spc,%sr1
  989. idtlba pte,(%sr1,va)
  990. idtlbp prot,(%sr1,va)
  991. mtsp t0, %sr1 /* Restore sr1 */
  992. rfir
  993. nop
  994. nadtlb_check_alias_11:
  995. do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,11
  996. idtlba pte,(va)
  997. idtlbp prot,(va)
  998. rfir
  999. nop
  1000. dtlb_miss_20:
  1001. space_adjust spc,va,t0
  1002. get_pgd spc,ptp
  1003. space_check spc,t0,dtlb_fault
  1004. L2_ptep ptp,pte,t0,va,dtlb_check_alias_20
  1005. update_ptep ptp,pte,t0,t1
  1006. make_insert_tlb spc,pte,prot
  1007. f_extend pte,t0
  1008. idtlbt pte,prot
  1009. rfir
  1010. nop
  1011. dtlb_check_alias_20:
  1012. do_alias spc,t0,t1,va,pte,prot,dtlb_fault,20
  1013. idtlbt pte,prot
  1014. rfir
  1015. nop
  1016. nadtlb_miss_20:
  1017. get_pgd spc,ptp
  1018. space_check spc,t0,nadtlb_fault
  1019. L2_ptep ptp,pte,t0,va,nadtlb_check_alias_20
  1020. update_ptep ptp,pte,t0,t1
  1021. make_insert_tlb spc,pte,prot
  1022. f_extend pte,t0
  1023. idtlbt pte,prot
  1024. rfir
  1025. nop
  1026. nadtlb_check_alias_20:
  1027. do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,20
  1028. idtlbt pte,prot
  1029. rfir
  1030. nop
  1031. #endif
  1032. nadtlb_emulate:
  1033. /*
  1034. * Non access misses can be caused by fdc,fic,pdc,lpa,probe and
  1035. * probei instructions. We don't want to fault for these
  1036. * instructions (not only does it not make sense, it can cause
  1037. * deadlocks, since some flushes are done with the mmap
  1038. * semaphore held). If the translation doesn't exist, we can't
  1039. * insert a translation, so have to emulate the side effects
  1040. * of the instruction. Since we don't insert a translation
  1041. * we can get a lot of faults during a flush loop, so it makes
  1042. * sense to try to do it here with minimum overhead. We only
  1043. * emulate fdc,fic,pdc,probew,prober instructions whose base
  1044. * and index registers are not shadowed. We defer everything
  1045. * else to the "slow" path.
  1046. */
  1047. mfctl %cr19,%r9 /* Get iir */
  1048. /* PA 2.0 Arch Ref. Book pg 382 has a good description of the insn bits.
  1049. Checks for fdc,fdce,pdc,"fic,4f",prober,probeir,probew, probeiw */
  1050. /* Checks for fdc,fdce,pdc,"fic,4f" only */
  1051. ldi 0x280,%r16
  1052. and %r9,%r16,%r17
  1053. cmpb,<>,n %r16,%r17,nadtlb_probe_check
  1054. bb,>=,n %r9,26,nadtlb_nullify /* m bit not set, just nullify */
  1055. BL get_register,%r25
  1056. extrw,u %r9,15,5,%r8 /* Get index register # */
  1057. cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
  1058. copy %r1,%r24
  1059. BL get_register,%r25
  1060. extrw,u %r9,10,5,%r8 /* Get base register # */
  1061. cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
  1062. BL set_register,%r25
  1063. add,l %r1,%r24,%r1 /* doesn't affect c/b bits */
  1064. nadtlb_nullify:
  1065. mfctl %ipsw,%r8
  1066. ldil L%PSW_N,%r9
  1067. or %r8,%r9,%r8 /* Set PSW_N */
  1068. mtctl %r8,%ipsw
  1069. rfir
  1070. nop
  1071. /*
  1072. When there is no translation for the probe address then we
  1073. must nullify the insn and return zero in the target regsiter.
  1074. This will indicate to the calling code that it does not have
  1075. write/read privileges to this address.
  1076. This should technically work for prober and probew in PA 1.1,
  1077. and also probe,r and probe,w in PA 2.0
  1078. WARNING: USE ONLY NON-SHADOW REGISTERS WITH PROBE INSN!
  1079. THE SLOW-PATH EMULATION HAS NOT BEEN WRITTEN YET.
  1080. */
  1081. nadtlb_probe_check:
  1082. ldi 0x80,%r16
  1083. and %r9,%r16,%r17
  1084. cmpb,<>,n %r16,%r17,nadtlb_fault /* Must be probe,[rw]*/
  1085. BL get_register,%r25 /* Find the target register */
  1086. extrw,u %r9,31,5,%r8 /* Get target register */
  1087. cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
  1088. BL set_register,%r25
  1089. copy %r0,%r1 /* Write zero to target register */
  1090. b nadtlb_nullify /* Nullify return insn */
  1091. nop
  1092. #ifdef CONFIG_64BIT
  1093. itlb_miss_20w:
  1094. /*
  1095. * I miss is a little different, since we allow users to fault
  1096. * on the gateway page which is in the kernel address space.
  1097. */
  1098. space_adjust spc,va,t0
  1099. get_pgd spc,ptp
  1100. space_check spc,t0,itlb_fault
  1101. L3_ptep ptp,pte,t0,va,itlb_fault
  1102. update_ptep ptp,pte,t0,t1
  1103. make_insert_tlb spc,pte,prot
  1104. iitlbt pte,prot
  1105. rfir
  1106. nop
  1107. naitlb_miss_20w:
  1108. /*
  1109. * I miss is a little different, since we allow users to fault
  1110. * on the gateway page which is in the kernel address space.
  1111. */
  1112. space_adjust spc,va,t0
  1113. get_pgd spc,ptp
  1114. space_check spc,t0,naitlb_fault
  1115. L3_ptep ptp,pte,t0,va,naitlb_check_alias_20w
  1116. update_ptep ptp,pte,t0,t1
  1117. make_insert_tlb spc,pte,prot
  1118. iitlbt pte,prot
  1119. rfir
  1120. nop
  1121. naitlb_check_alias_20w:
  1122. do_alias spc,t0,t1,va,pte,prot,naitlb_fault,20
  1123. iitlbt pte,prot
  1124. rfir
  1125. nop
  1126. #else
  1127. itlb_miss_11:
  1128. get_pgd spc,ptp
  1129. space_check spc,t0,itlb_fault
  1130. L2_ptep ptp,pte,t0,va,itlb_fault
  1131. update_ptep ptp,pte,t0,t1
  1132. make_insert_tlb_11 spc,pte,prot
  1133. mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
  1134. mtsp spc,%sr1
  1135. iitlba pte,(%sr1,va)
  1136. iitlbp prot,(%sr1,va)
  1137. mtsp t0, %sr1 /* Restore sr1 */
  1138. rfir
  1139. nop
  1140. naitlb_miss_11:
  1141. get_pgd spc,ptp
  1142. space_check spc,t0,naitlb_fault
  1143. L2_ptep ptp,pte,t0,va,naitlb_check_alias_11
  1144. update_ptep ptp,pte,t0,t1
  1145. make_insert_tlb_11 spc,pte,prot
  1146. mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
  1147. mtsp spc,%sr1
  1148. iitlba pte,(%sr1,va)
  1149. iitlbp prot,(%sr1,va)
  1150. mtsp t0, %sr1 /* Restore sr1 */
  1151. rfir
  1152. nop
  1153. naitlb_check_alias_11:
  1154. do_alias spc,t0,t1,va,pte,prot,itlb_fault,11
  1155. iitlba pte,(%sr0, va)
  1156. iitlbp prot,(%sr0, va)
  1157. rfir
  1158. nop
  1159. itlb_miss_20:
  1160. get_pgd spc,ptp
  1161. space_check spc,t0,itlb_fault
  1162. L2_ptep ptp,pte,t0,va,itlb_fault
  1163. update_ptep ptp,pte,t0,t1
  1164. make_insert_tlb spc,pte,prot
  1165. f_extend pte,t0
  1166. iitlbt pte,prot
  1167. rfir
  1168. nop
  1169. naitlb_miss_20:
  1170. get_pgd spc,ptp
  1171. space_check spc,t0,naitlb_fault
  1172. L2_ptep ptp,pte,t0,va,naitlb_check_alias_20
  1173. update_ptep ptp,pte,t0,t1
  1174. make_insert_tlb spc,pte,prot
  1175. f_extend pte,t0
  1176. iitlbt pte,prot
  1177. rfir
  1178. nop
  1179. naitlb_check_alias_20:
  1180. do_alias spc,t0,t1,va,pte,prot,naitlb_fault,20
  1181. iitlbt pte,prot
  1182. rfir
  1183. nop
  1184. #endif
  1185. #ifdef CONFIG_64BIT
  1186. dbit_trap_20w:
  1187. space_adjust spc,va,t0
  1188. get_pgd spc,ptp
  1189. space_check spc,t0,dbit_fault
  1190. L3_ptep ptp,pte,t0,va,dbit_fault
  1191. #ifdef CONFIG_SMP
  1192. cmpib,COND(=),n 0,spc,dbit_nolock_20w
  1193. load32 PA(pa_dbit_lock),t0
  1194. dbit_spin_20w:
  1195. LDCW 0(t0),t1
  1196. cmpib,COND(=) 0,t1,dbit_spin_20w
  1197. nop
  1198. dbit_nolock_20w:
  1199. #endif
  1200. update_dirty ptp,pte,t1
  1201. make_insert_tlb spc,pte,prot
  1202. idtlbt pte,prot
  1203. #ifdef CONFIG_SMP
  1204. cmpib,COND(=),n 0,spc,dbit_nounlock_20w
  1205. ldi 1,t1
  1206. stw t1,0(t0)
  1207. dbit_nounlock_20w:
  1208. #endif
  1209. rfir
  1210. nop
  1211. #else
  1212. dbit_trap_11:
  1213. get_pgd spc,ptp
  1214. space_check spc,t0,dbit_fault
  1215. L2_ptep ptp,pte,t0,va,dbit_fault
  1216. #ifdef CONFIG_SMP
  1217. cmpib,COND(=),n 0,spc,dbit_nolock_11
  1218. load32 PA(pa_dbit_lock),t0
  1219. dbit_spin_11:
  1220. LDCW 0(t0),t1
  1221. cmpib,= 0,t1,dbit_spin_11
  1222. nop
  1223. dbit_nolock_11:
  1224. #endif
  1225. update_dirty ptp,pte,t1
  1226. make_insert_tlb_11 spc,pte,prot
  1227. mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
  1228. mtsp spc,%sr1
  1229. idtlba pte,(%sr1,va)
  1230. idtlbp prot,(%sr1,va)
  1231. mtsp t1, %sr1 /* Restore sr1 */
  1232. #ifdef CONFIG_SMP
  1233. cmpib,COND(=),n 0,spc,dbit_nounlock_11
  1234. ldi 1,t1
  1235. stw t1,0(t0)
  1236. dbit_nounlock_11:
  1237. #endif
  1238. rfir
  1239. nop
  1240. dbit_trap_20:
  1241. get_pgd spc,ptp
  1242. space_check spc,t0,dbit_fault
  1243. L2_ptep ptp,pte,t0,va,dbit_fault
  1244. #ifdef CONFIG_SMP
  1245. cmpib,COND(=),n 0,spc,dbit_nolock_20
  1246. load32 PA(pa_dbit_lock),t0
  1247. dbit_spin_20:
  1248. LDCW 0(t0),t1
  1249. cmpib,= 0,t1,dbit_spin_20
  1250. nop
  1251. dbit_nolock_20:
  1252. #endif
  1253. update_dirty ptp,pte,t1
  1254. make_insert_tlb spc,pte,prot
  1255. f_extend pte,t1
  1256. idtlbt pte,prot
  1257. #ifdef CONFIG_SMP
  1258. cmpib,COND(=),n 0,spc,dbit_nounlock_20
  1259. ldi 1,t1
  1260. stw t1,0(t0)
  1261. dbit_nounlock_20:
  1262. #endif
  1263. rfir
  1264. nop
  1265. #endif
  1266. .import handle_interruption,code
  1267. kernel_bad_space:
  1268. b intr_save
  1269. ldi 31,%r8 /* Use an unused code */
  1270. dbit_fault:
  1271. b intr_save
  1272. ldi 20,%r8
  1273. itlb_fault:
  1274. b intr_save
  1275. ldi 6,%r8
  1276. nadtlb_fault:
  1277. b intr_save
  1278. ldi 17,%r8
  1279. naitlb_fault:
  1280. b intr_save
  1281. ldi 16,%r8
  1282. dtlb_fault:
  1283. b intr_save
  1284. ldi 15,%r8
  1285. /* Register saving semantics for system calls:
  1286. %r1 clobbered by system call macro in userspace
  1287. %r2 saved in PT_REGS by gateway page
  1288. %r3 - %r18 preserved by C code (saved by signal code)
  1289. %r19 - %r20 saved in PT_REGS by gateway page
  1290. %r21 - %r22 non-standard syscall args
  1291. stored in kernel stack by gateway page
  1292. %r23 - %r26 arg3-arg0, saved in PT_REGS by gateway page
  1293. %r27 - %r30 saved in PT_REGS by gateway page
  1294. %r31 syscall return pointer
  1295. */
  1296. /* Floating point registers (FIXME: what do we do with these?)
  1297. %fr0 - %fr3 status/exception, not preserved
  1298. %fr4 - %fr7 arguments
  1299. %fr8 - %fr11 not preserved by C code
  1300. %fr12 - %fr21 preserved by C code
  1301. %fr22 - %fr31 not preserved by C code
  1302. */
  1303. .macro reg_save regs
  1304. STREG %r3, PT_GR3(\regs)
  1305. STREG %r4, PT_GR4(\regs)
  1306. STREG %r5, PT_GR5(\regs)
  1307. STREG %r6, PT_GR6(\regs)
  1308. STREG %r7, PT_GR7(\regs)
  1309. STREG %r8, PT_GR8(\regs)
  1310. STREG %r9, PT_GR9(\regs)
  1311. STREG %r10,PT_GR10(\regs)
  1312. STREG %r11,PT_GR11(\regs)
  1313. STREG %r12,PT_GR12(\regs)
  1314. STREG %r13,PT_GR13(\regs)
  1315. STREG %r14,PT_GR14(\regs)
  1316. STREG %r15,PT_GR15(\regs)
  1317. STREG %r16,PT_GR16(\regs)
  1318. STREG %r17,PT_GR17(\regs)
  1319. STREG %r18,PT_GR18(\regs)
  1320. .endm
  1321. .macro reg_restore regs
  1322. LDREG PT_GR3(\regs), %r3
  1323. LDREG PT_GR4(\regs), %r4
  1324. LDREG PT_GR5(\regs), %r5
  1325. LDREG PT_GR6(\regs), %r6
  1326. LDREG PT_GR7(\regs), %r7
  1327. LDREG PT_GR8(\regs), %r8
  1328. LDREG PT_GR9(\regs), %r9
  1329. LDREG PT_GR10(\regs),%r10
  1330. LDREG PT_GR11(\regs),%r11
  1331. LDREG PT_GR12(\regs),%r12
  1332. LDREG PT_GR13(\regs),%r13
  1333. LDREG PT_GR14(\regs),%r14
  1334. LDREG PT_GR15(\regs),%r15
  1335. LDREG PT_GR16(\regs),%r16
  1336. LDREG PT_GR17(\regs),%r17
  1337. LDREG PT_GR18(\regs),%r18
  1338. .endm
  1339. .macro fork_like name
  1340. ENTRY(sys_\name\()_wrapper)
  1341. LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
  1342. ldo TASK_REGS(%r1),%r1
  1343. reg_save %r1
  1344. mfctl %cr27, %r28
  1345. ldil L%sys_\name, %r31
  1346. be R%sys_\name(%sr4,%r31)
  1347. STREG %r28, PT_CR27(%r1)
  1348. ENDPROC(sys_\name\()_wrapper)
  1349. .endm
  1350. fork_like clone
  1351. fork_like fork
  1352. fork_like vfork
  1353. /* Set the return value for the child */
  1354. ENTRY(child_return)
  1355. BL schedule_tail, %r2
  1356. nop
  1357. finish_child_return:
  1358. LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
  1359. ldo TASK_REGS(%r1),%r1 /* get pt regs */
  1360. LDREG PT_CR27(%r1), %r3
  1361. mtctl %r3, %cr27
  1362. reg_restore %r1
  1363. b syscall_exit
  1364. copy %r0,%r28
  1365. ENDPROC(child_return)
  1366. ENTRY(sys_rt_sigreturn_wrapper)
  1367. LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26
  1368. ldo TASK_REGS(%r26),%r26 /* get pt regs */
  1369. /* Don't save regs, we are going to restore them from sigcontext. */
  1370. STREG %r2, -RP_OFFSET(%r30)
  1371. #ifdef CONFIG_64BIT
  1372. ldo FRAME_SIZE(%r30), %r30
  1373. BL sys_rt_sigreturn,%r2
  1374. ldo -16(%r30),%r29 /* Reference param save area */
  1375. #else
  1376. BL sys_rt_sigreturn,%r2
  1377. ldo FRAME_SIZE(%r30), %r30
  1378. #endif
  1379. ldo -FRAME_SIZE(%r30), %r30
  1380. LDREG -RP_OFFSET(%r30), %r2
  1381. /* FIXME: I think we need to restore a few more things here. */
  1382. LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
  1383. ldo TASK_REGS(%r1),%r1 /* get pt regs */
  1384. reg_restore %r1
  1385. /* If the signal was received while the process was blocked on a
  1386. * syscall, then r2 will take us to syscall_exit; otherwise r2 will
  1387. * take us to syscall_exit_rfi and on to intr_return.
  1388. */
  1389. bv %r0(%r2)
  1390. LDREG PT_GR28(%r1),%r28 /* reload original r28 for syscall_exit */
  1391. ENDPROC(sys_rt_sigreturn_wrapper)
  1392. ENTRY(syscall_exit)
  1393. /* NOTE: HP-UX syscalls also come through here
  1394. * after hpux_syscall_exit fixes up return
  1395. * values. */
  1396. /* NOTE: Not all syscalls exit this way. rt_sigreturn will exit
  1397. * via syscall_exit_rfi if the signal was received while the process
  1398. * was running.
  1399. */
  1400. /* save return value now */
  1401. mfctl %cr30, %r1
  1402. LDREG TI_TASK(%r1),%r1
  1403. STREG %r28,TASK_PT_GR28(%r1)
  1404. #ifdef CONFIG_HPUX
  1405. /* <linux/personality.h> cannot be easily included */
  1406. #define PER_HPUX 0x10
  1407. ldw TASK_PERSONALITY(%r1),%r19
  1408. /* We can't use "CMPIB<> PER_HPUX" since "im5" field is sign extended */
  1409. ldo -PER_HPUX(%r19), %r19
  1410. cmpib,COND(<>),n 0,%r19,1f
  1411. /* Save other hpux returns if personality is PER_HPUX */
  1412. STREG %r22,TASK_PT_GR22(%r1)
  1413. STREG %r29,TASK_PT_GR29(%r1)
  1414. 1:
  1415. #endif /* CONFIG_HPUX */
  1416. /* Seems to me that dp could be wrong here, if the syscall involved
  1417. * calling a module, and nothing got round to restoring dp on return.
  1418. */
  1419. loadgp
  1420. syscall_check_resched:
  1421. /* check for reschedule */
  1422. LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19 /* long */
  1423. bb,<,n %r19, 31-TIF_NEED_RESCHED, syscall_do_resched /* forward */
  1424. .import do_signal,code
  1425. syscall_check_sig:
  1426. LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19
  1427. ldi (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME), %r26
  1428. and,COND(<>) %r19, %r26, %r0
  1429. b,n syscall_restore /* skip past if we've nothing to do */
  1430. syscall_do_signal:
  1431. /* Save callee-save registers (for sigcontext).
  1432. * FIXME: After this point the process structure should be
  1433. * consistent with all the relevant state of the process
  1434. * before the syscall. We need to verify this.
  1435. */
  1436. LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
  1437. ldo TASK_REGS(%r1), %r26 /* struct pt_regs *regs */
  1438. reg_save %r26
  1439. #ifdef CONFIG_64BIT
  1440. ldo -16(%r30),%r29 /* Reference param save area */
  1441. #endif
  1442. BL do_notify_resume,%r2
  1443. ldi 1, %r25 /* long in_syscall = 1 */
  1444. LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
  1445. ldo TASK_REGS(%r1), %r20 /* reload pt_regs */
  1446. reg_restore %r20
  1447. b,n syscall_check_sig
  1448. syscall_restore:
  1449. LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
  1450. /* Are we being ptraced? */
  1451. ldw TASK_FLAGS(%r1),%r19
  1452. ldi _TIF_SYSCALL_TRACE_MASK,%r2
  1453. and,COND(=) %r19,%r2,%r0
  1454. b,n syscall_restore_rfi
  1455. ldo TASK_PT_FR31(%r1),%r19 /* reload fpregs */
  1456. rest_fp %r19
  1457. LDREG TASK_PT_SAR(%r1),%r19 /* restore SAR */
  1458. mtsar %r19
  1459. LDREG TASK_PT_GR2(%r1),%r2 /* restore user rp */
  1460. LDREG TASK_PT_GR19(%r1),%r19
  1461. LDREG TASK_PT_GR20(%r1),%r20
  1462. LDREG TASK_PT_GR21(%r1),%r21
  1463. LDREG TASK_PT_GR22(%r1),%r22
  1464. LDREG TASK_PT_GR23(%r1),%r23
  1465. LDREG TASK_PT_GR24(%r1),%r24
  1466. LDREG TASK_PT_GR25(%r1),%r25
  1467. LDREG TASK_PT_GR26(%r1),%r26
  1468. LDREG TASK_PT_GR27(%r1),%r27 /* restore user dp */
  1469. LDREG TASK_PT_GR28(%r1),%r28 /* syscall return value */
  1470. LDREG TASK_PT_GR29(%r1),%r29
  1471. LDREG TASK_PT_GR31(%r1),%r31 /* restore syscall rp */
  1472. /* NOTE: We use rsm/ssm pair to make this operation atomic */
  1473. LDREG TASK_PT_GR30(%r1),%r1 /* Get user sp */
  1474. rsm PSW_SM_I, %r0
  1475. copy %r1,%r30 /* Restore user sp */
  1476. mfsp %sr3,%r1 /* Get user space id */
  1477. mtsp %r1,%sr7 /* Restore sr7 */
  1478. ssm PSW_SM_I, %r0
  1479. /* Set sr2 to zero for userspace syscalls to work. */
  1480. mtsp %r0,%sr2
  1481. mtsp %r1,%sr4 /* Restore sr4 */
  1482. mtsp %r1,%sr5 /* Restore sr5 */
  1483. mtsp %r1,%sr6 /* Restore sr6 */
  1484. depi 3,31,2,%r31 /* ensure return to user mode. */
  1485. #ifdef CONFIG_64BIT
  1486. /* decide whether to reset the wide mode bit
  1487. *
  1488. * For a syscall, the W bit is stored in the lowest bit
  1489. * of sp. Extract it and reset W if it is zero */
  1490. extrd,u,*<> %r30,63,1,%r1
  1491. rsm PSW_SM_W, %r0
  1492. /* now reset the lowest bit of sp if it was set */
  1493. xor %r30,%r1,%r30
  1494. #endif
  1495. be,n 0(%sr3,%r31) /* return to user space */
  1496. /* We have to return via an RFI, so that PSW T and R bits can be set
  1497. * appropriately.
  1498. * This sets up pt_regs so we can return via intr_restore, which is not
  1499. * the most efficient way of doing things, but it works.
  1500. */
  1501. syscall_restore_rfi:
  1502. ldo -1(%r0),%r2 /* Set recovery cntr to -1 */
  1503. mtctl %r2,%cr0 /* for immediate trap */
  1504. LDREG TASK_PT_PSW(%r1),%r2 /* Get old PSW */
  1505. ldi 0x0b,%r20 /* Create new PSW */
  1506. depi -1,13,1,%r20 /* C, Q, D, and I bits */
  1507. /* The values of SINGLESTEP_BIT and BLOCKSTEP_BIT are
  1508. * set in thread_info.h and converted to PA bitmap
  1509. * numbers in asm-offsets.c */
  1510. /* if ((%r19.SINGLESTEP_BIT)) { %r20.27=1} */
  1511. extru,= %r19,TIF_SINGLESTEP_PA_BIT,1,%r0
  1512. depi -1,27,1,%r20 /* R bit */
  1513. /* if ((%r19.BLOCKSTEP_BIT)) { %r20.7=1} */
  1514. extru,= %r19,TIF_BLOCKSTEP_PA_BIT,1,%r0
  1515. depi -1,7,1,%r20 /* T bit */
  1516. STREG %r20,TASK_PT_PSW(%r1)
  1517. /* Always store space registers, since sr3 can be changed (e.g. fork) */
  1518. mfsp %sr3,%r25
  1519. STREG %r25,TASK_PT_SR3(%r1)
  1520. STREG %r25,TASK_PT_SR4(%r1)
  1521. STREG %r25,TASK_PT_SR5(%r1)
  1522. STREG %r25,TASK_PT_SR6(%r1)
  1523. STREG %r25,TASK_PT_SR7(%r1)
  1524. STREG %r25,TASK_PT_IASQ0(%r1)
  1525. STREG %r25,TASK_PT_IASQ1(%r1)
  1526. /* XXX W bit??? */
  1527. /* Now if old D bit is clear, it means we didn't save all registers
  1528. * on syscall entry, so do that now. This only happens on TRACEME
  1529. * calls, or if someone attached to us while we were on a syscall.
  1530. * We could make this more efficient by not saving r3-r18, but
  1531. * then we wouldn't be able to use the common intr_restore path.
  1532. * It is only for traced processes anyway, so performance is not
  1533. * an issue.
  1534. */
  1535. bb,< %r2,30,pt_regs_ok /* Branch if D set */
  1536. ldo TASK_REGS(%r1),%r25
  1537. reg_save %r25 /* Save r3 to r18 */
  1538. /* Save the current sr */
  1539. mfsp %sr0,%r2
  1540. STREG %r2,TASK_PT_SR0(%r1)
  1541. /* Save the scratch sr */
  1542. mfsp %sr1,%r2
  1543. STREG %r2,TASK_PT_SR1(%r1)
  1544. /* sr2 should be set to zero for userspace syscalls */
  1545. STREG %r0,TASK_PT_SR2(%r1)
  1546. LDREG TASK_PT_GR31(%r1),%r2
  1547. depi 3,31,2,%r2 /* ensure return to user mode. */
  1548. STREG %r2,TASK_PT_IAOQ0(%r1)
  1549. ldo 4(%r2),%r2
  1550. STREG %r2,TASK_PT_IAOQ1(%r1)
  1551. b intr_restore
  1552. copy %r25,%r16
  1553. pt_regs_ok:
  1554. LDREG TASK_PT_IAOQ0(%r1),%r2
  1555. depi 3,31,2,%r2 /* ensure return to user mode. */
  1556. STREG %r2,TASK_PT_IAOQ0(%r1)
  1557. LDREG TASK_PT_IAOQ1(%r1),%r2
  1558. depi 3,31,2,%r2
  1559. STREG %r2,TASK_PT_IAOQ1(%r1)
  1560. b intr_restore
  1561. copy %r25,%r16
  1562. .import schedule,code
  1563. syscall_do_resched:
  1564. BL schedule,%r2
  1565. #ifdef CONFIG_64BIT
  1566. ldo -16(%r30),%r29 /* Reference param save area */
  1567. #else
  1568. nop
  1569. #endif
  1570. b syscall_check_resched /* if resched, we start over again */
  1571. nop
  1572. ENDPROC(syscall_exit)
  1573. #ifdef CONFIG_FUNCTION_TRACER
  1574. .import ftrace_function_trampoline,code
  1575. ENTRY(_mcount)
  1576. copy %r3, %arg2
  1577. b ftrace_function_trampoline
  1578. nop
  1579. ENDPROC(_mcount)
  1580. ENTRY(return_to_handler)
  1581. load32 return_trampoline, %rp
  1582. copy %ret0, %arg0
  1583. copy %ret1, %arg1
  1584. b ftrace_return_to_handler
  1585. nop
  1586. return_trampoline:
  1587. copy %ret0, %rp
  1588. copy %r23, %ret0
  1589. copy %r24, %ret1
  1590. .globl ftrace_stub
  1591. ftrace_stub:
  1592. bv %r0(%rp)
  1593. nop
  1594. ENDPROC(return_to_handler)
  1595. #endif /* CONFIG_FUNCTION_TRACER */
  1596. #ifdef CONFIG_IRQSTACKS
  1597. /* void call_on_stack(unsigned long param1, void *func,
  1598. unsigned long new_stack) */
  1599. ENTRY(call_on_stack)
  1600. copy %sp, %r1
  1601. /* Regarding the HPPA calling conventions for function pointers,
  1602. we assume the PIC register is not changed across call. For
  1603. CONFIG_64BIT, the argument pointer is left to point at the
  1604. argument region allocated for the call to call_on_stack. */
  1605. # ifdef CONFIG_64BIT
  1606. /* Switch to new stack. We allocate two 128 byte frames. */
  1607. ldo 256(%arg2), %sp
  1608. /* Save previous stack pointer and return pointer in frame marker */
  1609. STREG %rp, -144(%sp)
  1610. /* Calls always use function descriptor */
  1611. LDREG 16(%arg1), %arg1
  1612. bve,l (%arg1), %rp
  1613. STREG %r1, -136(%sp)
  1614. LDREG -144(%sp), %rp
  1615. bve (%rp)
  1616. LDREG -136(%sp), %sp
  1617. # else
  1618. /* Switch to new stack. We allocate two 64 byte frames. */
  1619. ldo 128(%arg2), %sp
  1620. /* Save previous stack pointer and return pointer in frame marker */
  1621. STREG %r1, -68(%sp)
  1622. STREG %rp, -84(%sp)
  1623. /* Calls use function descriptor if PLABEL bit is set */
  1624. bb,>=,n %arg1, 30, 1f
  1625. depwi 0,31,2, %arg1
  1626. LDREG 0(%arg1), %arg1
  1627. 1:
  1628. be,l 0(%sr4,%arg1), %sr0, %r31
  1629. copy %r31, %rp
  1630. LDREG -84(%sp), %rp
  1631. bv (%rp)
  1632. LDREG -68(%sp), %sp
  1633. # endif /* CONFIG_64BIT */
  1634. ENDPROC(call_on_stack)
  1635. #endif /* CONFIG_IRQSTACKS */
  1636. get_register:
  1637. /*
  1638. * get_register is used by the non access tlb miss handlers to
  1639. * copy the value of the general register specified in r8 into
  1640. * r1. This routine can't be used for shadowed registers, since
  1641. * the rfir will restore the original value. So, for the shadowed
  1642. * registers we put a -1 into r1 to indicate that the register
  1643. * should not be used (the register being copied could also have
  1644. * a -1 in it, but that is OK, it just means that we will have
  1645. * to use the slow path instead).
  1646. */
  1647. blr %r8,%r0
  1648. nop
  1649. bv %r0(%r25) /* r0 */
  1650. copy %r0,%r1
  1651. bv %r0(%r25) /* r1 - shadowed */
  1652. ldi -1,%r1
  1653. bv %r0(%r25) /* r2 */
  1654. copy %r2,%r1
  1655. bv %r0(%r25) /* r3 */
  1656. copy %r3,%r1
  1657. bv %r0(%r25) /* r4 */
  1658. copy %r4,%r1
  1659. bv %r0(%r25) /* r5 */
  1660. copy %r5,%r1
  1661. bv %r0(%r25) /* r6 */
  1662. copy %r6,%r1
  1663. bv %r0(%r25) /* r7 */
  1664. copy %r7,%r1
  1665. bv %r0(%r25) /* r8 - shadowed */
  1666. ldi -1,%r1
  1667. bv %r0(%r25) /* r9 - shadowed */
  1668. ldi -1,%r1
  1669. bv %r0(%r25) /* r10 */
  1670. copy %r10,%r1
  1671. bv %r0(%r25) /* r11 */
  1672. copy %r11,%r1
  1673. bv %r0(%r25) /* r12 */
  1674. copy %r12,%r1
  1675. bv %r0(%r25) /* r13 */
  1676. copy %r13,%r1
  1677. bv %r0(%r25) /* r14 */
  1678. copy %r14,%r1
  1679. bv %r0(%r25) /* r15 */
  1680. copy %r15,%r1
  1681. bv %r0(%r25) /* r16 - shadowed */
  1682. ldi -1,%r1
  1683. bv %r0(%r25) /* r17 - shadowed */
  1684. ldi -1,%r1
  1685. bv %r0(%r25) /* r18 */
  1686. copy %r18,%r1
  1687. bv %r0(%r25) /* r19 */
  1688. copy %r19,%r1
  1689. bv %r0(%r25) /* r20 */
  1690. copy %r20,%r1
  1691. bv %r0(%r25) /* r21 */
  1692. copy %r21,%r1
  1693. bv %r0(%r25) /* r22 */
  1694. copy %r22,%r1
  1695. bv %r0(%r25) /* r23 */
  1696. copy %r23,%r1
  1697. bv %r0(%r25) /* r24 - shadowed */
  1698. ldi -1,%r1
  1699. bv %r0(%r25) /* r25 - shadowed */
  1700. ldi -1,%r1
  1701. bv %r0(%r25) /* r26 */
  1702. copy %r26,%r1
  1703. bv %r0(%r25) /* r27 */
  1704. copy %r27,%r1
  1705. bv %r0(%r25) /* r28 */
  1706. copy %r28,%r1
  1707. bv %r0(%r25) /* r29 */
  1708. copy %r29,%r1
  1709. bv %r0(%r25) /* r30 */
  1710. copy %r30,%r1
  1711. bv %r0(%r25) /* r31 */
  1712. copy %r31,%r1
  1713. set_register:
  1714. /*
  1715. * set_register is used by the non access tlb miss handlers to
  1716. * copy the value of r1 into the general register specified in
  1717. * r8.
  1718. */
  1719. blr %r8,%r0
  1720. nop
  1721. bv %r0(%r25) /* r0 (silly, but it is a place holder) */
  1722. copy %r1,%r0
  1723. bv %r0(%r25) /* r1 */
  1724. copy %r1,%r1
  1725. bv %r0(%r25) /* r2 */
  1726. copy %r1,%r2
  1727. bv %r0(%r25) /* r3 */
  1728. copy %r1,%r3
  1729. bv %r0(%r25) /* r4 */
  1730. copy %r1,%r4
  1731. bv %r0(%r25) /* r5 */
  1732. copy %r1,%r5
  1733. bv %r0(%r25) /* r6 */
  1734. copy %r1,%r6
  1735. bv %r0(%r25) /* r7 */
  1736. copy %r1,%r7
  1737. bv %r0(%r25) /* r8 */
  1738. copy %r1,%r8
  1739. bv %r0(%r25) /* r9 */
  1740. copy %r1,%r9
  1741. bv %r0(%r25) /* r10 */
  1742. copy %r1,%r10
  1743. bv %r0(%r25) /* r11 */
  1744. copy %r1,%r11
  1745. bv %r0(%r25) /* r12 */
  1746. copy %r1,%r12
  1747. bv %r0(%r25) /* r13 */
  1748. copy %r1,%r13
  1749. bv %r0(%r25) /* r14 */
  1750. copy %r1,%r14
  1751. bv %r0(%r25) /* r15 */
  1752. copy %r1,%r15
  1753. bv %r0(%r25) /* r16 */
  1754. copy %r1,%r16
  1755. bv %r0(%r25) /* r17 */
  1756. copy %r1,%r17
  1757. bv %r0(%r25) /* r18 */
  1758. copy %r1,%r18
  1759. bv %r0(%r25) /* r19 */
  1760. copy %r1,%r19
  1761. bv %r0(%r25) /* r20 */
  1762. copy %r1,%r20
  1763. bv %r0(%r25) /* r21 */
  1764. copy %r1,%r21
  1765. bv %r0(%r25) /* r22 */
  1766. copy %r1,%r22
  1767. bv %r0(%r25) /* r23 */
  1768. copy %r1,%r23
  1769. bv %r0(%r25) /* r24 */
  1770. copy %r1,%r24
  1771. bv %r0(%r25) /* r25 */
  1772. copy %r1,%r25
  1773. bv %r0(%r25) /* r26 */
  1774. copy %r1,%r26
  1775. bv %r0(%r25) /* r27 */
  1776. copy %r1,%r27
  1777. bv %r0(%r25) /* r28 */
  1778. copy %r1,%r28
  1779. bv %r0(%r25) /* r29 */
  1780. copy %r1,%r29
  1781. bv %r0(%r25) /* r30 */
  1782. copy %r1,%r30
  1783. bv %r0(%r25) /* r31 */
  1784. copy %r1,%r31