rt3883.c 6.2 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify it
  3. * under the terms of the GNU General Public License version 2 as published
  4. * by the Free Software Foundation.
  5. *
  6. * Parts of this file are based on Ralink's 2.6.21 BSP
  7. *
  8. * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  9. * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  10. * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/init.h>
  14. #include <linux/module.h>
  15. #include <asm/mipsregs.h>
  16. #include <asm/mach-ralink/ralink_regs.h>
  17. #include <asm/mach-ralink/rt3883.h>
  18. #include "common.h"
  19. static struct ralink_pinmux_grp mode_mux[] = {
  20. {
  21. .name = "i2c",
  22. .mask = RT3883_GPIO_MODE_I2C,
  23. .gpio_first = RT3883_GPIO_I2C_SD,
  24. .gpio_last = RT3883_GPIO_I2C_SCLK,
  25. }, {
  26. .name = "spi",
  27. .mask = RT3883_GPIO_MODE_SPI,
  28. .gpio_first = RT3883_GPIO_SPI_CS0,
  29. .gpio_last = RT3883_GPIO_SPI_MISO,
  30. }, {
  31. .name = "uartlite",
  32. .mask = RT3883_GPIO_MODE_UART1,
  33. .gpio_first = RT3883_GPIO_UART1_TXD,
  34. .gpio_last = RT3883_GPIO_UART1_RXD,
  35. }, {
  36. .name = "jtag",
  37. .mask = RT3883_GPIO_MODE_JTAG,
  38. .gpio_first = RT3883_GPIO_JTAG_TDO,
  39. .gpio_last = RT3883_GPIO_JTAG_TCLK,
  40. }, {
  41. .name = "mdio",
  42. .mask = RT3883_GPIO_MODE_MDIO,
  43. .gpio_first = RT3883_GPIO_MDIO_MDC,
  44. .gpio_last = RT3883_GPIO_MDIO_MDIO,
  45. }, {
  46. .name = "ge1",
  47. .mask = RT3883_GPIO_MODE_GE1,
  48. .gpio_first = RT3883_GPIO_GE1_TXD0,
  49. .gpio_last = RT3883_GPIO_GE1_RXCLK,
  50. }, {
  51. .name = "ge2",
  52. .mask = RT3883_GPIO_MODE_GE2,
  53. .gpio_first = RT3883_GPIO_GE2_TXD0,
  54. .gpio_last = RT3883_GPIO_GE2_RXCLK,
  55. }, {
  56. .name = "pci",
  57. .mask = RT3883_GPIO_MODE_PCI,
  58. .gpio_first = RT3883_GPIO_PCI_AD0,
  59. .gpio_last = RT3883_GPIO_PCI_AD31,
  60. }, {
  61. .name = "lna a",
  62. .mask = RT3883_GPIO_MODE_LNA_A,
  63. .gpio_first = RT3883_GPIO_LNA_PE_A0,
  64. .gpio_last = RT3883_GPIO_LNA_PE_A2,
  65. }, {
  66. .name = "lna g",
  67. .mask = RT3883_GPIO_MODE_LNA_G,
  68. .gpio_first = RT3883_GPIO_LNA_PE_G0,
  69. .gpio_last = RT3883_GPIO_LNA_PE_G2,
  70. }, {0}
  71. };
  72. static struct ralink_pinmux_grp uart_mux[] = {
  73. {
  74. .name = "uartf",
  75. .mask = RT3883_GPIO_MODE_UARTF,
  76. .gpio_first = RT3883_GPIO_7,
  77. .gpio_last = RT3883_GPIO_14,
  78. }, {
  79. .name = "pcm uartf",
  80. .mask = RT3883_GPIO_MODE_PCM_UARTF,
  81. .gpio_first = RT3883_GPIO_7,
  82. .gpio_last = RT3883_GPIO_14,
  83. }, {
  84. .name = "pcm i2s",
  85. .mask = RT3883_GPIO_MODE_PCM_I2S,
  86. .gpio_first = RT3883_GPIO_7,
  87. .gpio_last = RT3883_GPIO_14,
  88. }, {
  89. .name = "i2s uartf",
  90. .mask = RT3883_GPIO_MODE_I2S_UARTF,
  91. .gpio_first = RT3883_GPIO_7,
  92. .gpio_last = RT3883_GPIO_14,
  93. }, {
  94. .name = "pcm gpio",
  95. .mask = RT3883_GPIO_MODE_PCM_GPIO,
  96. .gpio_first = RT3883_GPIO_11,
  97. .gpio_last = RT3883_GPIO_14,
  98. }, {
  99. .name = "gpio uartf",
  100. .mask = RT3883_GPIO_MODE_GPIO_UARTF,
  101. .gpio_first = RT3883_GPIO_7,
  102. .gpio_last = RT3883_GPIO_10,
  103. }, {
  104. .name = "gpio i2s",
  105. .mask = RT3883_GPIO_MODE_GPIO_I2S,
  106. .gpio_first = RT3883_GPIO_7,
  107. .gpio_last = RT3883_GPIO_10,
  108. }, {
  109. .name = "gpio",
  110. .mask = RT3883_GPIO_MODE_GPIO,
  111. }, {0}
  112. };
  113. static struct ralink_pinmux_grp pci_mux[] = {
  114. {
  115. .name = "pci-dev",
  116. .mask = 0,
  117. .gpio_first = RT3883_GPIO_PCI_AD0,
  118. .gpio_last = RT3883_GPIO_PCI_AD31,
  119. }, {
  120. .name = "pci-host2",
  121. .mask = 1,
  122. .gpio_first = RT3883_GPIO_PCI_AD0,
  123. .gpio_last = RT3883_GPIO_PCI_AD31,
  124. }, {
  125. .name = "pci-host1",
  126. .mask = 2,
  127. .gpio_first = RT3883_GPIO_PCI_AD0,
  128. .gpio_last = RT3883_GPIO_PCI_AD31,
  129. }, {
  130. .name = "pci-fnc",
  131. .mask = 3,
  132. .gpio_first = RT3883_GPIO_PCI_AD0,
  133. .gpio_last = RT3883_GPIO_PCI_AD31,
  134. }, {
  135. .name = "pci-gpio",
  136. .mask = 7,
  137. .gpio_first = RT3883_GPIO_PCI_AD0,
  138. .gpio_last = RT3883_GPIO_PCI_AD31,
  139. }, {0}
  140. };
  141. static void rt3883_wdt_reset(void)
  142. {
  143. u32 t;
  144. /* enable WDT reset output on GPIO 2 */
  145. t = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
  146. t |= RT3883_SYSCFG1_GPIO2_AS_WDT_OUT;
  147. rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
  148. }
  149. struct ralink_pinmux rt_gpio_pinmux = {
  150. .mode = mode_mux,
  151. .uart = uart_mux,
  152. .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
  153. .uart_mask = RT3883_GPIO_MODE_UART0_MASK,
  154. .wdt_reset = rt3883_wdt_reset,
  155. .pci = pci_mux,
  156. .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
  157. .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
  158. };
  159. void __init ralink_clk_init(void)
  160. {
  161. unsigned long cpu_rate, sys_rate;
  162. u32 syscfg0;
  163. u32 clksel;
  164. u32 ddr2;
  165. syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
  166. clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
  167. RT3883_SYSCFG0_CPUCLK_MASK);
  168. ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
  169. switch (clksel) {
  170. case RT3883_SYSCFG0_CPUCLK_250:
  171. cpu_rate = 250000000;
  172. sys_rate = (ddr2) ? 125000000 : 83000000;
  173. break;
  174. case RT3883_SYSCFG0_CPUCLK_384:
  175. cpu_rate = 384000000;
  176. sys_rate = (ddr2) ? 128000000 : 96000000;
  177. break;
  178. case RT3883_SYSCFG0_CPUCLK_480:
  179. cpu_rate = 480000000;
  180. sys_rate = (ddr2) ? 160000000 : 120000000;
  181. break;
  182. case RT3883_SYSCFG0_CPUCLK_500:
  183. cpu_rate = 500000000;
  184. sys_rate = (ddr2) ? 166000000 : 125000000;
  185. break;
  186. }
  187. ralink_clk_add("cpu", cpu_rate);
  188. ralink_clk_add("10000100.timer", sys_rate);
  189. ralink_clk_add("10000120.watchdog", sys_rate);
  190. ralink_clk_add("10000500.uart", 40000000);
  191. ralink_clk_add("10000b00.spi", sys_rate);
  192. ralink_clk_add("10000c00.uartlite", 40000000);
  193. ralink_clk_add("10100000.ethernet", sys_rate);
  194. }
  195. void __init ralink_of_remap(void)
  196. {
  197. rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
  198. rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
  199. if (!rt_sysc_membase || !rt_memc_membase)
  200. panic("Failed to remap core resources");
  201. }
  202. void prom_soc_init(struct ralink_soc_info *soc_info)
  203. {
  204. void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
  205. const char *name;
  206. u32 n0;
  207. u32 n1;
  208. u32 id;
  209. n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3);
  210. n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7);
  211. id = __raw_readl(sysc + RT3883_SYSC_REG_REVID);
  212. if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) {
  213. soc_info->compatible = "ralink,rt3883-soc";
  214. name = "RT3883";
  215. } else {
  216. panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1);
  217. }
  218. snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
  219. "Ralink %s ver:%u eco:%u",
  220. name,
  221. (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
  222. (id & RT3883_REVID_ECO_ID_MASK));
  223. soc_info->mem_base = RT3883_SDRAM_BASE;
  224. soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
  225. soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
  226. }