rt305x.c 7.5 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify it
  3. * under the terms of the GNU General Public License version 2 as published
  4. * by the Free Software Foundation.
  5. *
  6. * Parts of this file are based on Ralink's 2.6.21 BSP
  7. *
  8. * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  9. * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  10. * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/init.h>
  14. #include <linux/module.h>
  15. #include <asm/mipsregs.h>
  16. #include <asm/mach-ralink/ralink_regs.h>
  17. #include <asm/mach-ralink/rt305x.h>
  18. #include "common.h"
  19. enum rt305x_soc_type rt305x_soc;
  20. static struct ralink_pinmux_grp mode_mux[] = {
  21. {
  22. .name = "i2c",
  23. .mask = RT305X_GPIO_MODE_I2C,
  24. .gpio_first = RT305X_GPIO_I2C_SD,
  25. .gpio_last = RT305X_GPIO_I2C_SCLK,
  26. }, {
  27. .name = "spi",
  28. .mask = RT305X_GPIO_MODE_SPI,
  29. .gpio_first = RT305X_GPIO_SPI_EN,
  30. .gpio_last = RT305X_GPIO_SPI_CLK,
  31. }, {
  32. .name = "uartlite",
  33. .mask = RT305X_GPIO_MODE_UART1,
  34. .gpio_first = RT305X_GPIO_UART1_TXD,
  35. .gpio_last = RT305X_GPIO_UART1_RXD,
  36. }, {
  37. .name = "jtag",
  38. .mask = RT305X_GPIO_MODE_JTAG,
  39. .gpio_first = RT305X_GPIO_JTAG_TDO,
  40. .gpio_last = RT305X_GPIO_JTAG_TDI,
  41. }, {
  42. .name = "mdio",
  43. .mask = RT305X_GPIO_MODE_MDIO,
  44. .gpio_first = RT305X_GPIO_MDIO_MDC,
  45. .gpio_last = RT305X_GPIO_MDIO_MDIO,
  46. }, {
  47. .name = "sdram",
  48. .mask = RT305X_GPIO_MODE_SDRAM,
  49. .gpio_first = RT305X_GPIO_SDRAM_MD16,
  50. .gpio_last = RT305X_GPIO_SDRAM_MD31,
  51. }, {
  52. .name = "rgmii",
  53. .mask = RT305X_GPIO_MODE_RGMII,
  54. .gpio_first = RT305X_GPIO_GE0_TXD0,
  55. .gpio_last = RT305X_GPIO_GE0_RXCLK,
  56. }, {0}
  57. };
  58. static struct ralink_pinmux_grp uart_mux[] = {
  59. {
  60. .name = "uartf",
  61. .mask = RT305X_GPIO_MODE_UARTF,
  62. .gpio_first = RT305X_GPIO_7,
  63. .gpio_last = RT305X_GPIO_14,
  64. }, {
  65. .name = "pcm uartf",
  66. .mask = RT305X_GPIO_MODE_PCM_UARTF,
  67. .gpio_first = RT305X_GPIO_7,
  68. .gpio_last = RT305X_GPIO_14,
  69. }, {
  70. .name = "pcm i2s",
  71. .mask = RT305X_GPIO_MODE_PCM_I2S,
  72. .gpio_first = RT305X_GPIO_7,
  73. .gpio_last = RT305X_GPIO_14,
  74. }, {
  75. .name = "i2s uartf",
  76. .mask = RT305X_GPIO_MODE_I2S_UARTF,
  77. .gpio_first = RT305X_GPIO_7,
  78. .gpio_last = RT305X_GPIO_14,
  79. }, {
  80. .name = "pcm gpio",
  81. .mask = RT305X_GPIO_MODE_PCM_GPIO,
  82. .gpio_first = RT305X_GPIO_10,
  83. .gpio_last = RT305X_GPIO_14,
  84. }, {
  85. .name = "gpio uartf",
  86. .mask = RT305X_GPIO_MODE_GPIO_UARTF,
  87. .gpio_first = RT305X_GPIO_7,
  88. .gpio_last = RT305X_GPIO_10,
  89. }, {
  90. .name = "gpio i2s",
  91. .mask = RT305X_GPIO_MODE_GPIO_I2S,
  92. .gpio_first = RT305X_GPIO_7,
  93. .gpio_last = RT305X_GPIO_10,
  94. }, {
  95. .name = "gpio",
  96. .mask = RT305X_GPIO_MODE_GPIO,
  97. }, {0}
  98. };
  99. static void rt305x_wdt_reset(void)
  100. {
  101. u32 t;
  102. /* enable WDT reset output on pin SRAM_CS_N */
  103. t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
  104. t |= RT305X_SYSCFG_SRAM_CS0_MODE_WDT <<
  105. RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT;
  106. rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
  107. }
  108. struct ralink_pinmux rt_gpio_pinmux = {
  109. .mode = mode_mux,
  110. .uart = uart_mux,
  111. .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
  112. .uart_mask = RT305X_GPIO_MODE_UART0_MASK,
  113. .wdt_reset = rt305x_wdt_reset,
  114. };
  115. static unsigned long rt5350_get_mem_size(void)
  116. {
  117. void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
  118. unsigned long ret;
  119. u32 t;
  120. t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
  121. t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
  122. RT5350_SYSCFG0_DRAM_SIZE_MASK;
  123. switch (t) {
  124. case RT5350_SYSCFG0_DRAM_SIZE_2M:
  125. ret = 2;
  126. break;
  127. case RT5350_SYSCFG0_DRAM_SIZE_8M:
  128. ret = 8;
  129. break;
  130. case RT5350_SYSCFG0_DRAM_SIZE_16M:
  131. ret = 16;
  132. break;
  133. case RT5350_SYSCFG0_DRAM_SIZE_32M:
  134. ret = 32;
  135. break;
  136. case RT5350_SYSCFG0_DRAM_SIZE_64M:
  137. ret = 64;
  138. break;
  139. default:
  140. panic("rt5350: invalid DRAM size: %u", t);
  141. break;
  142. }
  143. return ret;
  144. }
  145. void __init ralink_clk_init(void)
  146. {
  147. unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
  148. unsigned long wmac_rate = 40000000;
  149. u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
  150. if (soc_is_rt305x() || soc_is_rt3350()) {
  151. t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
  152. RT305X_SYSCFG_CPUCLK_MASK;
  153. switch (t) {
  154. case RT305X_SYSCFG_CPUCLK_LOW:
  155. cpu_rate = 320000000;
  156. break;
  157. case RT305X_SYSCFG_CPUCLK_HIGH:
  158. cpu_rate = 384000000;
  159. break;
  160. }
  161. sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
  162. } else if (soc_is_rt3352()) {
  163. t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
  164. RT3352_SYSCFG0_CPUCLK_MASK;
  165. switch (t) {
  166. case RT3352_SYSCFG0_CPUCLK_LOW:
  167. cpu_rate = 384000000;
  168. break;
  169. case RT3352_SYSCFG0_CPUCLK_HIGH:
  170. cpu_rate = 400000000;
  171. break;
  172. }
  173. sys_rate = wdt_rate = cpu_rate / 3;
  174. uart_rate = 40000000;
  175. } else if (soc_is_rt5350()) {
  176. t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
  177. RT5350_SYSCFG0_CPUCLK_MASK;
  178. switch (t) {
  179. case RT5350_SYSCFG0_CPUCLK_360:
  180. cpu_rate = 360000000;
  181. sys_rate = cpu_rate / 3;
  182. break;
  183. case RT5350_SYSCFG0_CPUCLK_320:
  184. cpu_rate = 320000000;
  185. sys_rate = cpu_rate / 4;
  186. break;
  187. case RT5350_SYSCFG0_CPUCLK_300:
  188. cpu_rate = 300000000;
  189. sys_rate = cpu_rate / 3;
  190. break;
  191. default:
  192. BUG();
  193. }
  194. uart_rate = 40000000;
  195. wdt_rate = sys_rate;
  196. } else {
  197. BUG();
  198. }
  199. if (soc_is_rt3352() || soc_is_rt5350()) {
  200. u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
  201. if (!(val & RT3352_CLKCFG0_XTAL_SEL))
  202. wmac_rate = 20000000;
  203. }
  204. ralink_clk_add("cpu", cpu_rate);
  205. ralink_clk_add("10000b00.spi", sys_rate);
  206. ralink_clk_add("10000100.timer", wdt_rate);
  207. ralink_clk_add("10000120.watchdog", wdt_rate);
  208. ralink_clk_add("10000500.uart", uart_rate);
  209. ralink_clk_add("10000c00.uartlite", uart_rate);
  210. ralink_clk_add("10100000.ethernet", sys_rate);
  211. ralink_clk_add("10180000.wmac", wmac_rate);
  212. }
  213. void __init ralink_of_remap(void)
  214. {
  215. rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
  216. rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc");
  217. if (!rt_sysc_membase || !rt_memc_membase)
  218. panic("Failed to remap core resources");
  219. }
  220. void prom_soc_init(struct ralink_soc_info *soc_info)
  221. {
  222. void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
  223. unsigned char *name;
  224. u32 n0;
  225. u32 n1;
  226. u32 id;
  227. n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
  228. n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
  229. if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
  230. unsigned long icache_sets;
  231. icache_sets = (read_c0_config1() >> 22) & 7;
  232. if (icache_sets == 1) {
  233. rt305x_soc = RT305X_SOC_RT3050;
  234. name = "RT3050";
  235. soc_info->compatible = "ralink,rt3050-soc";
  236. } else {
  237. rt305x_soc = RT305X_SOC_RT3052;
  238. name = "RT3052";
  239. soc_info->compatible = "ralink,rt3052-soc";
  240. }
  241. } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
  242. rt305x_soc = RT305X_SOC_RT3350;
  243. name = "RT3350";
  244. soc_info->compatible = "ralink,rt3350-soc";
  245. } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
  246. rt305x_soc = RT305X_SOC_RT3352;
  247. name = "RT3352";
  248. soc_info->compatible = "ralink,rt3352-soc";
  249. } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
  250. rt305x_soc = RT305X_SOC_RT5350;
  251. name = "RT5350";
  252. soc_info->compatible = "ralink,rt5350-soc";
  253. } else {
  254. panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
  255. }
  256. id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
  257. snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
  258. "Ralink %s id:%u rev:%u",
  259. name,
  260. (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
  261. (id & CHIP_ID_REV_MASK));
  262. soc_info->mem_base = RT305X_SDRAM_BASE;
  263. if (soc_is_rt5350()) {
  264. soc_info->mem_size = rt5350_get_mem_size();
  265. } else if (soc_is_rt305x() || soc_is_rt3350()) {
  266. soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
  267. soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
  268. } else if (soc_is_rt3352()) {
  269. soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
  270. soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
  271. }
  272. }