rt288x.c 3.3 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify it
  3. * under the terms of the GNU General Public License version 2 as published
  4. * by the Free Software Foundation.
  5. *
  6. * Parts of this file are based on Ralink's 2.6.21 BSP
  7. *
  8. * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  9. * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  10. * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/init.h>
  14. #include <linux/module.h>
  15. #include <asm/mipsregs.h>
  16. #include <asm/mach-ralink/ralink_regs.h>
  17. #include <asm/mach-ralink/rt288x.h>
  18. #include "common.h"
  19. static struct ralink_pinmux_grp mode_mux[] = {
  20. {
  21. .name = "i2c",
  22. .mask = RT2880_GPIO_MODE_I2C,
  23. .gpio_first = 1,
  24. .gpio_last = 2,
  25. }, {
  26. .name = "spi",
  27. .mask = RT2880_GPIO_MODE_SPI,
  28. .gpio_first = 3,
  29. .gpio_last = 6,
  30. }, {
  31. .name = "uartlite",
  32. .mask = RT2880_GPIO_MODE_UART0,
  33. .gpio_first = 7,
  34. .gpio_last = 14,
  35. }, {
  36. .name = "jtag",
  37. .mask = RT2880_GPIO_MODE_JTAG,
  38. .gpio_first = 17,
  39. .gpio_last = 21,
  40. }, {
  41. .name = "mdio",
  42. .mask = RT2880_GPIO_MODE_MDIO,
  43. .gpio_first = 22,
  44. .gpio_last = 23,
  45. }, {
  46. .name = "sdram",
  47. .mask = RT2880_GPIO_MODE_SDRAM,
  48. .gpio_first = 24,
  49. .gpio_last = 39,
  50. }, {
  51. .name = "pci",
  52. .mask = RT2880_GPIO_MODE_PCI,
  53. .gpio_first = 40,
  54. .gpio_last = 71,
  55. }, {0}
  56. };
  57. static void rt288x_wdt_reset(void)
  58. {
  59. u32 t;
  60. /* enable WDT reset output on pin SRAM_CS_N */
  61. t = rt_sysc_r32(SYSC_REG_CLKCFG);
  62. t |= CLKCFG_SRAM_CS_N_WDT;
  63. rt_sysc_w32(t, SYSC_REG_CLKCFG);
  64. }
  65. struct ralink_pinmux rt_gpio_pinmux = {
  66. .mode = mode_mux,
  67. .wdt_reset = rt288x_wdt_reset,
  68. };
  69. void __init ralink_clk_init(void)
  70. {
  71. unsigned long cpu_rate;
  72. u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
  73. t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
  74. switch (t) {
  75. case SYSTEM_CONFIG_CPUCLK_250:
  76. cpu_rate = 250000000;
  77. break;
  78. case SYSTEM_CONFIG_CPUCLK_266:
  79. cpu_rate = 266666667;
  80. break;
  81. case SYSTEM_CONFIG_CPUCLK_280:
  82. cpu_rate = 280000000;
  83. break;
  84. case SYSTEM_CONFIG_CPUCLK_300:
  85. cpu_rate = 300000000;
  86. break;
  87. }
  88. ralink_clk_add("cpu", cpu_rate);
  89. ralink_clk_add("300100.timer", cpu_rate / 2);
  90. ralink_clk_add("300120.watchdog", cpu_rate / 2);
  91. ralink_clk_add("300500.uart", cpu_rate / 2);
  92. ralink_clk_add("300c00.uartlite", cpu_rate / 2);
  93. ralink_clk_add("400000.ethernet", cpu_rate / 2);
  94. }
  95. void __init ralink_of_remap(void)
  96. {
  97. rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
  98. rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");
  99. if (!rt_sysc_membase || !rt_memc_membase)
  100. panic("Failed to remap core resources");
  101. }
  102. void prom_soc_init(struct ralink_soc_info *soc_info)
  103. {
  104. void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
  105. const char *name;
  106. u32 n0;
  107. u32 n1;
  108. u32 id;
  109. n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
  110. n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
  111. id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
  112. if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) {
  113. soc_info->compatible = "ralink,r2880-soc";
  114. name = "RT2880";
  115. } else {
  116. panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1);
  117. }
  118. snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
  119. "Ralink %s id:%u rev:%u",
  120. name,
  121. (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
  122. (id & CHIP_ID_REV_MASK));
  123. soc_info->mem_base = RT2880_SDRAM_BASE;
  124. soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
  125. soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
  126. }