mt7620.c 5.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234
  1. /*
  2. * This program is free software; you can redistribute it and/or modify it
  3. * under the terms of the GNU General Public License version 2 as published
  4. * by the Free Software Foundation.
  5. *
  6. * Parts of this file are based on Ralink's 2.6.21 BSP
  7. *
  8. * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  9. * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  10. * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/init.h>
  14. #include <linux/module.h>
  15. #include <asm/mipsregs.h>
  16. #include <asm/mach-ralink/ralink_regs.h>
  17. #include <asm/mach-ralink/mt7620.h>
  18. #include "common.h"
  19. /* does the board have sdram or ddram */
  20. static int dram_type;
  21. /* the pll dividers */
  22. static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
  23. static struct ralink_pinmux_grp mode_mux[] = {
  24. {
  25. .name = "i2c",
  26. .mask = MT7620_GPIO_MODE_I2C,
  27. .gpio_first = 1,
  28. .gpio_last = 2,
  29. }, {
  30. .name = "spi",
  31. .mask = MT7620_GPIO_MODE_SPI,
  32. .gpio_first = 3,
  33. .gpio_last = 6,
  34. }, {
  35. .name = "uartlite",
  36. .mask = MT7620_GPIO_MODE_UART1,
  37. .gpio_first = 15,
  38. .gpio_last = 16,
  39. }, {
  40. .name = "wdt",
  41. .mask = MT7620_GPIO_MODE_WDT,
  42. .gpio_first = 17,
  43. .gpio_last = 17,
  44. }, {
  45. .name = "mdio",
  46. .mask = MT7620_GPIO_MODE_MDIO,
  47. .gpio_first = 22,
  48. .gpio_last = 23,
  49. }, {
  50. .name = "rgmii1",
  51. .mask = MT7620_GPIO_MODE_RGMII1,
  52. .gpio_first = 24,
  53. .gpio_last = 35,
  54. }, {
  55. .name = "spi refclk",
  56. .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
  57. .gpio_first = 37,
  58. .gpio_last = 39,
  59. }, {
  60. .name = "jtag",
  61. .mask = MT7620_GPIO_MODE_JTAG,
  62. .gpio_first = 40,
  63. .gpio_last = 44,
  64. }, {
  65. /* shared lines with jtag */
  66. .name = "ephy",
  67. .mask = MT7620_GPIO_MODE_EPHY,
  68. .gpio_first = 40,
  69. .gpio_last = 44,
  70. }, {
  71. .name = "nand",
  72. .mask = MT7620_GPIO_MODE_JTAG,
  73. .gpio_first = 45,
  74. .gpio_last = 59,
  75. }, {
  76. .name = "rgmii2",
  77. .mask = MT7620_GPIO_MODE_RGMII2,
  78. .gpio_first = 60,
  79. .gpio_last = 71,
  80. }, {
  81. .name = "wled",
  82. .mask = MT7620_GPIO_MODE_WLED,
  83. .gpio_first = 72,
  84. .gpio_last = 72,
  85. }, {0}
  86. };
  87. static struct ralink_pinmux_grp uart_mux[] = {
  88. {
  89. .name = "uartf",
  90. .mask = MT7620_GPIO_MODE_UARTF,
  91. .gpio_first = 7,
  92. .gpio_last = 14,
  93. }, {
  94. .name = "pcm uartf",
  95. .mask = MT7620_GPIO_MODE_PCM_UARTF,
  96. .gpio_first = 7,
  97. .gpio_last = 14,
  98. }, {
  99. .name = "pcm i2s",
  100. .mask = MT7620_GPIO_MODE_PCM_I2S,
  101. .gpio_first = 7,
  102. .gpio_last = 14,
  103. }, {
  104. .name = "i2s uartf",
  105. .mask = MT7620_GPIO_MODE_I2S_UARTF,
  106. .gpio_first = 7,
  107. .gpio_last = 14,
  108. }, {
  109. .name = "pcm gpio",
  110. .mask = MT7620_GPIO_MODE_PCM_GPIO,
  111. .gpio_first = 11,
  112. .gpio_last = 14,
  113. }, {
  114. .name = "gpio uartf",
  115. .mask = MT7620_GPIO_MODE_GPIO_UARTF,
  116. .gpio_first = 7,
  117. .gpio_last = 10,
  118. }, {
  119. .name = "gpio i2s",
  120. .mask = MT7620_GPIO_MODE_GPIO_I2S,
  121. .gpio_first = 7,
  122. .gpio_last = 10,
  123. }, {
  124. .name = "gpio",
  125. .mask = MT7620_GPIO_MODE_GPIO,
  126. }, {0}
  127. };
  128. struct ralink_pinmux rt_gpio_pinmux = {
  129. .mode = mode_mux,
  130. .uart = uart_mux,
  131. .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
  132. .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
  133. };
  134. void __init ralink_clk_init(void)
  135. {
  136. unsigned long cpu_rate, sys_rate;
  137. u32 c0 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
  138. u32 c1 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
  139. u32 swconfig = (c0 >> CPLL_SW_CONFIG_SHIFT) & CPLL_SW_CONFIG_MASK;
  140. u32 cpu_clk = (c1 >> CPLL_CPU_CLK_SHIFT) & CPLL_CPU_CLK_MASK;
  141. if (cpu_clk) {
  142. cpu_rate = 480000000;
  143. } else if (!swconfig) {
  144. cpu_rate = 600000000;
  145. } else {
  146. u32 m = (c0 >> CPLL_MULT_RATIO_SHIFT) & CPLL_MULT_RATIO;
  147. u32 d = (c0 >> CPLL_DIV_RATIO_SHIFT) & CPLL_DIV_RATIO;
  148. cpu_rate = ((40 * (m + 24)) / mt7620_clk_divider[d]) * 1000000;
  149. }
  150. if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
  151. sys_rate = cpu_rate / 4;
  152. else
  153. sys_rate = cpu_rate / 3;
  154. ralink_clk_add("cpu", cpu_rate);
  155. ralink_clk_add("10000100.timer", 40000000);
  156. ralink_clk_add("10000500.uart", 40000000);
  157. ralink_clk_add("10000c00.uartlite", 40000000);
  158. }
  159. void __init ralink_of_remap(void)
  160. {
  161. rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
  162. rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
  163. if (!rt_sysc_membase || !rt_memc_membase)
  164. panic("Failed to remap core resources");
  165. }
  166. void prom_soc_init(struct ralink_soc_info *soc_info)
  167. {
  168. void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
  169. unsigned char *name = NULL;
  170. u32 n0;
  171. u32 n1;
  172. u32 rev;
  173. u32 cfg0;
  174. n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
  175. n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
  176. if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) {
  177. name = "MT7620N";
  178. soc_info->compatible = "ralink,mt7620n-soc";
  179. } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) {
  180. name = "MT7620A";
  181. soc_info->compatible = "ralink,mt7620a-soc";
  182. } else {
  183. panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
  184. }
  185. rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
  186. snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
  187. "Ralink %s ver:%u eco:%u",
  188. name,
  189. (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
  190. (rev & CHIP_REV_ECO_MASK));
  191. cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
  192. dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
  193. switch (dram_type) {
  194. case SYSCFG0_DRAM_TYPE_SDRAM:
  195. soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
  196. soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
  197. break;
  198. case SYSCFG0_DRAM_TYPE_DDR1:
  199. soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
  200. soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
  201. break;
  202. case SYSCFG0_DRAM_TYPE_DDR2:
  203. soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
  204. soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
  205. break;
  206. default:
  207. BUG();
  208. }
  209. soc_info->mem_base = MT7620_DRAM_BASE;
  210. }