irq.c 4.4 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify it
  3. * under the terms of the GNU General Public License version 2 as published
  4. * by the Free Software Foundation.
  5. *
  6. * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
  7. * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  8. */
  9. #include <linux/io.h>
  10. #include <linux/bitops.h>
  11. #include <linux/of_platform.h>
  12. #include <linux/of_address.h>
  13. #include <linux/of_irq.h>
  14. #include <linux/irqdomain.h>
  15. #include <linux/interrupt.h>
  16. #include <asm/irq_cpu.h>
  17. #include <asm/mipsregs.h>
  18. #include "common.h"
  19. /* INTC register offsets */
  20. #define INTC_REG_STATUS0 0x00
  21. #define INTC_REG_STATUS1 0x04
  22. #define INTC_REG_TYPE 0x20
  23. #define INTC_REG_RAW_STATUS 0x30
  24. #define INTC_REG_ENABLE 0x34
  25. #define INTC_REG_DISABLE 0x38
  26. #define INTC_INT_GLOBAL BIT(31)
  27. #define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)
  28. #define RALINK_CPU_IRQ_PCI (MIPS_CPU_IRQ_BASE + 4)
  29. #define RALINK_CPU_IRQ_FE (MIPS_CPU_IRQ_BASE + 5)
  30. #define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6)
  31. #define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7)
  32. /* we have a cascade of 8 irqs */
  33. #define RALINK_INTC_IRQ_BASE 8
  34. /* we have 32 SoC irqs */
  35. #define RALINK_INTC_IRQ_COUNT 32
  36. #define RALINK_INTC_IRQ_PERFC (RALINK_INTC_IRQ_BASE + 9)
  37. static void __iomem *rt_intc_membase;
  38. static inline void rt_intc_w32(u32 val, unsigned reg)
  39. {
  40. __raw_writel(val, rt_intc_membase + reg);
  41. }
  42. static inline u32 rt_intc_r32(unsigned reg)
  43. {
  44. return __raw_readl(rt_intc_membase + reg);
  45. }
  46. static void ralink_intc_irq_unmask(struct irq_data *d)
  47. {
  48. rt_intc_w32(BIT(d->hwirq), INTC_REG_ENABLE);
  49. }
  50. static void ralink_intc_irq_mask(struct irq_data *d)
  51. {
  52. rt_intc_w32(BIT(d->hwirq), INTC_REG_DISABLE);
  53. }
  54. static struct irq_chip ralink_intc_irq_chip = {
  55. .name = "INTC",
  56. .irq_unmask = ralink_intc_irq_unmask,
  57. .irq_mask = ralink_intc_irq_mask,
  58. .irq_mask_ack = ralink_intc_irq_mask,
  59. };
  60. unsigned int __cpuinit get_c0_compare_int(void)
  61. {
  62. return CP0_LEGACY_COMPARE_IRQ;
  63. }
  64. static void ralink_intc_irq_handler(unsigned int irq, struct irq_desc *desc)
  65. {
  66. u32 pending = rt_intc_r32(INTC_REG_STATUS0);
  67. if (pending) {
  68. struct irq_domain *domain = irq_get_handler_data(irq);
  69. generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
  70. } else {
  71. spurious_interrupt();
  72. }
  73. }
  74. asmlinkage void plat_irq_dispatch(void)
  75. {
  76. unsigned long pending;
  77. pending = read_c0_status() & read_c0_cause() & ST0_IM;
  78. if (pending & STATUSF_IP7)
  79. do_IRQ(RALINK_CPU_IRQ_COUNTER);
  80. else if (pending & STATUSF_IP5)
  81. do_IRQ(RALINK_CPU_IRQ_FE);
  82. else if (pending & STATUSF_IP6)
  83. do_IRQ(RALINK_CPU_IRQ_WIFI);
  84. else if (pending & STATUSF_IP4)
  85. do_IRQ(RALINK_CPU_IRQ_PCI);
  86. else if (pending & STATUSF_IP2)
  87. do_IRQ(RALINK_CPU_IRQ_INTC);
  88. else
  89. spurious_interrupt();
  90. }
  91. static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
  92. {
  93. irq_set_chip_and_handler(irq, &ralink_intc_irq_chip, handle_level_irq);
  94. return 0;
  95. }
  96. static const struct irq_domain_ops irq_domain_ops = {
  97. .xlate = irq_domain_xlate_onecell,
  98. .map = intc_map,
  99. };
  100. static int __init intc_of_init(struct device_node *node,
  101. struct device_node *parent)
  102. {
  103. struct resource res;
  104. struct irq_domain *domain;
  105. int irq;
  106. irq = irq_of_parse_and_map(node, 0);
  107. if (!irq)
  108. panic("Failed to get INTC IRQ");
  109. if (of_address_to_resource(node, 0, &res))
  110. panic("Failed to get intc memory range");
  111. if (request_mem_region(res.start, resource_size(&res),
  112. res.name) < 0)
  113. pr_err("Failed to request intc memory");
  114. rt_intc_membase = ioremap_nocache(res.start,
  115. resource_size(&res));
  116. if (!rt_intc_membase)
  117. panic("Failed to remap intc memory");
  118. /* disable all interrupts */
  119. rt_intc_w32(~0, INTC_REG_DISABLE);
  120. /* route all INTC interrupts to MIPS HW0 interrupt */
  121. rt_intc_w32(0, INTC_REG_TYPE);
  122. domain = irq_domain_add_legacy(node, RALINK_INTC_IRQ_COUNT,
  123. RALINK_INTC_IRQ_BASE, 0, &irq_domain_ops, NULL);
  124. if (!domain)
  125. panic("Failed to add irqdomain");
  126. rt_intc_w32(INTC_INT_GLOBAL, INTC_REG_ENABLE);
  127. irq_set_chained_handler(irq, ralink_intc_irq_handler);
  128. irq_set_handler_data(irq, domain);
  129. /* tell the kernel which irq is used for performance monitoring */
  130. cp0_perfcount_irq = irq_create_mapping(domain, 9);
  131. return 0;
  132. }
  133. static struct of_device_id __initdata of_irq_ids[] = {
  134. { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
  135. { .compatible = "ralink,rt2880-intc", .data = intc_of_init },
  136. {},
  137. };
  138. void __init arch_init_irq(void)
  139. {
  140. of_irq_init(of_irq_ids);
  141. }