inst.h 22 KB

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  1. /*
  2. * Format of an instruction in memory.
  3. *
  4. * This file is subject to the terms and conditions of the GNU General Public
  5. * License. See the file "COPYING" in the main directory of this archive
  6. * for more details.
  7. *
  8. * Copyright (C) 1996, 2000 by Ralf Baechle
  9. * Copyright (C) 2006 by Thiemo Seufer
  10. * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
  11. */
  12. #ifndef _UAPI_ASM_INST_H
  13. #define _UAPI_ASM_INST_H
  14. /*
  15. * Major opcodes; before MIPS IV cop1x was called cop3.
  16. */
  17. enum major_op {
  18. spec_op, bcond_op, j_op, jal_op,
  19. beq_op, bne_op, blez_op, bgtz_op,
  20. addi_op, addiu_op, slti_op, sltiu_op,
  21. andi_op, ori_op, xori_op, lui_op,
  22. cop0_op, cop1_op, cop2_op, cop1x_op,
  23. beql_op, bnel_op, blezl_op, bgtzl_op,
  24. daddi_op, daddiu_op, ldl_op, ldr_op,
  25. spec2_op, jalx_op, mdmx_op, spec3_op,
  26. lb_op, lh_op, lwl_op, lw_op,
  27. lbu_op, lhu_op, lwr_op, lwu_op,
  28. sb_op, sh_op, swl_op, sw_op,
  29. sdl_op, sdr_op, swr_op, cache_op,
  30. ll_op, lwc1_op, lwc2_op, pref_op,
  31. lld_op, ldc1_op, ldc2_op, ld_op,
  32. sc_op, swc1_op, swc2_op, major_3b_op,
  33. scd_op, sdc1_op, sdc2_op, sd_op
  34. };
  35. /*
  36. * func field of spec opcode.
  37. */
  38. enum spec_op {
  39. sll_op, movc_op, srl_op, sra_op,
  40. sllv_op, pmon_op, srlv_op, srav_op,
  41. jr_op, jalr_op, movz_op, movn_op,
  42. syscall_op, break_op, spim_op, sync_op,
  43. mfhi_op, mthi_op, mflo_op, mtlo_op,
  44. dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
  45. mult_op, multu_op, div_op, divu_op,
  46. dmult_op, dmultu_op, ddiv_op, ddivu_op,
  47. add_op, addu_op, sub_op, subu_op,
  48. and_op, or_op, xor_op, nor_op,
  49. spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
  50. dadd_op, daddu_op, dsub_op, dsubu_op,
  51. tge_op, tgeu_op, tlt_op, tltu_op,
  52. teq_op, spec5_unused_op, tne_op, spec6_unused_op,
  53. dsll_op, spec7_unused_op, dsrl_op, dsra_op,
  54. dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
  55. };
  56. /*
  57. * func field of spec2 opcode.
  58. */
  59. enum spec2_op {
  60. madd_op, maddu_op, mul_op, spec2_3_unused_op,
  61. msub_op, msubu_op, /* more unused ops */
  62. clz_op = 0x20, clo_op,
  63. dclz_op = 0x24, dclo_op,
  64. sdbpp_op = 0x3f
  65. };
  66. /*
  67. * func field of spec3 opcode.
  68. */
  69. enum spec3_op {
  70. ext_op, dextm_op, dextu_op, dext_op,
  71. ins_op, dinsm_op, dinsu_op, dins_op,
  72. lx_op = 0x0a,
  73. bshfl_op = 0x20,
  74. dbshfl_op = 0x24,
  75. rdhwr_op = 0x3b
  76. };
  77. /*
  78. * rt field of bcond opcodes.
  79. */
  80. enum rt_op {
  81. bltz_op, bgez_op, bltzl_op, bgezl_op,
  82. spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
  83. tgei_op, tgeiu_op, tlti_op, tltiu_op,
  84. teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
  85. bltzal_op, bgezal_op, bltzall_op, bgezall_op,
  86. rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
  87. rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
  88. bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
  89. };
  90. /*
  91. * rs field of cop opcodes.
  92. */
  93. enum cop_op {
  94. mfc_op = 0x00, dmfc_op = 0x01,
  95. cfc_op = 0x02, mtc_op = 0x04,
  96. dmtc_op = 0x05, ctc_op = 0x06,
  97. bc_op = 0x08, cop_op = 0x10,
  98. copm_op = 0x18
  99. };
  100. /*
  101. * rt field of cop.bc_op opcodes
  102. */
  103. enum bcop_op {
  104. bcf_op, bct_op, bcfl_op, bctl_op
  105. };
  106. /*
  107. * func field of cop0 coi opcodes.
  108. */
  109. enum cop0_coi_func {
  110. tlbr_op = 0x01, tlbwi_op = 0x02,
  111. tlbwr_op = 0x06, tlbp_op = 0x08,
  112. rfe_op = 0x10, eret_op = 0x18
  113. };
  114. /*
  115. * func field of cop0 com opcodes.
  116. */
  117. enum cop0_com_func {
  118. tlbr1_op = 0x01, tlbw_op = 0x02,
  119. tlbp1_op = 0x08, dctr_op = 0x09,
  120. dctw_op = 0x0a
  121. };
  122. /*
  123. * fmt field of cop1 opcodes.
  124. */
  125. enum cop1_fmt {
  126. s_fmt, d_fmt, e_fmt, q_fmt,
  127. w_fmt, l_fmt
  128. };
  129. /*
  130. * func field of cop1 instructions using d, s or w format.
  131. */
  132. enum cop1_sdw_func {
  133. fadd_op = 0x00, fsub_op = 0x01,
  134. fmul_op = 0x02, fdiv_op = 0x03,
  135. fsqrt_op = 0x04, fabs_op = 0x05,
  136. fmov_op = 0x06, fneg_op = 0x07,
  137. froundl_op = 0x08, ftruncl_op = 0x09,
  138. fceill_op = 0x0a, ffloorl_op = 0x0b,
  139. fround_op = 0x0c, ftrunc_op = 0x0d,
  140. fceil_op = 0x0e, ffloor_op = 0x0f,
  141. fmovc_op = 0x11, fmovz_op = 0x12,
  142. fmovn_op = 0x13, frecip_op = 0x15,
  143. frsqrt_op = 0x16, fcvts_op = 0x20,
  144. fcvtd_op = 0x21, fcvte_op = 0x22,
  145. fcvtw_op = 0x24, fcvtl_op = 0x25,
  146. fcmp_op = 0x30
  147. };
  148. /*
  149. * func field of cop1x opcodes (MIPS IV).
  150. */
  151. enum cop1x_func {
  152. lwxc1_op = 0x00, ldxc1_op = 0x01,
  153. pfetch_op = 0x07, swxc1_op = 0x08,
  154. sdxc1_op = 0x09, madd_s_op = 0x20,
  155. madd_d_op = 0x21, madd_e_op = 0x22,
  156. msub_s_op = 0x28, msub_d_op = 0x29,
  157. msub_e_op = 0x2a, nmadd_s_op = 0x30,
  158. nmadd_d_op = 0x31, nmadd_e_op = 0x32,
  159. nmsub_s_op = 0x38, nmsub_d_op = 0x39,
  160. nmsub_e_op = 0x3a
  161. };
  162. /*
  163. * func field for mad opcodes (MIPS IV).
  164. */
  165. enum mad_func {
  166. madd_fp_op = 0x08, msub_fp_op = 0x0a,
  167. nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e
  168. };
  169. /*
  170. * func field for special3 lx opcodes (Cavium Octeon).
  171. */
  172. enum lx_func {
  173. lwx_op = 0x00,
  174. lhx_op = 0x04,
  175. lbux_op = 0x06,
  176. ldx_op = 0x08,
  177. lwux_op = 0x10,
  178. lhux_op = 0x14,
  179. lbx_op = 0x16,
  180. };
  181. /*
  182. * (microMIPS) Major opcodes.
  183. */
  184. enum mm_major_op {
  185. mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op,
  186. mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op,
  187. mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
  188. mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
  189. mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
  190. mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op,
  191. mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
  192. mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
  193. mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
  194. mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op,
  195. mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op,
  196. mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
  197. mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op,
  198. mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op,
  199. mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op,
  200. mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,
  201. };
  202. /*
  203. * (microMIPS) POOL32I minor opcodes.
  204. */
  205. enum mm_32i_minor_op {
  206. mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op,
  207. mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
  208. mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op,
  209. mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op,
  210. mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op,
  211. mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op,
  212. mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op,
  213. mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op,
  214. mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op,
  215. };
  216. /*
  217. * (microMIPS) POOL32A minor opcodes.
  218. */
  219. enum mm_32a_minor_op {
  220. mm_sll32_op = 0x000,
  221. mm_ins_op = 0x00c,
  222. mm_ext_op = 0x02c,
  223. mm_pool32axf_op = 0x03c,
  224. mm_srl32_op = 0x040,
  225. mm_sra_op = 0x080,
  226. mm_rotr_op = 0x0c0,
  227. mm_lwxs_op = 0x118,
  228. mm_addu32_op = 0x150,
  229. mm_subu32_op = 0x1d0,
  230. mm_and_op = 0x250,
  231. mm_or32_op = 0x290,
  232. mm_xor32_op = 0x310,
  233. };
  234. /*
  235. * (microMIPS) POOL32B functions.
  236. */
  237. enum mm_32b_func {
  238. mm_lwc2_func = 0x0,
  239. mm_lwp_func = 0x1,
  240. mm_ldc2_func = 0x2,
  241. mm_ldp_func = 0x4,
  242. mm_lwm32_func = 0x5,
  243. mm_cache_func = 0x6,
  244. mm_ldm_func = 0x7,
  245. mm_swc2_func = 0x8,
  246. mm_swp_func = 0x9,
  247. mm_sdc2_func = 0xa,
  248. mm_sdp_func = 0xc,
  249. mm_swm32_func = 0xd,
  250. mm_sdm_func = 0xf,
  251. };
  252. /*
  253. * (microMIPS) POOL32C functions.
  254. */
  255. enum mm_32c_func {
  256. mm_pref_func = 0x2,
  257. mm_ll_func = 0x3,
  258. mm_swr_func = 0x9,
  259. mm_sc_func = 0xb,
  260. mm_lwu_func = 0xe,
  261. };
  262. /*
  263. * (microMIPS) POOL32AXF minor opcodes.
  264. */
  265. enum mm_32axf_minor_op {
  266. mm_mfc0_op = 0x003,
  267. mm_mtc0_op = 0x00b,
  268. mm_tlbp_op = 0x00d,
  269. mm_jalr_op = 0x03c,
  270. mm_tlbr_op = 0x04d,
  271. mm_jalrhb_op = 0x07c,
  272. mm_tlbwi_op = 0x08d,
  273. mm_tlbwr_op = 0x0cd,
  274. mm_jalrs_op = 0x13c,
  275. mm_jalrshb_op = 0x17c,
  276. mm_syscall_op = 0x22d,
  277. mm_eret_op = 0x3cd,
  278. };
  279. /*
  280. * (microMIPS) POOL32F minor opcodes.
  281. */
  282. enum mm_32f_minor_op {
  283. mm_32f_00_op = 0x00,
  284. mm_32f_01_op = 0x01,
  285. mm_32f_02_op = 0x02,
  286. mm_32f_10_op = 0x08,
  287. mm_32f_11_op = 0x09,
  288. mm_32f_12_op = 0x0a,
  289. mm_32f_20_op = 0x10,
  290. mm_32f_30_op = 0x18,
  291. mm_32f_40_op = 0x20,
  292. mm_32f_41_op = 0x21,
  293. mm_32f_42_op = 0x22,
  294. mm_32f_50_op = 0x28,
  295. mm_32f_51_op = 0x29,
  296. mm_32f_52_op = 0x2a,
  297. mm_32f_60_op = 0x30,
  298. mm_32f_70_op = 0x38,
  299. mm_32f_73_op = 0x3b,
  300. mm_32f_74_op = 0x3c,
  301. };
  302. /*
  303. * (microMIPS) POOL32F secondary minor opcodes.
  304. */
  305. enum mm_32f_10_minor_op {
  306. mm_lwxc1_op = 0x1,
  307. mm_swxc1_op,
  308. mm_ldxc1_op,
  309. mm_sdxc1_op,
  310. mm_luxc1_op,
  311. mm_suxc1_op,
  312. };
  313. enum mm_32f_func {
  314. mm_lwxc1_func = 0x048,
  315. mm_swxc1_func = 0x088,
  316. mm_ldxc1_func = 0x0c8,
  317. mm_sdxc1_func = 0x108,
  318. };
  319. /*
  320. * (microMIPS) POOL32F secondary minor opcodes.
  321. */
  322. enum mm_32f_40_minor_op {
  323. mm_fmovf_op,
  324. mm_fmovt_op,
  325. };
  326. /*
  327. * (microMIPS) POOL32F secondary minor opcodes.
  328. */
  329. enum mm_32f_60_minor_op {
  330. mm_fadd_op,
  331. mm_fsub_op,
  332. mm_fmul_op,
  333. mm_fdiv_op,
  334. };
  335. /*
  336. * (microMIPS) POOL32F secondary minor opcodes.
  337. */
  338. enum mm_32f_70_minor_op {
  339. mm_fmovn_op,
  340. mm_fmovz_op,
  341. };
  342. /*
  343. * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F.
  344. */
  345. enum mm_32f_73_minor_op {
  346. mm_fmov0_op = 0x01,
  347. mm_fcvtl_op = 0x04,
  348. mm_movf0_op = 0x05,
  349. mm_frsqrt_op = 0x08,
  350. mm_ffloorl_op = 0x0c,
  351. mm_fabs0_op = 0x0d,
  352. mm_fcvtw_op = 0x24,
  353. mm_movt0_op = 0x25,
  354. mm_fsqrt_op = 0x28,
  355. mm_ffloorw_op = 0x2c,
  356. mm_fneg0_op = 0x2d,
  357. mm_cfc1_op = 0x40,
  358. mm_frecip_op = 0x48,
  359. mm_fceill_op = 0x4c,
  360. mm_fcvtd0_op = 0x4d,
  361. mm_ctc1_op = 0x60,
  362. mm_fceilw_op = 0x6c,
  363. mm_fcvts0_op = 0x6d,
  364. mm_mfc1_op = 0x80,
  365. mm_fmov1_op = 0x81,
  366. mm_movf1_op = 0x85,
  367. mm_ftruncl_op = 0x8c,
  368. mm_fabs1_op = 0x8d,
  369. mm_mtc1_op = 0xa0,
  370. mm_movt1_op = 0xa5,
  371. mm_ftruncw_op = 0xac,
  372. mm_fneg1_op = 0xad,
  373. mm_froundl_op = 0xcc,
  374. mm_fcvtd1_op = 0xcd,
  375. mm_froundw_op = 0xec,
  376. mm_fcvts1_op = 0xed,
  377. };
  378. /*
  379. * (microMIPS) POOL16C minor opcodes.
  380. */
  381. enum mm_16c_minor_op {
  382. mm_lwm16_op = 0x04,
  383. mm_swm16_op = 0x05,
  384. mm_jr16_op = 0x18,
  385. mm_jrc_op = 0x1a,
  386. mm_jalr16_op = 0x1c,
  387. mm_jalrs16_op = 0x1e,
  388. };
  389. /*
  390. * (microMIPS) POOL16D minor opcodes.
  391. */
  392. enum mm_16d_minor_op {
  393. mm_addius5_func,
  394. mm_addiusp_func,
  395. };
  396. /*
  397. * (MIPS16e) opcodes.
  398. */
  399. enum MIPS16e_ops {
  400. MIPS16e_jal_op = 003,
  401. MIPS16e_ld_op = 007,
  402. MIPS16e_i8_op = 014,
  403. MIPS16e_sd_op = 017,
  404. MIPS16e_lb_op = 020,
  405. MIPS16e_lh_op = 021,
  406. MIPS16e_lwsp_op = 022,
  407. MIPS16e_lw_op = 023,
  408. MIPS16e_lbu_op = 024,
  409. MIPS16e_lhu_op = 025,
  410. MIPS16e_lwpc_op = 026,
  411. MIPS16e_lwu_op = 027,
  412. MIPS16e_sb_op = 030,
  413. MIPS16e_sh_op = 031,
  414. MIPS16e_swsp_op = 032,
  415. MIPS16e_sw_op = 033,
  416. MIPS16e_rr_op = 035,
  417. MIPS16e_extend_op = 036,
  418. MIPS16e_i64_op = 037,
  419. };
  420. enum MIPS16e_i64_func {
  421. MIPS16e_ldsp_func,
  422. MIPS16e_sdsp_func,
  423. MIPS16e_sdrasp_func,
  424. MIPS16e_dadjsp_func,
  425. MIPS16e_ldpc_func,
  426. };
  427. enum MIPS16e_rr_func {
  428. MIPS16e_jr_func,
  429. };
  430. enum MIPS6e_i8_func {
  431. MIPS16e_swrasp_func = 02,
  432. };
  433. /*
  434. * (microMIPS & MIPS16e) NOP instruction.
  435. */
  436. #define MM_NOP16 0x0c00
  437. /*
  438. * Damn ... bitfields depend from byteorder :-(
  439. */
  440. #ifdef __MIPSEB__
  441. #define BITFIELD_FIELD(field, more) \
  442. field; \
  443. more
  444. #elif defined(__MIPSEL__)
  445. #define BITFIELD_FIELD(field, more) \
  446. more \
  447. field;
  448. #else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
  449. #error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
  450. #endif
  451. struct j_format {
  452. BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
  453. BITFIELD_FIELD(unsigned int target : 26,
  454. ;))
  455. };
  456. struct i_format { /* signed immediate format */
  457. BITFIELD_FIELD(unsigned int opcode : 6,
  458. BITFIELD_FIELD(unsigned int rs : 5,
  459. BITFIELD_FIELD(unsigned int rt : 5,
  460. BITFIELD_FIELD(signed int simmediate : 16,
  461. ;))))
  462. };
  463. struct u_format { /* unsigned immediate format */
  464. BITFIELD_FIELD(unsigned int opcode : 6,
  465. BITFIELD_FIELD(unsigned int rs : 5,
  466. BITFIELD_FIELD(unsigned int rt : 5,
  467. BITFIELD_FIELD(unsigned int uimmediate : 16,
  468. ;))))
  469. };
  470. struct c_format { /* Cache (>= R6000) format */
  471. BITFIELD_FIELD(unsigned int opcode : 6,
  472. BITFIELD_FIELD(unsigned int rs : 5,
  473. BITFIELD_FIELD(unsigned int c_op : 3,
  474. BITFIELD_FIELD(unsigned int cache : 2,
  475. BITFIELD_FIELD(unsigned int simmediate : 16,
  476. ;)))))
  477. };
  478. struct r_format { /* Register format */
  479. BITFIELD_FIELD(unsigned int opcode : 6,
  480. BITFIELD_FIELD(unsigned int rs : 5,
  481. BITFIELD_FIELD(unsigned int rt : 5,
  482. BITFIELD_FIELD(unsigned int rd : 5,
  483. BITFIELD_FIELD(unsigned int re : 5,
  484. BITFIELD_FIELD(unsigned int func : 6,
  485. ;))))))
  486. };
  487. struct p_format { /* Performance counter format (R10000) */
  488. BITFIELD_FIELD(unsigned int opcode : 6,
  489. BITFIELD_FIELD(unsigned int rs : 5,
  490. BITFIELD_FIELD(unsigned int rt : 5,
  491. BITFIELD_FIELD(unsigned int rd : 5,
  492. BITFIELD_FIELD(unsigned int re : 5,
  493. BITFIELD_FIELD(unsigned int func : 6,
  494. ;))))))
  495. };
  496. struct f_format { /* FPU register format */
  497. BITFIELD_FIELD(unsigned int opcode : 6,
  498. BITFIELD_FIELD(unsigned int : 1,
  499. BITFIELD_FIELD(unsigned int fmt : 4,
  500. BITFIELD_FIELD(unsigned int rt : 5,
  501. BITFIELD_FIELD(unsigned int rd : 5,
  502. BITFIELD_FIELD(unsigned int re : 5,
  503. BITFIELD_FIELD(unsigned int func : 6,
  504. ;)))))))
  505. };
  506. struct ma_format { /* FPU multiply and add format (MIPS IV) */
  507. BITFIELD_FIELD(unsigned int opcode : 6,
  508. BITFIELD_FIELD(unsigned int fr : 5,
  509. BITFIELD_FIELD(unsigned int ft : 5,
  510. BITFIELD_FIELD(unsigned int fs : 5,
  511. BITFIELD_FIELD(unsigned int fd : 5,
  512. BITFIELD_FIELD(unsigned int func : 4,
  513. BITFIELD_FIELD(unsigned int fmt : 2,
  514. ;)))))))
  515. };
  516. struct b_format { /* BREAK and SYSCALL */
  517. BITFIELD_FIELD(unsigned int opcode : 6,
  518. BITFIELD_FIELD(unsigned int code : 20,
  519. BITFIELD_FIELD(unsigned int func : 6,
  520. ;)))
  521. };
  522. struct ps_format { /* MIPS-3D / paired single format */
  523. BITFIELD_FIELD(unsigned int opcode : 6,
  524. BITFIELD_FIELD(unsigned int rs : 5,
  525. BITFIELD_FIELD(unsigned int ft : 5,
  526. BITFIELD_FIELD(unsigned int fs : 5,
  527. BITFIELD_FIELD(unsigned int fd : 5,
  528. BITFIELD_FIELD(unsigned int func : 6,
  529. ;))))))
  530. };
  531. struct v_format { /* MDMX vector format */
  532. BITFIELD_FIELD(unsigned int opcode : 6,
  533. BITFIELD_FIELD(unsigned int sel : 4,
  534. BITFIELD_FIELD(unsigned int fmt : 1,
  535. BITFIELD_FIELD(unsigned int vt : 5,
  536. BITFIELD_FIELD(unsigned int vs : 5,
  537. BITFIELD_FIELD(unsigned int vd : 5,
  538. BITFIELD_FIELD(unsigned int func : 6,
  539. ;)))))))
  540. };
  541. /*
  542. * microMIPS instruction formats (32-bit length)
  543. *
  544. * NOTE:
  545. * Parenthesis denote whether the format is a microMIPS instruction or
  546. * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
  547. */
  548. struct fb_format { /* FPU branch format (MIPS32) */
  549. BITFIELD_FIELD(unsigned int opcode : 6,
  550. BITFIELD_FIELD(unsigned int bc : 5,
  551. BITFIELD_FIELD(unsigned int cc : 3,
  552. BITFIELD_FIELD(unsigned int flag : 2,
  553. BITFIELD_FIELD(signed int simmediate : 16,
  554. ;)))))
  555. };
  556. struct fp0_format { /* FPU multiply and add format (MIPS32) */
  557. BITFIELD_FIELD(unsigned int opcode : 6,
  558. BITFIELD_FIELD(unsigned int fmt : 5,
  559. BITFIELD_FIELD(unsigned int ft : 5,
  560. BITFIELD_FIELD(unsigned int fs : 5,
  561. BITFIELD_FIELD(unsigned int fd : 5,
  562. BITFIELD_FIELD(unsigned int func : 6,
  563. ;))))))
  564. };
  565. struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */
  566. BITFIELD_FIELD(unsigned int opcode : 6,
  567. BITFIELD_FIELD(unsigned int ft : 5,
  568. BITFIELD_FIELD(unsigned int fs : 5,
  569. BITFIELD_FIELD(unsigned int fd : 5,
  570. BITFIELD_FIELD(unsigned int fmt : 3,
  571. BITFIELD_FIELD(unsigned int op : 2,
  572. BITFIELD_FIELD(unsigned int func : 6,
  573. ;)))))))
  574. };
  575. struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */
  576. BITFIELD_FIELD(unsigned int opcode : 6,
  577. BITFIELD_FIELD(unsigned int op : 5,
  578. BITFIELD_FIELD(unsigned int rt : 5,
  579. BITFIELD_FIELD(unsigned int fs : 5,
  580. BITFIELD_FIELD(unsigned int fd : 5,
  581. BITFIELD_FIELD(unsigned int func : 6,
  582. ;))))))
  583. };
  584. struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */
  585. BITFIELD_FIELD(unsigned int opcode : 6,
  586. BITFIELD_FIELD(unsigned int rt : 5,
  587. BITFIELD_FIELD(unsigned int fs : 5,
  588. BITFIELD_FIELD(unsigned int fmt : 2,
  589. BITFIELD_FIELD(unsigned int op : 8,
  590. BITFIELD_FIELD(unsigned int func : 6,
  591. ;))))))
  592. };
  593. struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */
  594. BITFIELD_FIELD(unsigned int opcode : 6,
  595. BITFIELD_FIELD(unsigned int fd : 5,
  596. BITFIELD_FIELD(unsigned int fs : 5,
  597. BITFIELD_FIELD(unsigned int cc : 3,
  598. BITFIELD_FIELD(unsigned int zero : 2,
  599. BITFIELD_FIELD(unsigned int fmt : 2,
  600. BITFIELD_FIELD(unsigned int op : 3,
  601. BITFIELD_FIELD(unsigned int func : 6,
  602. ;))))))))
  603. };
  604. struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */
  605. BITFIELD_FIELD(unsigned int opcode : 6,
  606. BITFIELD_FIELD(unsigned int rt : 5,
  607. BITFIELD_FIELD(unsigned int fs : 5,
  608. BITFIELD_FIELD(unsigned int fmt : 3,
  609. BITFIELD_FIELD(unsigned int op : 7,
  610. BITFIELD_FIELD(unsigned int func : 6,
  611. ;))))))
  612. };
  613. struct mm_fp4_format { /* FPU c.cond format (microMIPS) */
  614. BITFIELD_FIELD(unsigned int opcode : 6,
  615. BITFIELD_FIELD(unsigned int rt : 5,
  616. BITFIELD_FIELD(unsigned int fs : 5,
  617. BITFIELD_FIELD(unsigned int cc : 3,
  618. BITFIELD_FIELD(unsigned int fmt : 3,
  619. BITFIELD_FIELD(unsigned int cond : 4,
  620. BITFIELD_FIELD(unsigned int func : 6,
  621. ;)))))))
  622. };
  623. struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */
  624. BITFIELD_FIELD(unsigned int opcode : 6,
  625. BITFIELD_FIELD(unsigned int index : 5,
  626. BITFIELD_FIELD(unsigned int base : 5,
  627. BITFIELD_FIELD(unsigned int fd : 5,
  628. BITFIELD_FIELD(unsigned int op : 5,
  629. BITFIELD_FIELD(unsigned int func : 6,
  630. ;))))))
  631. };
  632. struct fp6_format { /* FPU madd and msub format (MIPS IV) */
  633. BITFIELD_FIELD(unsigned int opcode : 6,
  634. BITFIELD_FIELD(unsigned int fr : 5,
  635. BITFIELD_FIELD(unsigned int ft : 5,
  636. BITFIELD_FIELD(unsigned int fs : 5,
  637. BITFIELD_FIELD(unsigned int fd : 5,
  638. BITFIELD_FIELD(unsigned int func : 6,
  639. ;))))))
  640. };
  641. struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */
  642. BITFIELD_FIELD(unsigned int opcode : 6,
  643. BITFIELD_FIELD(unsigned int ft : 5,
  644. BITFIELD_FIELD(unsigned int fs : 5,
  645. BITFIELD_FIELD(unsigned int fd : 5,
  646. BITFIELD_FIELD(unsigned int fr : 5,
  647. BITFIELD_FIELD(unsigned int func : 6,
  648. ;))))))
  649. };
  650. struct mm_i_format { /* Immediate format (microMIPS) */
  651. BITFIELD_FIELD(unsigned int opcode : 6,
  652. BITFIELD_FIELD(unsigned int rt : 5,
  653. BITFIELD_FIELD(unsigned int rs : 5,
  654. BITFIELD_FIELD(signed int simmediate : 16,
  655. ;))))
  656. };
  657. struct mm_m_format { /* Multi-word load/store format (microMIPS) */
  658. BITFIELD_FIELD(unsigned int opcode : 6,
  659. BITFIELD_FIELD(unsigned int rd : 5,
  660. BITFIELD_FIELD(unsigned int base : 5,
  661. BITFIELD_FIELD(unsigned int func : 4,
  662. BITFIELD_FIELD(signed int simmediate : 12,
  663. ;)))))
  664. };
  665. struct mm_x_format { /* Scaled indexed load format (microMIPS) */
  666. BITFIELD_FIELD(unsigned int opcode : 6,
  667. BITFIELD_FIELD(unsigned int index : 5,
  668. BITFIELD_FIELD(unsigned int base : 5,
  669. BITFIELD_FIELD(unsigned int rd : 5,
  670. BITFIELD_FIELD(unsigned int func : 11,
  671. ;)))))
  672. };
  673. /*
  674. * microMIPS instruction formats (16-bit length)
  675. */
  676. struct mm_b0_format { /* Unconditional branch format (microMIPS) */
  677. BITFIELD_FIELD(unsigned int opcode : 6,
  678. BITFIELD_FIELD(signed int simmediate : 10,
  679. BITFIELD_FIELD(unsigned int : 16, /* Ignored */
  680. ;)))
  681. };
  682. struct mm_b1_format { /* Conditional branch format (microMIPS) */
  683. BITFIELD_FIELD(unsigned int opcode : 6,
  684. BITFIELD_FIELD(unsigned int rs : 3,
  685. BITFIELD_FIELD(signed int simmediate : 7,
  686. BITFIELD_FIELD(unsigned int : 16, /* Ignored */
  687. ;))))
  688. };
  689. struct mm16_m_format { /* Multi-word load/store format */
  690. BITFIELD_FIELD(unsigned int opcode : 6,
  691. BITFIELD_FIELD(unsigned int func : 4,
  692. BITFIELD_FIELD(unsigned int rlist : 2,
  693. BITFIELD_FIELD(unsigned int imm : 4,
  694. BITFIELD_FIELD(unsigned int : 16, /* Ignored */
  695. ;)))))
  696. };
  697. struct mm16_rb_format { /* Signed immediate format */
  698. BITFIELD_FIELD(unsigned int opcode : 6,
  699. BITFIELD_FIELD(unsigned int rt : 3,
  700. BITFIELD_FIELD(unsigned int base : 3,
  701. BITFIELD_FIELD(signed int simmediate : 4,
  702. BITFIELD_FIELD(unsigned int : 16, /* Ignored */
  703. ;)))))
  704. };
  705. struct mm16_r3_format { /* Load from global pointer format */
  706. BITFIELD_FIELD(unsigned int opcode : 6,
  707. BITFIELD_FIELD(unsigned int rt : 3,
  708. BITFIELD_FIELD(signed int simmediate : 7,
  709. BITFIELD_FIELD(unsigned int : 16, /* Ignored */
  710. ;))))
  711. };
  712. struct mm16_r5_format { /* Load/store from stack pointer format */
  713. BITFIELD_FIELD(unsigned int opcode : 6,
  714. BITFIELD_FIELD(unsigned int rt : 5,
  715. BITFIELD_FIELD(signed int simmediate : 5,
  716. BITFIELD_FIELD(unsigned int : 16, /* Ignored */
  717. ;))))
  718. };
  719. /*
  720. * MIPS16e instruction formats (16-bit length)
  721. */
  722. struct m16e_rr {
  723. BITFIELD_FIELD(unsigned int opcode : 5,
  724. BITFIELD_FIELD(unsigned int rx : 3,
  725. BITFIELD_FIELD(unsigned int nd : 1,
  726. BITFIELD_FIELD(unsigned int l : 1,
  727. BITFIELD_FIELD(unsigned int ra : 1,
  728. BITFIELD_FIELD(unsigned int func : 5,
  729. ;))))))
  730. };
  731. struct m16e_jal {
  732. BITFIELD_FIELD(unsigned int opcode : 5,
  733. BITFIELD_FIELD(unsigned int x : 1,
  734. BITFIELD_FIELD(unsigned int imm20_16 : 5,
  735. BITFIELD_FIELD(signed int imm25_21 : 5,
  736. ;))))
  737. };
  738. struct m16e_i64 {
  739. BITFIELD_FIELD(unsigned int opcode : 5,
  740. BITFIELD_FIELD(unsigned int func : 3,
  741. BITFIELD_FIELD(unsigned int imm : 8,
  742. ;)))
  743. };
  744. struct m16e_ri64 {
  745. BITFIELD_FIELD(unsigned int opcode : 5,
  746. BITFIELD_FIELD(unsigned int func : 3,
  747. BITFIELD_FIELD(unsigned int ry : 3,
  748. BITFIELD_FIELD(unsigned int imm : 5,
  749. ;))))
  750. };
  751. struct m16e_ri {
  752. BITFIELD_FIELD(unsigned int opcode : 5,
  753. BITFIELD_FIELD(unsigned int rx : 3,
  754. BITFIELD_FIELD(unsigned int imm : 8,
  755. ;)))
  756. };
  757. struct m16e_rri {
  758. BITFIELD_FIELD(unsigned int opcode : 5,
  759. BITFIELD_FIELD(unsigned int rx : 3,
  760. BITFIELD_FIELD(unsigned int ry : 3,
  761. BITFIELD_FIELD(unsigned int imm : 5,
  762. ;))))
  763. };
  764. struct m16e_i8 {
  765. BITFIELD_FIELD(unsigned int opcode : 5,
  766. BITFIELD_FIELD(unsigned int func : 3,
  767. BITFIELD_FIELD(unsigned int imm : 8,
  768. ;)))
  769. };
  770. union mips_instruction {
  771. unsigned int word;
  772. unsigned short halfword[2];
  773. unsigned char byte[4];
  774. struct j_format j_format;
  775. struct i_format i_format;
  776. struct u_format u_format;
  777. struct c_format c_format;
  778. struct r_format r_format;
  779. struct p_format p_format;
  780. struct f_format f_format;
  781. struct ma_format ma_format;
  782. struct b_format b_format;
  783. struct ps_format ps_format;
  784. struct v_format v_format;
  785. struct fb_format fb_format;
  786. struct fp0_format fp0_format;
  787. struct mm_fp0_format mm_fp0_format;
  788. struct fp1_format fp1_format;
  789. struct mm_fp1_format mm_fp1_format;
  790. struct mm_fp2_format mm_fp2_format;
  791. struct mm_fp3_format mm_fp3_format;
  792. struct mm_fp4_format mm_fp4_format;
  793. struct mm_fp5_format mm_fp5_format;
  794. struct fp6_format fp6_format;
  795. struct mm_fp6_format mm_fp6_format;
  796. struct mm_i_format mm_i_format;
  797. struct mm_m_format mm_m_format;
  798. struct mm_x_format mm_x_format;
  799. struct mm_b0_format mm_b0_format;
  800. struct mm_b1_format mm_b1_format;
  801. struct mm16_m_format mm16_m_format ;
  802. struct mm16_rb_format mm16_rb_format;
  803. struct mm16_r3_format mm16_r3_format;
  804. struct mm16_r5_format mm16_r5_format;
  805. };
  806. union mips16e_instruction {
  807. unsigned int full : 16;
  808. struct m16e_rr rr;
  809. struct m16e_jal jal;
  810. struct m16e_i64 i64;
  811. struct m16e_ri64 ri64;
  812. struct m16e_ri ri;
  813. struct m16e_rri rri;
  814. struct m16e_i8 i8;
  815. };
  816. #endif /* _UAPI_ASM_INST_H */