bcm63xx_regs.h 51 KB

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  1. #ifndef BCM63XX_REGS_H_
  2. #define BCM63XX_REGS_H_
  3. /*************************************************************************
  4. * _REG relative to RSET_PERF
  5. *************************************************************************/
  6. /* Chip Identifier / Revision register */
  7. #define PERF_REV_REG 0x0
  8. #define REV_CHIPID_SHIFT 16
  9. #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
  10. #define REV_REVID_SHIFT 0
  11. #define REV_REVID_MASK (0xff << REV_REVID_SHIFT)
  12. /* Clock Control register */
  13. #define PERF_CKCTL_REG 0x4
  14. #define CKCTL_6328_PHYMIPS_EN (1 << 0)
  15. #define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
  16. #define CKCTL_6328_ADSL_AFE_EN (1 << 2)
  17. #define CKCTL_6328_ADSL_EN (1 << 3)
  18. #define CKCTL_6328_MIPS_EN (1 << 4)
  19. #define CKCTL_6328_SAR_EN (1 << 5)
  20. #define CKCTL_6328_PCM_EN (1 << 6)
  21. #define CKCTL_6328_USBD_EN (1 << 7)
  22. #define CKCTL_6328_USBH_EN (1 << 8)
  23. #define CKCTL_6328_HSSPI_EN (1 << 9)
  24. #define CKCTL_6328_PCIE_EN (1 << 10)
  25. #define CKCTL_6328_ROBOSW_EN (1 << 11)
  26. #define CKCTL_6328_ALL_SAFE_EN (CKCTL_6328_PHYMIPS_EN | \
  27. CKCTL_6328_ADSL_QPROC_EN | \
  28. CKCTL_6328_ADSL_AFE_EN | \
  29. CKCTL_6328_ADSL_EN | \
  30. CKCTL_6328_SAR_EN | \
  31. CKCTL_6328_PCM_EN | \
  32. CKCTL_6328_USBD_EN | \
  33. CKCTL_6328_USBH_EN | \
  34. CKCTL_6328_ROBOSW_EN | \
  35. CKCTL_6328_PCIE_EN)
  36. #define CKCTL_6338_ADSLPHY_EN (1 << 0)
  37. #define CKCTL_6338_MPI_EN (1 << 1)
  38. #define CKCTL_6338_DRAM_EN (1 << 2)
  39. #define CKCTL_6338_ENET_EN (1 << 4)
  40. #define CKCTL_6338_USBS_EN (1 << 4)
  41. #define CKCTL_6338_SAR_EN (1 << 5)
  42. #define CKCTL_6338_SPI_EN (1 << 9)
  43. #define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ADSLPHY_EN | \
  44. CKCTL_6338_MPI_EN | \
  45. CKCTL_6338_ENET_EN | \
  46. CKCTL_6338_SAR_EN | \
  47. CKCTL_6338_SPI_EN)
  48. /* BCM6345 clock bits are shifted by 16 on the left, because of the test
  49. * control register which is 16-bits wide. That way we do not have any
  50. * specific BCM6345 code for handling clocks, and writing 0 to the test
  51. * control register is fine.
  52. */
  53. #define CKCTL_6345_CPU_EN (1 << 16)
  54. #define CKCTL_6345_BUS_EN (1 << 17)
  55. #define CKCTL_6345_EBI_EN (1 << 18)
  56. #define CKCTL_6345_UART_EN (1 << 19)
  57. #define CKCTL_6345_ADSLPHY_EN (1 << 20)
  58. #define CKCTL_6345_ENET_EN (1 << 23)
  59. #define CKCTL_6345_USBH_EN (1 << 24)
  60. #define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \
  61. CKCTL_6345_USBH_EN | \
  62. CKCTL_6345_ADSLPHY_EN)
  63. #define CKCTL_6348_ADSLPHY_EN (1 << 0)
  64. #define CKCTL_6348_MPI_EN (1 << 1)
  65. #define CKCTL_6348_SDRAM_EN (1 << 2)
  66. #define CKCTL_6348_M2M_EN (1 << 3)
  67. #define CKCTL_6348_ENET_EN (1 << 4)
  68. #define CKCTL_6348_SAR_EN (1 << 5)
  69. #define CKCTL_6348_USBS_EN (1 << 6)
  70. #define CKCTL_6348_USBH_EN (1 << 8)
  71. #define CKCTL_6348_SPI_EN (1 << 9)
  72. #define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \
  73. CKCTL_6348_M2M_EN | \
  74. CKCTL_6348_ENET_EN | \
  75. CKCTL_6348_SAR_EN | \
  76. CKCTL_6348_USBS_EN | \
  77. CKCTL_6348_USBH_EN | \
  78. CKCTL_6348_SPI_EN)
  79. #define CKCTL_6358_ENET_EN (1 << 4)
  80. #define CKCTL_6358_ADSLPHY_EN (1 << 5)
  81. #define CKCTL_6358_PCM_EN (1 << 8)
  82. #define CKCTL_6358_SPI_EN (1 << 9)
  83. #define CKCTL_6358_USBS_EN (1 << 10)
  84. #define CKCTL_6358_SAR_EN (1 << 11)
  85. #define CKCTL_6358_EMUSB_EN (1 << 17)
  86. #define CKCTL_6358_ENET0_EN (1 << 18)
  87. #define CKCTL_6358_ENET1_EN (1 << 19)
  88. #define CKCTL_6358_USBSU_EN (1 << 20)
  89. #define CKCTL_6358_EPHY_EN (1 << 21)
  90. #define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \
  91. CKCTL_6358_ADSLPHY_EN | \
  92. CKCTL_6358_PCM_EN | \
  93. CKCTL_6358_SPI_EN | \
  94. CKCTL_6358_USBS_EN | \
  95. CKCTL_6358_SAR_EN | \
  96. CKCTL_6358_EMUSB_EN | \
  97. CKCTL_6358_ENET0_EN | \
  98. CKCTL_6358_ENET1_EN | \
  99. CKCTL_6358_USBSU_EN | \
  100. CKCTL_6358_EPHY_EN)
  101. #define CKCTL_6362_ADSL_QPROC_EN (1 << 1)
  102. #define CKCTL_6362_ADSL_AFE_EN (1 << 2)
  103. #define CKCTL_6362_ADSL_EN (1 << 3)
  104. #define CKCTL_6362_MIPS_EN (1 << 4)
  105. #define CKCTL_6362_WLAN_OCP_EN (1 << 5)
  106. #define CKCTL_6362_SWPKT_USB_EN (1 << 7)
  107. #define CKCTL_6362_SWPKT_SAR_EN (1 << 8)
  108. #define CKCTL_6362_SAR_EN (1 << 9)
  109. #define CKCTL_6362_ROBOSW_EN (1 << 10)
  110. #define CKCTL_6362_PCM_EN (1 << 11)
  111. #define CKCTL_6362_USBD_EN (1 << 12)
  112. #define CKCTL_6362_USBH_EN (1 << 13)
  113. #define CKCTL_6362_IPSEC_EN (1 << 14)
  114. #define CKCTL_6362_SPI_EN (1 << 15)
  115. #define CKCTL_6362_HSSPI_EN (1 << 16)
  116. #define CKCTL_6362_PCIE_EN (1 << 17)
  117. #define CKCTL_6362_FAP_EN (1 << 18)
  118. #define CKCTL_6362_PHYMIPS_EN (1 << 19)
  119. #define CKCTL_6362_NAND_EN (1 << 20)
  120. #define CKCTL_6362_ALL_SAFE_EN (CKCTL_6362_PHYMIPS_EN | \
  121. CKCTL_6362_ADSL_QPROC_EN | \
  122. CKCTL_6362_ADSL_AFE_EN | \
  123. CKCTL_6362_ADSL_EN | \
  124. CKCTL_6362_SAR_EN | \
  125. CKCTL_6362_PCM_EN | \
  126. CKCTL_6362_IPSEC_EN | \
  127. CKCTL_6362_USBD_EN | \
  128. CKCTL_6362_USBH_EN | \
  129. CKCTL_6362_ROBOSW_EN | \
  130. CKCTL_6362_PCIE_EN)
  131. #define CKCTL_6368_VDSL_QPROC_EN (1 << 2)
  132. #define CKCTL_6368_VDSL_AFE_EN (1 << 3)
  133. #define CKCTL_6368_VDSL_BONDING_EN (1 << 4)
  134. #define CKCTL_6368_VDSL_EN (1 << 5)
  135. #define CKCTL_6368_PHYMIPS_EN (1 << 6)
  136. #define CKCTL_6368_SWPKT_USB_EN (1 << 7)
  137. #define CKCTL_6368_SWPKT_SAR_EN (1 << 8)
  138. #define CKCTL_6368_SPI_EN (1 << 9)
  139. #define CKCTL_6368_USBD_EN (1 << 10)
  140. #define CKCTL_6368_SAR_EN (1 << 11)
  141. #define CKCTL_6368_ROBOSW_EN (1 << 12)
  142. #define CKCTL_6368_UTOPIA_EN (1 << 13)
  143. #define CKCTL_6368_PCM_EN (1 << 14)
  144. #define CKCTL_6368_USBH_EN (1 << 15)
  145. #define CKCTL_6368_DISABLE_GLESS_EN (1 << 16)
  146. #define CKCTL_6368_NAND_EN (1 << 17)
  147. #define CKCTL_6368_IPSEC_EN (1 << 18)
  148. #define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \
  149. CKCTL_6368_SWPKT_SAR_EN | \
  150. CKCTL_6368_SPI_EN | \
  151. CKCTL_6368_USBD_EN | \
  152. CKCTL_6368_SAR_EN | \
  153. CKCTL_6368_ROBOSW_EN | \
  154. CKCTL_6368_UTOPIA_EN | \
  155. CKCTL_6368_PCM_EN | \
  156. CKCTL_6368_USBH_EN | \
  157. CKCTL_6368_DISABLE_GLESS_EN | \
  158. CKCTL_6368_NAND_EN | \
  159. CKCTL_6368_IPSEC_EN)
  160. /* System PLL Control register */
  161. #define PERF_SYS_PLL_CTL_REG 0x8
  162. #define SYS_PLL_SOFT_RESET 0x1
  163. /* Interrupt Mask register */
  164. #define PERF_IRQMASK_6328_REG 0x20
  165. #define PERF_IRQMASK_6338_REG 0xc
  166. #define PERF_IRQMASK_6345_REG 0xc
  167. #define PERF_IRQMASK_6348_REG 0xc
  168. #define PERF_IRQMASK_6358_REG 0xc
  169. #define PERF_IRQMASK_6362_REG 0x20
  170. #define PERF_IRQMASK_6368_REG 0x20
  171. /* Interrupt Status register */
  172. #define PERF_IRQSTAT_6328_REG 0x28
  173. #define PERF_IRQSTAT_6338_REG 0x10
  174. #define PERF_IRQSTAT_6345_REG 0x10
  175. #define PERF_IRQSTAT_6348_REG 0x10
  176. #define PERF_IRQSTAT_6358_REG 0x10
  177. #define PERF_IRQSTAT_6362_REG 0x28
  178. #define PERF_IRQSTAT_6368_REG 0x28
  179. /* External Interrupt Configuration register */
  180. #define PERF_EXTIRQ_CFG_REG_6328 0x18
  181. #define PERF_EXTIRQ_CFG_REG_6338 0x14
  182. #define PERF_EXTIRQ_CFG_REG_6345 0x14
  183. #define PERF_EXTIRQ_CFG_REG_6348 0x14
  184. #define PERF_EXTIRQ_CFG_REG_6358 0x14
  185. #define PERF_EXTIRQ_CFG_REG_6362 0x18
  186. #define PERF_EXTIRQ_CFG_REG_6368 0x18
  187. #define PERF_EXTIRQ_CFG_REG2_6368 0x1c
  188. /* for 6348 only */
  189. #define EXTIRQ_CFG_SENSE_6348(x) (1 << (x))
  190. #define EXTIRQ_CFG_STAT_6348(x) (1 << (x + 5))
  191. #define EXTIRQ_CFG_CLEAR_6348(x) (1 << (x + 10))
  192. #define EXTIRQ_CFG_MASK_6348(x) (1 << (x + 15))
  193. #define EXTIRQ_CFG_BOTHEDGE_6348(x) (1 << (x + 20))
  194. #define EXTIRQ_CFG_LEVELSENSE_6348(x) (1 << (x + 25))
  195. #define EXTIRQ_CFG_CLEAR_ALL_6348 (0xf << 10)
  196. #define EXTIRQ_CFG_MASK_ALL_6348 (0xf << 15)
  197. /* for all others */
  198. #define EXTIRQ_CFG_SENSE(x) (1 << (x))
  199. #define EXTIRQ_CFG_STAT(x) (1 << (x + 4))
  200. #define EXTIRQ_CFG_CLEAR(x) (1 << (x + 8))
  201. #define EXTIRQ_CFG_MASK(x) (1 << (x + 12))
  202. #define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 16))
  203. #define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 20))
  204. #define EXTIRQ_CFG_CLEAR_ALL (0xf << 8)
  205. #define EXTIRQ_CFG_MASK_ALL (0xf << 12)
  206. /* Soft Reset register */
  207. #define PERF_SOFTRESET_REG 0x28
  208. #define PERF_SOFTRESET_6328_REG 0x10
  209. #define PERF_SOFTRESET_6358_REG 0x34
  210. #define PERF_SOFTRESET_6362_REG 0x10
  211. #define PERF_SOFTRESET_6368_REG 0x10
  212. #define SOFTRESET_6328_SPI_MASK (1 << 0)
  213. #define SOFTRESET_6328_EPHY_MASK (1 << 1)
  214. #define SOFTRESET_6328_SAR_MASK (1 << 2)
  215. #define SOFTRESET_6328_ENETSW_MASK (1 << 3)
  216. #define SOFTRESET_6328_USBS_MASK (1 << 4)
  217. #define SOFTRESET_6328_USBH_MASK (1 << 5)
  218. #define SOFTRESET_6328_PCM_MASK (1 << 6)
  219. #define SOFTRESET_6328_PCIE_CORE_MASK (1 << 7)
  220. #define SOFTRESET_6328_PCIE_MASK (1 << 8)
  221. #define SOFTRESET_6328_PCIE_EXT_MASK (1 << 9)
  222. #define SOFTRESET_6328_PCIE_HARD_MASK (1 << 10)
  223. #define SOFTRESET_6338_SPI_MASK (1 << 0)
  224. #define SOFTRESET_6338_ENET_MASK (1 << 2)
  225. #define SOFTRESET_6338_USBH_MASK (1 << 3)
  226. #define SOFTRESET_6338_USBS_MASK (1 << 4)
  227. #define SOFTRESET_6338_ADSL_MASK (1 << 5)
  228. #define SOFTRESET_6338_DMAMEM_MASK (1 << 6)
  229. #define SOFTRESET_6338_SAR_MASK (1 << 7)
  230. #define SOFTRESET_6338_ACLC_MASK (1 << 8)
  231. #define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10)
  232. #define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \
  233. SOFTRESET_6338_ENET_MASK | \
  234. SOFTRESET_6338_USBH_MASK | \
  235. SOFTRESET_6338_USBS_MASK | \
  236. SOFTRESET_6338_ADSL_MASK | \
  237. SOFTRESET_6338_DMAMEM_MASK | \
  238. SOFTRESET_6338_SAR_MASK | \
  239. SOFTRESET_6338_ACLC_MASK | \
  240. SOFTRESET_6338_ADSLMIPSPLL_MASK)
  241. #define SOFTRESET_6348_SPI_MASK (1 << 0)
  242. #define SOFTRESET_6348_ENET_MASK (1 << 2)
  243. #define SOFTRESET_6348_USBH_MASK (1 << 3)
  244. #define SOFTRESET_6348_USBS_MASK (1 << 4)
  245. #define SOFTRESET_6348_ADSL_MASK (1 << 5)
  246. #define SOFTRESET_6348_DMAMEM_MASK (1 << 6)
  247. #define SOFTRESET_6348_SAR_MASK (1 << 7)
  248. #define SOFTRESET_6348_ACLC_MASK (1 << 8)
  249. #define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10)
  250. #define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \
  251. SOFTRESET_6348_ENET_MASK | \
  252. SOFTRESET_6348_USBH_MASK | \
  253. SOFTRESET_6348_USBS_MASK | \
  254. SOFTRESET_6348_ADSL_MASK | \
  255. SOFTRESET_6348_DMAMEM_MASK | \
  256. SOFTRESET_6348_SAR_MASK | \
  257. SOFTRESET_6348_ACLC_MASK | \
  258. SOFTRESET_6348_ADSLMIPSPLL_MASK)
  259. #define SOFTRESET_6358_SPI_MASK (1 << 0)
  260. #define SOFTRESET_6358_ENET_MASK (1 << 2)
  261. #define SOFTRESET_6358_MPI_MASK (1 << 3)
  262. #define SOFTRESET_6358_EPHY_MASK (1 << 6)
  263. #define SOFTRESET_6358_SAR_MASK (1 << 7)
  264. #define SOFTRESET_6358_USBH_MASK (1 << 12)
  265. #define SOFTRESET_6358_PCM_MASK (1 << 13)
  266. #define SOFTRESET_6358_ADSL_MASK (1 << 14)
  267. #define SOFTRESET_6362_SPI_MASK (1 << 0)
  268. #define SOFTRESET_6362_IPSEC_MASK (1 << 1)
  269. #define SOFTRESET_6362_EPHY_MASK (1 << 2)
  270. #define SOFTRESET_6362_SAR_MASK (1 << 3)
  271. #define SOFTRESET_6362_ENETSW_MASK (1 << 4)
  272. #define SOFTRESET_6362_USBS_MASK (1 << 5)
  273. #define SOFTRESET_6362_USBH_MASK (1 << 6)
  274. #define SOFTRESET_6362_PCM_MASK (1 << 7)
  275. #define SOFTRESET_6362_PCIE_CORE_MASK (1 << 8)
  276. #define SOFTRESET_6362_PCIE_MASK (1 << 9)
  277. #define SOFTRESET_6362_PCIE_EXT_MASK (1 << 10)
  278. #define SOFTRESET_6362_WLAN_SHIM_MASK (1 << 11)
  279. #define SOFTRESET_6362_DDR_PHY_MASK (1 << 12)
  280. #define SOFTRESET_6362_FAP_MASK (1 << 13)
  281. #define SOFTRESET_6362_WLAN_UBUS_MASK (1 << 14)
  282. #define SOFTRESET_6368_SPI_MASK (1 << 0)
  283. #define SOFTRESET_6368_MPI_MASK (1 << 3)
  284. #define SOFTRESET_6368_EPHY_MASK (1 << 6)
  285. #define SOFTRESET_6368_SAR_MASK (1 << 7)
  286. #define SOFTRESET_6368_ENETSW_MASK (1 << 10)
  287. #define SOFTRESET_6368_USBS_MASK (1 << 11)
  288. #define SOFTRESET_6368_USBH_MASK (1 << 12)
  289. #define SOFTRESET_6368_PCM_MASK (1 << 13)
  290. /* MIPS PLL control register */
  291. #define PERF_MIPSPLLCTL_REG 0x34
  292. #define MIPSPLLCTL_N1_SHIFT 20
  293. #define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT)
  294. #define MIPSPLLCTL_N2_SHIFT 15
  295. #define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT)
  296. #define MIPSPLLCTL_M1REF_SHIFT 12
  297. #define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT)
  298. #define MIPSPLLCTL_M2REF_SHIFT 9
  299. #define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT)
  300. #define MIPSPLLCTL_M1CPU_SHIFT 6
  301. #define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT)
  302. #define MIPSPLLCTL_M1BUS_SHIFT 3
  303. #define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT)
  304. #define MIPSPLLCTL_M2BUS_SHIFT 0
  305. #define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT)
  306. /* ADSL PHY PLL Control register */
  307. #define PERF_ADSLPLLCTL_REG 0x38
  308. #define ADSLPLLCTL_N1_SHIFT 20
  309. #define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT)
  310. #define ADSLPLLCTL_N2_SHIFT 15
  311. #define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT)
  312. #define ADSLPLLCTL_M1REF_SHIFT 12
  313. #define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT)
  314. #define ADSLPLLCTL_M2REF_SHIFT 9
  315. #define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT)
  316. #define ADSLPLLCTL_M1CPU_SHIFT 6
  317. #define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT)
  318. #define ADSLPLLCTL_M1BUS_SHIFT 3
  319. #define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT)
  320. #define ADSLPLLCTL_M2BUS_SHIFT 0
  321. #define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT)
  322. #define ADSLPLLCTL_VAL(n1, n2, m1ref, m2ref, m1cpu, m1bus, m2bus) \
  323. (((n1) << ADSLPLLCTL_N1_SHIFT) | \
  324. ((n2) << ADSLPLLCTL_N2_SHIFT) | \
  325. ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \
  326. ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \
  327. ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \
  328. ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \
  329. ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT))
  330. /*************************************************************************
  331. * _REG relative to RSET_TIMER
  332. *************************************************************************/
  333. #define BCM63XX_TIMER_COUNT 4
  334. #define TIMER_T0_ID 0
  335. #define TIMER_T1_ID 1
  336. #define TIMER_T2_ID 2
  337. #define TIMER_WDT_ID 3
  338. /* Timer irqstat register */
  339. #define TIMER_IRQSTAT_REG 0
  340. #define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x))
  341. #define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0)
  342. #define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1)
  343. #define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2)
  344. #define TIMER_IRQSTAT_WDT_CAUSE (1 << 3)
  345. #define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8))
  346. #define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8)
  347. #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9)
  348. #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10)
  349. /* Timer control register */
  350. #define TIMER_CTLx_REG(x) (0x4 + (x * 4))
  351. #define TIMER_CTL0_REG 0x4
  352. #define TIMER_CTL1_REG 0x8
  353. #define TIMER_CTL2_REG 0xC
  354. #define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff)
  355. #define TIMER_CTL_MONOTONIC_MASK (1 << 30)
  356. #define TIMER_CTL_ENABLE_MASK (1 << 31)
  357. /*************************************************************************
  358. * _REG relative to RSET_WDT
  359. *************************************************************************/
  360. /* Watchdog default count register */
  361. #define WDT_DEFVAL_REG 0x0
  362. /* Watchdog control register */
  363. #define WDT_CTL_REG 0x4
  364. /* Watchdog control register constants */
  365. #define WDT_START_1 (0xff00)
  366. #define WDT_START_2 (0x00ff)
  367. #define WDT_STOP_1 (0xee00)
  368. #define WDT_STOP_2 (0x00ee)
  369. /* Watchdog reset length register */
  370. #define WDT_RSTLEN_REG 0x8
  371. /* Watchdog soft reset register (BCM6328 only) */
  372. #define WDT_SOFTRESET_REG 0xc
  373. /*************************************************************************
  374. * _REG relative to RSET_UARTx
  375. *************************************************************************/
  376. /* UART Control Register */
  377. #define UART_CTL_REG 0x0
  378. #define UART_CTL_RXTMOUTCNT_SHIFT 0
  379. #define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
  380. #define UART_CTL_RSTTXDN_SHIFT 5
  381. #define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT)
  382. #define UART_CTL_RSTRXFIFO_SHIFT 6
  383. #define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
  384. #define UART_CTL_RSTTXFIFO_SHIFT 7
  385. #define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
  386. #define UART_CTL_STOPBITS_SHIFT 8
  387. #define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
  388. #define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
  389. #define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT)
  390. #define UART_CTL_BITSPERSYM_SHIFT 12
  391. #define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
  392. #define UART_CTL_XMITBRK_SHIFT 14
  393. #define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
  394. #define UART_CTL_RSVD_SHIFT 15
  395. #define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
  396. #define UART_CTL_RXPAREVEN_SHIFT 16
  397. #define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
  398. #define UART_CTL_RXPAREN_SHIFT 17
  399. #define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
  400. #define UART_CTL_TXPAREVEN_SHIFT 18
  401. #define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
  402. #define UART_CTL_TXPAREN_SHIFT 18
  403. #define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
  404. #define UART_CTL_LOOPBACK_SHIFT 20
  405. #define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
  406. #define UART_CTL_RXEN_SHIFT 21
  407. #define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
  408. #define UART_CTL_TXEN_SHIFT 22
  409. #define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
  410. #define UART_CTL_BRGEN_SHIFT 23
  411. #define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
  412. /* UART Baudword register */
  413. #define UART_BAUD_REG 0x4
  414. /* UART Misc Control register */
  415. #define UART_MCTL_REG 0x8
  416. #define UART_MCTL_DTR_SHIFT 0
  417. #define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT)
  418. #define UART_MCTL_RTS_SHIFT 1
  419. #define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT)
  420. #define UART_MCTL_RXFIFOTHRESH_SHIFT 8
  421. #define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
  422. #define UART_MCTL_TXFIFOTHRESH_SHIFT 12
  423. #define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
  424. #define UART_MCTL_RXFIFOFILL_SHIFT 16
  425. #define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
  426. #define UART_MCTL_TXFIFOFILL_SHIFT 24
  427. #define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
  428. /* UART External Input Configuration register */
  429. #define UART_EXTINP_REG 0xc
  430. #define UART_EXTINP_RI_SHIFT 0
  431. #define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT)
  432. #define UART_EXTINP_CTS_SHIFT 1
  433. #define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT)
  434. #define UART_EXTINP_DCD_SHIFT 2
  435. #define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT)
  436. #define UART_EXTINP_DSR_SHIFT 3
  437. #define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT)
  438. #define UART_EXTINP_IRSTAT(x) (1 << (x + 4))
  439. #define UART_EXTINP_IRMASK(x) (1 << (x + 8))
  440. #define UART_EXTINP_IR_RI 0
  441. #define UART_EXTINP_IR_CTS 1
  442. #define UART_EXTINP_IR_DCD 2
  443. #define UART_EXTINP_IR_DSR 3
  444. #define UART_EXTINP_RI_NOSENSE_SHIFT 16
  445. #define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT)
  446. #define UART_EXTINP_CTS_NOSENSE_SHIFT 17
  447. #define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
  448. #define UART_EXTINP_DCD_NOSENSE_SHIFT 18
  449. #define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
  450. #define UART_EXTINP_DSR_NOSENSE_SHIFT 19
  451. #define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
  452. /* UART Interrupt register */
  453. #define UART_IR_REG 0x10
  454. #define UART_IR_MASK(x) (1 << (x + 16))
  455. #define UART_IR_STAT(x) (1 << (x))
  456. #define UART_IR_EXTIP 0
  457. #define UART_IR_TXUNDER 1
  458. #define UART_IR_TXOVER 2
  459. #define UART_IR_TXTRESH 3
  460. #define UART_IR_TXRDLATCH 4
  461. #define UART_IR_TXEMPTY 5
  462. #define UART_IR_RXUNDER 6
  463. #define UART_IR_RXOVER 7
  464. #define UART_IR_RXTIMEOUT 8
  465. #define UART_IR_RXFULL 9
  466. #define UART_IR_RXTHRESH 10
  467. #define UART_IR_RXNOTEMPTY 11
  468. #define UART_IR_RXFRAMEERR 12
  469. #define UART_IR_RXPARERR 13
  470. #define UART_IR_RXBRK 14
  471. #define UART_IR_TXDONE 15
  472. /* UART Fifo register */
  473. #define UART_FIFO_REG 0x14
  474. #define UART_FIFO_VALID_SHIFT 0
  475. #define UART_FIFO_VALID_MASK 0xff
  476. #define UART_FIFO_FRAMEERR_SHIFT 8
  477. #define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
  478. #define UART_FIFO_PARERR_SHIFT 9
  479. #define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
  480. #define UART_FIFO_BRKDET_SHIFT 10
  481. #define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
  482. #define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
  483. UART_FIFO_PARERR_MASK | \
  484. UART_FIFO_BRKDET_MASK)
  485. /*************************************************************************
  486. * _REG relative to RSET_GPIO
  487. *************************************************************************/
  488. /* GPIO registers */
  489. #define GPIO_CTL_HI_REG 0x0
  490. #define GPIO_CTL_LO_REG 0x4
  491. #define GPIO_DATA_HI_REG 0x8
  492. #define GPIO_DATA_LO_REG 0xC
  493. #define GPIO_DATA_LO_REG_6345 0x8
  494. /* GPIO mux registers and constants */
  495. #define GPIO_MODE_REG 0x18
  496. #define GPIO_MODE_6348_G4_DIAG 0x00090000
  497. #define GPIO_MODE_6348_G4_UTOPIA 0x00080000
  498. #define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000
  499. #define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000
  500. #define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000
  501. #define GPIO_MODE_6348_G3_DIAG 0x00009000
  502. #define GPIO_MODE_6348_G3_UTOPIA 0x00008000
  503. #define GPIO_MODE_6348_G3_EXT_MII 0x00007000
  504. #define GPIO_MODE_6348_G2_DIAG 0x00000900
  505. #define GPIO_MODE_6348_G2_PCI 0x00000500
  506. #define GPIO_MODE_6348_G1_DIAG 0x00000090
  507. #define GPIO_MODE_6348_G1_UTOPIA 0x00000080
  508. #define GPIO_MODE_6348_G1_SPI_UART 0x00000060
  509. #define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060
  510. #define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040
  511. #define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020
  512. #define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010
  513. #define GPIO_MODE_6348_G0_DIAG 0x00000009
  514. #define GPIO_MODE_6348_G0_EXT_MII 0x00000007
  515. #define GPIO_MODE_6358_EXTRACS (1 << 5)
  516. #define GPIO_MODE_6358_UART1 (1 << 6)
  517. #define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
  518. #define GPIO_MODE_6358_SERIAL_LED (1 << 10)
  519. #define GPIO_MODE_6358_UTOPIA (1 << 12)
  520. #define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0)
  521. #define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1)
  522. #define GPIO_MODE_6368_SYS_IRQ (1 << 2)
  523. #define GPIO_MODE_6368_SERIAL_LED_DATA (1 << 3)
  524. #define GPIO_MODE_6368_SERIAL_LED_CLK (1 << 4)
  525. #define GPIO_MODE_6368_INET_LED (1 << 5)
  526. #define GPIO_MODE_6368_EPHY0_LED (1 << 6)
  527. #define GPIO_MODE_6368_EPHY1_LED (1 << 7)
  528. #define GPIO_MODE_6368_EPHY2_LED (1 << 8)
  529. #define GPIO_MODE_6368_EPHY3_LED (1 << 9)
  530. #define GPIO_MODE_6368_ROBOSW_LED_DAT (1 << 10)
  531. #define GPIO_MODE_6368_ROBOSW_LED_CLK (1 << 11)
  532. #define GPIO_MODE_6368_ROBOSW_LED0 (1 << 12)
  533. #define GPIO_MODE_6368_ROBOSW_LED1 (1 << 13)
  534. #define GPIO_MODE_6368_USBD_LED (1 << 14)
  535. #define GPIO_MODE_6368_NTR_PULSE (1 << 15)
  536. #define GPIO_MODE_6368_PCI_REQ1 (1 << 16)
  537. #define GPIO_MODE_6368_PCI_GNT1 (1 << 17)
  538. #define GPIO_MODE_6368_PCI_INTB (1 << 18)
  539. #define GPIO_MODE_6368_PCI_REQ0 (1 << 19)
  540. #define GPIO_MODE_6368_PCI_GNT0 (1 << 20)
  541. #define GPIO_MODE_6368_PCMCIA_CD1 (1 << 22)
  542. #define GPIO_MODE_6368_PCMCIA_CD2 (1 << 23)
  543. #define GPIO_MODE_6368_PCMCIA_VS1 (1 << 24)
  544. #define GPIO_MODE_6368_PCMCIA_VS2 (1 << 25)
  545. #define GPIO_MODE_6368_EBI_CS2 (1 << 26)
  546. #define GPIO_MODE_6368_EBI_CS3 (1 << 27)
  547. #define GPIO_MODE_6368_SPI_SSN2 (1 << 28)
  548. #define GPIO_MODE_6368_SPI_SSN3 (1 << 29)
  549. #define GPIO_MODE_6368_SPI_SSN4 (1 << 30)
  550. #define GPIO_MODE_6368_SPI_SSN5 (1 << 31)
  551. #define GPIO_PINMUX_OTHR_REG 0x24
  552. #define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12
  553. #define GPIO_PINMUX_OTHR_6328_USB_MASK (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
  554. #define GPIO_PINMUX_OTHR_6328_USB_HOST (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
  555. #define GPIO_PINMUX_OTHR_6328_USB_DEV (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
  556. #define GPIO_BASEMODE_6368_REG 0x38
  557. #define GPIO_BASEMODE_6368_UART2 0x1
  558. #define GPIO_BASEMODE_6368_GPIO 0x0
  559. #define GPIO_BASEMODE_6368_MASK 0x7
  560. /* those bits must be kept as read in gpio basemode register*/
  561. #define GPIO_STRAPBUS_REG 0x40
  562. #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
  563. #define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
  564. #define STRAPBUS_6368_BOOT_SEL_MASK 0x3
  565. #define STRAPBUS_6368_BOOT_SEL_NAND 0
  566. #define STRAPBUS_6368_BOOT_SEL_SERIAL 1
  567. #define STRAPBUS_6368_BOOT_SEL_PARALLEL 3
  568. /*************************************************************************
  569. * _REG relative to RSET_ENET
  570. *************************************************************************/
  571. /* Receiver Configuration register */
  572. #define ENET_RXCFG_REG 0x0
  573. #define ENET_RXCFG_ALLMCAST_SHIFT 1
  574. #define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT)
  575. #define ENET_RXCFG_PROMISC_SHIFT 3
  576. #define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT)
  577. #define ENET_RXCFG_LOOPBACK_SHIFT 4
  578. #define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT)
  579. #define ENET_RXCFG_ENFLOW_SHIFT 5
  580. #define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT)
  581. /* Receive Maximum Length register */
  582. #define ENET_RXMAXLEN_REG 0x4
  583. #define ENET_RXMAXLEN_SHIFT 0
  584. #define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT)
  585. /* Transmit Maximum Length register */
  586. #define ENET_TXMAXLEN_REG 0x8
  587. #define ENET_TXMAXLEN_SHIFT 0
  588. #define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT)
  589. /* MII Status/Control register */
  590. #define ENET_MIISC_REG 0x10
  591. #define ENET_MIISC_MDCFREQDIV_SHIFT 0
  592. #define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
  593. #define ENET_MIISC_PREAMBLEEN_SHIFT 7
  594. #define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT)
  595. /* MII Data register */
  596. #define ENET_MIIDATA_REG 0x14
  597. #define ENET_MIIDATA_DATA_SHIFT 0
  598. #define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT)
  599. #define ENET_MIIDATA_TA_SHIFT 16
  600. #define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT)
  601. #define ENET_MIIDATA_REG_SHIFT 18
  602. #define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT)
  603. #define ENET_MIIDATA_PHYID_SHIFT 23
  604. #define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT)
  605. #define ENET_MIIDATA_OP_READ_MASK (0x6 << 28)
  606. #define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28)
  607. /* Ethernet Interrupt Mask register */
  608. #define ENET_IRMASK_REG 0x18
  609. /* Ethernet Interrupt register */
  610. #define ENET_IR_REG 0x1c
  611. #define ENET_IR_MII (1 << 0)
  612. #define ENET_IR_MIB (1 << 1)
  613. #define ENET_IR_FLOWC (1 << 2)
  614. /* Ethernet Control register */
  615. #define ENET_CTL_REG 0x2c
  616. #define ENET_CTL_ENABLE_SHIFT 0
  617. #define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT)
  618. #define ENET_CTL_DISABLE_SHIFT 1
  619. #define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT)
  620. #define ENET_CTL_SRESET_SHIFT 2
  621. #define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT)
  622. #define ENET_CTL_EPHYSEL_SHIFT 3
  623. #define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT)
  624. /* Transmit Control register */
  625. #define ENET_TXCTL_REG 0x30
  626. #define ENET_TXCTL_FD_SHIFT 0
  627. #define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT)
  628. /* Transmit Watermask register */
  629. #define ENET_TXWMARK_REG 0x34
  630. #define ENET_TXWMARK_WM_SHIFT 0
  631. #define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT)
  632. /* MIB Control register */
  633. #define ENET_MIBCTL_REG 0x38
  634. #define ENET_MIBCTL_RDCLEAR_SHIFT 0
  635. #define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT)
  636. /* Perfect Match Data Low register */
  637. #define ENET_PML_REG(x) (0x58 + (x) * 8)
  638. #define ENET_PMH_REG(x) (0x5c + (x) * 8)
  639. #define ENET_PMH_DATAVALID_SHIFT 16
  640. #define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT)
  641. /* MIB register */
  642. #define ENET_MIB_REG(x) (0x200 + (x) * 4)
  643. #define ENET_MIB_REG_COUNT 55
  644. /*************************************************************************
  645. * _REG relative to RSET_ENETDMA
  646. *************************************************************************/
  647. /* Controller Configuration Register */
  648. #define ENETDMA_CFG_REG (0x0)
  649. #define ENETDMA_CFG_EN_SHIFT 0
  650. #define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT)
  651. #define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1))
  652. /* Flow Control Descriptor Low Threshold register */
  653. #define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6)
  654. /* Flow Control Descriptor High Threshold register */
  655. #define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6)
  656. /* Flow Control Descriptor Buffer Alloca Threshold register */
  657. #define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6)
  658. #define ENETDMA_BUFALLOC_FORCE_SHIFT 31
  659. #define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
  660. /* Global interrupt status */
  661. #define ENETDMA_GLB_IRQSTAT_REG (0x40)
  662. /* Global interrupt mask */
  663. #define ENETDMA_GLB_IRQMASK_REG (0x44)
  664. /* Channel Configuration register */
  665. #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10)
  666. #define ENETDMA_CHANCFG_EN_SHIFT 0
  667. #define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
  668. #define ENETDMA_CHANCFG_PKTHALT_SHIFT 1
  669. #define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
  670. /* Interrupt Control/Status register */
  671. #define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10)
  672. #define ENETDMA_IR_BUFDONE_MASK (1 << 0)
  673. #define ENETDMA_IR_PKTDONE_MASK (1 << 1)
  674. #define ENETDMA_IR_NOTOWNER_MASK (1 << 2)
  675. /* Interrupt Mask register */
  676. #define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10)
  677. /* Maximum Burst Length */
  678. #define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10)
  679. /* Ring Start Address register */
  680. #define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10)
  681. /* State Ram Word 2 */
  682. #define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10)
  683. /* State Ram Word 3 */
  684. #define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10)
  685. /* State Ram Word 4 */
  686. #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
  687. /*************************************************************************
  688. * _REG relative to RSET_ENETDMAC
  689. *************************************************************************/
  690. /* Channel Configuration register */
  691. #define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10)
  692. #define ENETDMAC_CHANCFG_EN_SHIFT 0
  693. #define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMAC_CHANCFG_EN_SHIFT)
  694. #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
  695. #define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
  696. #define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2
  697. #define ENETDMAC_CHANCFG_BUFHALT_MASK (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
  698. /* Interrupt Control/Status register */
  699. #define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10)
  700. #define ENETDMAC_IR_BUFDONE_MASK (1 << 0)
  701. #define ENETDMAC_IR_PKTDONE_MASK (1 << 1)
  702. #define ENETDMAC_IR_NOTOWNER_MASK (1 << 2)
  703. /* Interrupt Mask register */
  704. #define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10)
  705. /* Maximum Burst Length */
  706. #define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10)
  707. /*************************************************************************
  708. * _REG relative to RSET_ENETDMAS
  709. *************************************************************************/
  710. /* Ring Start Address register */
  711. #define ENETDMAS_RSTART_REG(x) ((x) * 0x10)
  712. /* State Ram Word 2 */
  713. #define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10)
  714. /* State Ram Word 3 */
  715. #define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10)
  716. /* State Ram Word 4 */
  717. #define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10)
  718. /*************************************************************************
  719. * _REG relative to RSET_ENETSW
  720. *************************************************************************/
  721. /* MIB register */
  722. #define ENETSW_MIB_REG(x) (0x2800 + (x) * 4)
  723. #define ENETSW_MIB_REG_COUNT 47
  724. /*************************************************************************
  725. * _REG relative to RSET_OHCI_PRIV
  726. *************************************************************************/
  727. #define OHCI_PRIV_REG 0x0
  728. #define OHCI_PRIV_PORT1_HOST_SHIFT 0
  729. #define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT)
  730. #define OHCI_PRIV_REG_SWAP_SHIFT 3
  731. #define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT)
  732. /*************************************************************************
  733. * _REG relative to RSET_USBH_PRIV
  734. *************************************************************************/
  735. #define USBH_PRIV_SWAP_6358_REG 0x0
  736. #define USBH_PRIV_SWAP_6368_REG 0x1c
  737. #define USBH_PRIV_SWAP_USBD_SHIFT 6
  738. #define USBH_PRIV_SWAP_USBD_MASK (1 << USBH_PRIV_SWAP_USBD_SHIFT)
  739. #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
  740. #define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
  741. #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
  742. #define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)
  743. #define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1
  744. #define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)
  745. #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
  746. #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
  747. #define USBH_PRIV_UTMI_CTL_6368_REG 0x10
  748. #define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12
  749. #define USBH_PRIV_UTMI_CTL_NODRIV_MASK (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT)
  750. #define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT 0
  751. #define USBH_PRIV_UTMI_CTL_HOSTB_MASK (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT)
  752. #define USBH_PRIV_TEST_6358_REG 0x24
  753. #define USBH_PRIV_TEST_6368_REG 0x14
  754. #define USBH_PRIV_SETUP_6368_REG 0x28
  755. #define USBH_PRIV_SETUP_IOC_SHIFT 4
  756. #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT)
  757. /*************************************************************************
  758. * _REG relative to RSET_USBD
  759. *************************************************************************/
  760. /* General control */
  761. #define USBD_CONTROL_REG 0x00
  762. #define USBD_CONTROL_TXZLENINS_SHIFT 14
  763. #define USBD_CONTROL_TXZLENINS_MASK (1 << USBD_CONTROL_TXZLENINS_SHIFT)
  764. #define USBD_CONTROL_AUTO_CSRS_SHIFT 13
  765. #define USBD_CONTROL_AUTO_CSRS_MASK (1 << USBD_CONTROL_AUTO_CSRS_SHIFT)
  766. #define USBD_CONTROL_RXZSCFG_SHIFT 12
  767. #define USBD_CONTROL_RXZSCFG_MASK (1 << USBD_CONTROL_RXZSCFG_SHIFT)
  768. #define USBD_CONTROL_INIT_SEL_SHIFT 8
  769. #define USBD_CONTROL_INIT_SEL_MASK (0xf << USBD_CONTROL_INIT_SEL_SHIFT)
  770. #define USBD_CONTROL_FIFO_RESET_SHIFT 6
  771. #define USBD_CONTROL_FIFO_RESET_MASK (3 << USBD_CONTROL_FIFO_RESET_SHIFT)
  772. #define USBD_CONTROL_SETUPERRLOCK_SHIFT 5
  773. #define USBD_CONTROL_SETUPERRLOCK_MASK (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT)
  774. #define USBD_CONTROL_DONE_CSRS_SHIFT 0
  775. #define USBD_CONTROL_DONE_CSRS_MASK (1 << USBD_CONTROL_DONE_CSRS_SHIFT)
  776. /* Strap options */
  777. #define USBD_STRAPS_REG 0x04
  778. #define USBD_STRAPS_APP_SELF_PWR_SHIFT 10
  779. #define USBD_STRAPS_APP_SELF_PWR_MASK (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT)
  780. #define USBD_STRAPS_APP_DISCON_SHIFT 9
  781. #define USBD_STRAPS_APP_DISCON_MASK (1 << USBD_STRAPS_APP_DISCON_SHIFT)
  782. #define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8
  783. #define USBD_STRAPS_APP_CSRPRGSUP_MASK (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT)
  784. #define USBD_STRAPS_APP_RMTWKUP_SHIFT 6
  785. #define USBD_STRAPS_APP_RMTWKUP_MASK (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT)
  786. #define USBD_STRAPS_APP_RAM_IF_SHIFT 7
  787. #define USBD_STRAPS_APP_RAM_IF_MASK (1 << USBD_STRAPS_APP_RAM_IF_SHIFT)
  788. #define USBD_STRAPS_APP_8BITPHY_SHIFT 2
  789. #define USBD_STRAPS_APP_8BITPHY_MASK (1 << USBD_STRAPS_APP_8BITPHY_SHIFT)
  790. #define USBD_STRAPS_SPEED_SHIFT 0
  791. #define USBD_STRAPS_SPEED_MASK (3 << USBD_STRAPS_SPEED_SHIFT)
  792. /* Stall control */
  793. #define USBD_STALL_REG 0x08
  794. #define USBD_STALL_UPDATE_SHIFT 7
  795. #define USBD_STALL_UPDATE_MASK (1 << USBD_STALL_UPDATE_SHIFT)
  796. #define USBD_STALL_ENABLE_SHIFT 6
  797. #define USBD_STALL_ENABLE_MASK (1 << USBD_STALL_ENABLE_SHIFT)
  798. #define USBD_STALL_EPNUM_SHIFT 0
  799. #define USBD_STALL_EPNUM_MASK (0xf << USBD_STALL_EPNUM_SHIFT)
  800. /* General status */
  801. #define USBD_STATUS_REG 0x0c
  802. #define USBD_STATUS_SOF_SHIFT 16
  803. #define USBD_STATUS_SOF_MASK (0x7ff << USBD_STATUS_SOF_SHIFT)
  804. #define USBD_STATUS_SPD_SHIFT 12
  805. #define USBD_STATUS_SPD_MASK (3 << USBD_STATUS_SPD_SHIFT)
  806. #define USBD_STATUS_ALTINTF_SHIFT 8
  807. #define USBD_STATUS_ALTINTF_MASK (0xf << USBD_STATUS_ALTINTF_SHIFT)
  808. #define USBD_STATUS_INTF_SHIFT 4
  809. #define USBD_STATUS_INTF_MASK (0xf << USBD_STATUS_INTF_SHIFT)
  810. #define USBD_STATUS_CFG_SHIFT 0
  811. #define USBD_STATUS_CFG_MASK (0xf << USBD_STATUS_CFG_SHIFT)
  812. /* Other events */
  813. #define USBD_EVENTS_REG 0x10
  814. #define USBD_EVENTS_USB_LINK_SHIFT 10
  815. #define USBD_EVENTS_USB_LINK_MASK (1 << USBD_EVENTS_USB_LINK_SHIFT)
  816. /* IRQ status */
  817. #define USBD_EVENT_IRQ_STATUS_REG 0x14
  818. /* IRQ level (2 bits per IRQ event) */
  819. #define USBD_EVENT_IRQ_CFG_HI_REG 0x18
  820. #define USBD_EVENT_IRQ_CFG_LO_REG 0x1c
  821. #define USBD_EVENT_IRQ_CFG_SHIFT(x) ((x & 0xf) << 1)
  822. #define USBD_EVENT_IRQ_CFG_MASK(x) (3 << USBD_EVENT_IRQ_CFG_SHIFT(x))
  823. #define USBD_EVENT_IRQ_CFG_RISING(x) (0 << USBD_EVENT_IRQ_CFG_SHIFT(x))
  824. #define USBD_EVENT_IRQ_CFG_FALLING(x) (1 << USBD_EVENT_IRQ_CFG_SHIFT(x))
  825. /* IRQ mask (1=unmasked) */
  826. #define USBD_EVENT_IRQ_MASK_REG 0x20
  827. /* IRQ bits */
  828. #define USBD_EVENT_IRQ_USB_LINK 10
  829. #define USBD_EVENT_IRQ_SETCFG 9
  830. #define USBD_EVENT_IRQ_SETINTF 8
  831. #define USBD_EVENT_IRQ_ERRATIC_ERR 7
  832. #define USBD_EVENT_IRQ_SET_CSRS 6
  833. #define USBD_EVENT_IRQ_SUSPEND 5
  834. #define USBD_EVENT_IRQ_EARLY_SUSPEND 4
  835. #define USBD_EVENT_IRQ_SOF 3
  836. #define USBD_EVENT_IRQ_ENUM_ON 2
  837. #define USBD_EVENT_IRQ_SETUP 1
  838. #define USBD_EVENT_IRQ_USB_RESET 0
  839. /* TX FIFO partitioning */
  840. #define USBD_TXFIFO_CONFIG_REG 0x40
  841. #define USBD_TXFIFO_CONFIG_END_SHIFT 16
  842. #define USBD_TXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
  843. #define USBD_TXFIFO_CONFIG_START_SHIFT 0
  844. #define USBD_TXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
  845. /* RX FIFO partitioning */
  846. #define USBD_RXFIFO_CONFIG_REG 0x44
  847. #define USBD_RXFIFO_CONFIG_END_SHIFT 16
  848. #define USBD_RXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
  849. #define USBD_RXFIFO_CONFIG_START_SHIFT 0
  850. #define USBD_RXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
  851. /* TX FIFO/endpoint configuration */
  852. #define USBD_TXFIFO_EPSIZE_REG 0x48
  853. /* RX FIFO/endpoint configuration */
  854. #define USBD_RXFIFO_EPSIZE_REG 0x4c
  855. /* Endpoint<->DMA mappings */
  856. #define USBD_EPNUM_TYPEMAP_REG 0x50
  857. #define USBD_EPNUM_TYPEMAP_TYPE_SHIFT 8
  858. #define USBD_EPNUM_TYPEMAP_TYPE_MASK (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT)
  859. #define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0
  860. #define USBD_EPNUM_TYPEMAP_DMA_CH_MASK (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT)
  861. /* Misc per-endpoint settings */
  862. #define USBD_CSR_SETUPADDR_REG 0x80
  863. #define USBD_CSR_SETUPADDR_DEF 0xb550
  864. #define USBD_CSR_EP_REG(x) (0x84 + (x) * 4)
  865. #define USBD_CSR_EP_MAXPKT_SHIFT 19
  866. #define USBD_CSR_EP_MAXPKT_MASK (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT)
  867. #define USBD_CSR_EP_ALTIFACE_SHIFT 15
  868. #define USBD_CSR_EP_ALTIFACE_MASK (0xf << USBD_CSR_EP_ALTIFACE_SHIFT)
  869. #define USBD_CSR_EP_IFACE_SHIFT 11
  870. #define USBD_CSR_EP_IFACE_MASK (0xf << USBD_CSR_EP_IFACE_SHIFT)
  871. #define USBD_CSR_EP_CFG_SHIFT 7
  872. #define USBD_CSR_EP_CFG_MASK (0xf << USBD_CSR_EP_CFG_SHIFT)
  873. #define USBD_CSR_EP_TYPE_SHIFT 5
  874. #define USBD_CSR_EP_TYPE_MASK (3 << USBD_CSR_EP_TYPE_SHIFT)
  875. #define USBD_CSR_EP_DIR_SHIFT 4
  876. #define USBD_CSR_EP_DIR_MASK (1 << USBD_CSR_EP_DIR_SHIFT)
  877. #define USBD_CSR_EP_LOG_SHIFT 0
  878. #define USBD_CSR_EP_LOG_MASK (0xf << USBD_CSR_EP_LOG_SHIFT)
  879. /*************************************************************************
  880. * _REG relative to RSET_MPI
  881. *************************************************************************/
  882. /* well known (hard wired) chip select */
  883. #define MPI_CS_PCMCIA_COMMON 4
  884. #define MPI_CS_PCMCIA_ATTR 5
  885. #define MPI_CS_PCMCIA_IO 6
  886. /* Chip select base register */
  887. #define MPI_CSBASE_REG(x) (0x0 + (x) * 8)
  888. #define MPI_CSBASE_BASE_SHIFT 13
  889. #define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT)
  890. #define MPI_CSBASE_SIZE_SHIFT 0
  891. #define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT)
  892. #define MPI_CSBASE_SIZE_8K 0
  893. #define MPI_CSBASE_SIZE_16K 1
  894. #define MPI_CSBASE_SIZE_32K 2
  895. #define MPI_CSBASE_SIZE_64K 3
  896. #define MPI_CSBASE_SIZE_128K 4
  897. #define MPI_CSBASE_SIZE_256K 5
  898. #define MPI_CSBASE_SIZE_512K 6
  899. #define MPI_CSBASE_SIZE_1M 7
  900. #define MPI_CSBASE_SIZE_2M 8
  901. #define MPI_CSBASE_SIZE_4M 9
  902. #define MPI_CSBASE_SIZE_8M 10
  903. #define MPI_CSBASE_SIZE_16M 11
  904. #define MPI_CSBASE_SIZE_32M 12
  905. #define MPI_CSBASE_SIZE_64M 13
  906. #define MPI_CSBASE_SIZE_128M 14
  907. #define MPI_CSBASE_SIZE_256M 15
  908. /* Chip select control register */
  909. #define MPI_CSCTL_REG(x) (0x4 + (x) * 8)
  910. #define MPI_CSCTL_ENABLE_MASK (1 << 0)
  911. #define MPI_CSCTL_WAIT_SHIFT 1
  912. #define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT)
  913. #define MPI_CSCTL_DATA16_MASK (1 << 4)
  914. #define MPI_CSCTL_SYNCMODE_MASK (1 << 7)
  915. #define MPI_CSCTL_TSIZE_MASK (1 << 8)
  916. #define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10)
  917. #define MPI_CSCTL_SETUP_SHIFT 16
  918. #define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT)
  919. #define MPI_CSCTL_HOLD_SHIFT 20
  920. #define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT)
  921. /* PCI registers */
  922. #define MPI_SP0_RANGE_REG 0x100
  923. #define MPI_SP0_REMAP_REG 0x104
  924. #define MPI_SP0_REMAP_ENABLE_MASK (1 << 0)
  925. #define MPI_SP1_RANGE_REG 0x10C
  926. #define MPI_SP1_REMAP_REG 0x110
  927. #define MPI_SP1_REMAP_ENABLE_MASK (1 << 0)
  928. #define MPI_L2PCFG_REG 0x11C
  929. #define MPI_L2PCFG_CFG_TYPE_SHIFT 0
  930. #define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
  931. #define MPI_L2PCFG_REG_SHIFT 2
  932. #define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT)
  933. #define MPI_L2PCFG_FUNC_SHIFT 8
  934. #define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT)
  935. #define MPI_L2PCFG_DEVNUM_SHIFT 11
  936. #define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
  937. #define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30)
  938. #define MPI_L2PCFG_CFG_SEL_MASK (1 << 31)
  939. #define MPI_L2PMEMRANGE1_REG 0x120
  940. #define MPI_L2PMEMBASE1_REG 0x124
  941. #define MPI_L2PMEMREMAP1_REG 0x128
  942. #define MPI_L2PMEMRANGE2_REG 0x12C
  943. #define MPI_L2PMEMBASE2_REG 0x130
  944. #define MPI_L2PMEMREMAP2_REG 0x134
  945. #define MPI_L2PIORANGE_REG 0x138
  946. #define MPI_L2PIOBASE_REG 0x13C
  947. #define MPI_L2PIOREMAP_REG 0x140
  948. #define MPI_L2P_BASE_MASK (0xffff8000)
  949. #define MPI_L2PREMAP_ENABLED_MASK (1 << 0)
  950. #define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2)
  951. #define MPI_PCIMODESEL_REG 0x144
  952. #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
  953. #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
  954. #define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2)
  955. #define MPI_PCIMODESEL_PREFETCH_SHIFT 4
  956. #define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
  957. #define MPI_LOCBUSCTL_REG 0x14C
  958. #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0)
  959. #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1)
  960. #define MPI_LOCINT_REG 0x150
  961. #define MPI_LOCINT_MASK(x) (1 << (x + 16))
  962. #define MPI_LOCINT_STAT(x) (1 << (x))
  963. #define MPI_LOCINT_DIR_FAILED 6
  964. #define MPI_LOCINT_EXT_PCI_INT 7
  965. #define MPI_LOCINT_SERR 8
  966. #define MPI_LOCINT_CSERR 9
  967. #define MPI_PCICFGCTL_REG 0x178
  968. #define MPI_PCICFGCTL_CFGADDR_SHIFT 2
  969. #define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
  970. #define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7)
  971. #define MPI_PCICFGDATA_REG 0x17C
  972. /* PCI host bridge custom register */
  973. #define BCMPCI_REG_TIMERS 0x40
  974. #define REG_TIMER_TRDY_SHIFT 0
  975. #define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT)
  976. #define REG_TIMER_RETRY_SHIFT 8
  977. #define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT)
  978. /*************************************************************************
  979. * _REG relative to RSET_PCMCIA
  980. *************************************************************************/
  981. #define PCMCIA_C1_REG 0x0
  982. #define PCMCIA_C1_CD1_MASK (1 << 0)
  983. #define PCMCIA_C1_CD2_MASK (1 << 1)
  984. #define PCMCIA_C1_VS1_MASK (1 << 2)
  985. #define PCMCIA_C1_VS2_MASK (1 << 3)
  986. #define PCMCIA_C1_VS1OE_MASK (1 << 6)
  987. #define PCMCIA_C1_VS2OE_MASK (1 << 7)
  988. #define PCMCIA_C1_CBIDSEL_SHIFT (8)
  989. #define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
  990. #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13)
  991. #define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14)
  992. #define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15)
  993. #define PCMCIA_C1_RESET_MASK (1 << 18)
  994. #define PCMCIA_C2_REG 0x8
  995. #define PCMCIA_C2_DATA16_MASK (1 << 0)
  996. #define PCMCIA_C2_BYTESWAP_MASK (1 << 1)
  997. #define PCMCIA_C2_RWCOUNT_SHIFT 2
  998. #define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
  999. #define PCMCIA_C2_INACTIVE_SHIFT 8
  1000. #define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT)
  1001. #define PCMCIA_C2_SETUP_SHIFT 16
  1002. #define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT)
  1003. #define PCMCIA_C2_HOLD_SHIFT 24
  1004. #define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT)
  1005. /*************************************************************************
  1006. * _REG relative to RSET_SDRAM
  1007. *************************************************************************/
  1008. #define SDRAM_CFG_REG 0x0
  1009. #define SDRAM_CFG_ROW_SHIFT 4
  1010. #define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
  1011. #define SDRAM_CFG_COL_SHIFT 6
  1012. #define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
  1013. #define SDRAM_CFG_32B_SHIFT 10
  1014. #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
  1015. #define SDRAM_CFG_BANK_SHIFT 13
  1016. #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
  1017. #define SDRAM_MBASE_REG 0xc
  1018. #define SDRAM_PRIO_REG 0x2C
  1019. #define SDRAM_PRIO_MIPS_SHIFT 29
  1020. #define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
  1021. #define SDRAM_PRIO_ADSL_SHIFT 30
  1022. #define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT)
  1023. #define SDRAM_PRIO_EN_SHIFT 31
  1024. #define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT)
  1025. /*************************************************************************
  1026. * _REG relative to RSET_MEMC
  1027. *************************************************************************/
  1028. #define MEMC_CFG_REG 0x4
  1029. #define MEMC_CFG_32B_SHIFT 1
  1030. #define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
  1031. #define MEMC_CFG_COL_SHIFT 3
  1032. #define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
  1033. #define MEMC_CFG_ROW_SHIFT 6
  1034. #define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
  1035. /*************************************************************************
  1036. * _REG relative to RSET_DDR
  1037. *************************************************************************/
  1038. #define DDR_CSEND_REG 0x8
  1039. #define DDR_DMIPSPLLCFG_REG 0x18
  1040. #define DMIPSPLLCFG_M1_SHIFT 0
  1041. #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
  1042. #define DMIPSPLLCFG_N1_SHIFT 23
  1043. #define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT)
  1044. #define DMIPSPLLCFG_N2_SHIFT 29
  1045. #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
  1046. #define DDR_DMIPSPLLCFG_6368_REG 0x20
  1047. #define DMIPSPLLCFG_6368_P1_SHIFT 0
  1048. #define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
  1049. #define DMIPSPLLCFG_6368_P2_SHIFT 4
  1050. #define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
  1051. #define DMIPSPLLCFG_6368_NDIV_SHIFT 16
  1052. #define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
  1053. #define DDR_DMIPSPLLDIV_6368_REG 0x24
  1054. #define DMIPSPLLDIV_6368_MDIV_SHIFT 0
  1055. #define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
  1056. /*************************************************************************
  1057. * _REG relative to RSET_M2M
  1058. *************************************************************************/
  1059. #define M2M_RX 0
  1060. #define M2M_TX 1
  1061. #define M2M_SRC_REG(x) ((x) * 0x40 + 0x00)
  1062. #define M2M_DST_REG(x) ((x) * 0x40 + 0x04)
  1063. #define M2M_SIZE_REG(x) ((x) * 0x40 + 0x08)
  1064. #define M2M_CTRL_REG(x) ((x) * 0x40 + 0x0c)
  1065. #define M2M_CTRL_ENABLE_MASK (1 << 0)
  1066. #define M2M_CTRL_IRQEN_MASK (1 << 1)
  1067. #define M2M_CTRL_ERROR_CLR_MASK (1 << 6)
  1068. #define M2M_CTRL_DONE_CLR_MASK (1 << 7)
  1069. #define M2M_CTRL_NOINC_MASK (1 << 8)
  1070. #define M2M_CTRL_PCMCIASWAP_MASK (1 << 9)
  1071. #define M2M_CTRL_SWAPBYTE_MASK (1 << 10)
  1072. #define M2M_CTRL_ENDIAN_MASK (1 << 11)
  1073. #define M2M_STAT_REG(x) ((x) * 0x40 + 0x10)
  1074. #define M2M_STAT_DONE (1 << 0)
  1075. #define M2M_STAT_ERROR (1 << 1)
  1076. #define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14)
  1077. #define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18)
  1078. /*************************************************************************
  1079. * _REG relative to RSET_RNG
  1080. *************************************************************************/
  1081. #define RNG_CTRL 0x00
  1082. #define RNG_EN (1 << 0)
  1083. #define RNG_STAT 0x04
  1084. #define RNG_AVAIL_MASK (0xff000000)
  1085. #define RNG_DATA 0x08
  1086. #define RNG_THRES 0x0c
  1087. #define RNG_MASK 0x10
  1088. /*************************************************************************
  1089. * _REG relative to RSET_SPI
  1090. *************************************************************************/
  1091. /* BCM 6338/6348 SPI core */
  1092. #define SPI_6348_CMD 0x00 /* 16-bits register */
  1093. #define SPI_6348_INT_STATUS 0x02
  1094. #define SPI_6348_INT_MASK_ST 0x03
  1095. #define SPI_6348_INT_MASK 0x04
  1096. #define SPI_6348_ST 0x05
  1097. #define SPI_6348_CLK_CFG 0x06
  1098. #define SPI_6348_FILL_BYTE 0x07
  1099. #define SPI_6348_MSG_TAIL 0x09
  1100. #define SPI_6348_RX_TAIL 0x0b
  1101. #define SPI_6348_MSG_CTL 0x40 /* 8-bits register */
  1102. #define SPI_6348_MSG_CTL_WIDTH 8
  1103. #define SPI_6348_MSG_DATA 0x41
  1104. #define SPI_6348_MSG_DATA_SIZE 0x3f
  1105. #define SPI_6348_RX_DATA 0x80
  1106. #define SPI_6348_RX_DATA_SIZE 0x3f
  1107. /* BCM 6358/6262/6368 SPI core */
  1108. #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
  1109. #define SPI_6358_MSG_CTL_WIDTH 16
  1110. #define SPI_6358_MSG_DATA 0x02
  1111. #define SPI_6358_MSG_DATA_SIZE 0x21e
  1112. #define SPI_6358_RX_DATA 0x400
  1113. #define SPI_6358_RX_DATA_SIZE 0x220
  1114. #define SPI_6358_CMD 0x700 /* 16-bits register */
  1115. #define SPI_6358_INT_STATUS 0x702
  1116. #define SPI_6358_INT_MASK_ST 0x703
  1117. #define SPI_6358_INT_MASK 0x704
  1118. #define SPI_6358_ST 0x705
  1119. #define SPI_6358_CLK_CFG 0x706
  1120. #define SPI_6358_FILL_BYTE 0x707
  1121. #define SPI_6358_MSG_TAIL 0x709
  1122. #define SPI_6358_RX_TAIL 0x70B
  1123. /* Shared SPI definitions */
  1124. /* Message configuration */
  1125. #define SPI_FD_RW 0x00
  1126. #define SPI_HD_W 0x01
  1127. #define SPI_HD_R 0x02
  1128. #define SPI_BYTE_CNT_SHIFT 0
  1129. #define SPI_6348_MSG_TYPE_SHIFT 6
  1130. #define SPI_6358_MSG_TYPE_SHIFT 14
  1131. /* Command */
  1132. #define SPI_CMD_NOOP 0x00
  1133. #define SPI_CMD_SOFT_RESET 0x01
  1134. #define SPI_CMD_HARD_RESET 0x02
  1135. #define SPI_CMD_START_IMMEDIATE 0x03
  1136. #define SPI_CMD_COMMAND_SHIFT 0
  1137. #define SPI_CMD_COMMAND_MASK 0x000f
  1138. #define SPI_CMD_DEVICE_ID_SHIFT 4
  1139. #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
  1140. #define SPI_CMD_ONE_BYTE_SHIFT 11
  1141. #define SPI_CMD_ONE_WIRE_SHIFT 12
  1142. #define SPI_DEV_ID_0 0
  1143. #define SPI_DEV_ID_1 1
  1144. #define SPI_DEV_ID_2 2
  1145. #define SPI_DEV_ID_3 3
  1146. /* Interrupt mask */
  1147. #define SPI_INTR_CMD_DONE 0x01
  1148. #define SPI_INTR_RX_OVERFLOW 0x02
  1149. #define SPI_INTR_TX_UNDERFLOW 0x04
  1150. #define SPI_INTR_TX_OVERFLOW 0x08
  1151. #define SPI_INTR_RX_UNDERFLOW 0x10
  1152. #define SPI_INTR_CLEAR_ALL 0x1f
  1153. /* Status */
  1154. #define SPI_RX_EMPTY 0x02
  1155. #define SPI_CMD_BUSY 0x04
  1156. #define SPI_SERIAL_BUSY 0x08
  1157. /* Clock configuration */
  1158. #define SPI_CLK_20MHZ 0x00
  1159. #define SPI_CLK_0_391MHZ 0x01
  1160. #define SPI_CLK_0_781MHZ 0x02 /* default */
  1161. #define SPI_CLK_1_563MHZ 0x03
  1162. #define SPI_CLK_3_125MHZ 0x04
  1163. #define SPI_CLK_6_250MHZ 0x05
  1164. #define SPI_CLK_12_50MHZ 0x06
  1165. #define SPI_CLK_MASK 0x07
  1166. #define SPI_SSOFFTIME_MASK 0x38
  1167. #define SPI_SSOFFTIME_SHIFT 3
  1168. #define SPI_BYTE_SWAP 0x80
  1169. /*************************************************************************
  1170. * _REG relative to RSET_MISC
  1171. *************************************************************************/
  1172. #define MISC_SERDES_CTRL_6328_REG 0x0
  1173. #define MISC_SERDES_CTRL_6362_REG 0x4
  1174. #define SERDES_PCIE_EN (1 << 0)
  1175. #define SERDES_PCIE_EXD_EN (1 << 15)
  1176. #define MISC_STRAPBUS_6362_REG 0x14
  1177. #define STRAPBUS_6362_FCVO_SHIFT 1
  1178. #define STRAPBUS_6362_HSSPI_CLK_FAST (1 << 13)
  1179. #define STRAPBUS_6362_FCVO_MASK (0x1f << STRAPBUS_6362_FCVO_SHIFT)
  1180. #define STRAPBUS_6362_BOOT_SEL_SERIAL (1 << 15)
  1181. #define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15)
  1182. #define MISC_STRAPBUS_6328_REG 0x240
  1183. #define STRAPBUS_6328_FCVO_SHIFT 7
  1184. #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
  1185. #define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
  1186. #define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
  1187. /*************************************************************************
  1188. * _REG relative to RSET_PCIE
  1189. *************************************************************************/
  1190. #define PCIE_CONFIG2_REG 0x408
  1191. #define CONFIG2_BAR1_SIZE_EN 1
  1192. #define CONFIG2_BAR1_SIZE_MASK 0xf
  1193. #define PCIE_IDVAL3_REG 0x43c
  1194. #define IDVAL3_CLASS_CODE_MASK 0xffffff
  1195. #define IDVAL3_SUBCLASS_SHIFT 8
  1196. #define IDVAL3_CLASS_SHIFT 16
  1197. #define PCIE_DLSTATUS_REG 0x1048
  1198. #define DLSTATUS_PHYLINKUP (1 << 13)
  1199. #define PCIE_BRIDGE_OPT1_REG 0x2820
  1200. #define OPT1_RD_BE_OPT_EN (1 << 7)
  1201. #define OPT1_RD_REPLY_BE_FIX_EN (1 << 9)
  1202. #define OPT1_PCIE_BRIDGE_HOLE_DET_EN (1 << 11)
  1203. #define OPT1_L1_INT_STATUS_MASK_POL (1 << 12)
  1204. #define PCIE_BRIDGE_OPT2_REG 0x2824
  1205. #define OPT2_UBUS_UR_DECODE_DIS (1 << 2)
  1206. #define OPT2_TX_CREDIT_CHK_EN (1 << 4)
  1207. #define OPT2_CFG_TYPE1_BD_SEL (1 << 7)
  1208. #define OPT2_CFG_TYPE1_BUS_NO_SHIFT 16
  1209. #define OPT2_CFG_TYPE1_BUS_NO_MASK (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
  1210. #define PCIE_BRIDGE_BAR0_BASEMASK_REG 0x2828
  1211. #define PCIE_BRIDGE_BAR1_BASEMASK_REG 0x2830
  1212. #define BASEMASK_REMAP_EN (1 << 0)
  1213. #define BASEMASK_SWAP_EN (1 << 1)
  1214. #define BASEMASK_MASK_SHIFT 4
  1215. #define BASEMASK_MASK_MASK (0xfff << BASEMASK_MASK_SHIFT)
  1216. #define BASEMASK_BASE_SHIFT 20
  1217. #define BASEMASK_BASE_MASK (0xfff << BASEMASK_BASE_SHIFT)
  1218. #define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
  1219. #define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
  1220. #define REBASE_ADDR_BASE_SHIFT 20
  1221. #define REBASE_ADDR_BASE_MASK (0xfff << REBASE_ADDR_BASE_SHIFT)
  1222. #define PCIE_BRIDGE_RC_INT_MASK_REG 0x2854
  1223. #define PCIE_RC_INT_A (1 << 0)
  1224. #define PCIE_RC_INT_B (1 << 1)
  1225. #define PCIE_RC_INT_C (1 << 2)
  1226. #define PCIE_RC_INT_D (1 << 3)
  1227. #define PCIE_DEVICE_OFFSET 0x8000
  1228. #endif /* BCM63XX_REGS_H_ */