bcm63xx_cpu.h 37 KB

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  1. #ifndef BCM63XX_CPU_H_
  2. #define BCM63XX_CPU_H_
  3. #include <linux/types.h>
  4. #include <linux/init.h>
  5. /*
  6. * Macro to fetch bcm63xx cpu id and revision, should be optimized at
  7. * compile time if only one CPU support is enabled (idea stolen from
  8. * arm mach-types)
  9. */
  10. #define BCM6328_CPU_ID 0x6328
  11. #define BCM6338_CPU_ID 0x6338
  12. #define BCM6345_CPU_ID 0x6345
  13. #define BCM6348_CPU_ID 0x6348
  14. #define BCM6358_CPU_ID 0x6358
  15. #define BCM6362_CPU_ID 0x6362
  16. #define BCM6368_CPU_ID 0x6368
  17. void __init bcm63xx_cpu_init(void);
  18. u16 __bcm63xx_get_cpu_id(void);
  19. u8 bcm63xx_get_cpu_rev(void);
  20. unsigned int bcm63xx_get_cpu_freq(void);
  21. #ifdef CONFIG_BCM63XX_CPU_6328
  22. # ifdef bcm63xx_get_cpu_id
  23. # undef bcm63xx_get_cpu_id
  24. # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
  25. # define BCMCPU_RUNTIME_DETECT
  26. # else
  27. # define bcm63xx_get_cpu_id() BCM6328_CPU_ID
  28. # endif
  29. # define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
  30. #else
  31. # define BCMCPU_IS_6328() (0)
  32. #endif
  33. #ifdef CONFIG_BCM63XX_CPU_6338
  34. # ifdef bcm63xx_get_cpu_id
  35. # undef bcm63xx_get_cpu_id
  36. # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
  37. # define BCMCPU_RUNTIME_DETECT
  38. # else
  39. # define bcm63xx_get_cpu_id() BCM6338_CPU_ID
  40. # endif
  41. # define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
  42. #else
  43. # define BCMCPU_IS_6338() (0)
  44. #endif
  45. #ifdef CONFIG_BCM63XX_CPU_6345
  46. # ifdef bcm63xx_get_cpu_id
  47. # undef bcm63xx_get_cpu_id
  48. # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
  49. # define BCMCPU_RUNTIME_DETECT
  50. # else
  51. # define bcm63xx_get_cpu_id() BCM6345_CPU_ID
  52. # endif
  53. # define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
  54. #else
  55. # define BCMCPU_IS_6345() (0)
  56. #endif
  57. #ifdef CONFIG_BCM63XX_CPU_6348
  58. # ifdef bcm63xx_get_cpu_id
  59. # undef bcm63xx_get_cpu_id
  60. # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
  61. # define BCMCPU_RUNTIME_DETECT
  62. # else
  63. # define bcm63xx_get_cpu_id() BCM6348_CPU_ID
  64. # endif
  65. # define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
  66. #else
  67. # define BCMCPU_IS_6348() (0)
  68. #endif
  69. #ifdef CONFIG_BCM63XX_CPU_6358
  70. # ifdef bcm63xx_get_cpu_id
  71. # undef bcm63xx_get_cpu_id
  72. # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
  73. # define BCMCPU_RUNTIME_DETECT
  74. # else
  75. # define bcm63xx_get_cpu_id() BCM6358_CPU_ID
  76. # endif
  77. # define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
  78. #else
  79. # define BCMCPU_IS_6358() (0)
  80. #endif
  81. #ifdef CONFIG_BCM63XX_CPU_6362
  82. # ifdef bcm63xx_get_cpu_id
  83. # undef bcm63xx_get_cpu_id
  84. # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
  85. # define BCMCPU_RUNTIME_DETECT
  86. # else
  87. # define bcm63xx_get_cpu_id() BCM6362_CPU_ID
  88. # endif
  89. # define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
  90. #else
  91. # define BCMCPU_IS_6362() (0)
  92. #endif
  93. #ifdef CONFIG_BCM63XX_CPU_6368
  94. # ifdef bcm63xx_get_cpu_id
  95. # undef bcm63xx_get_cpu_id
  96. # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
  97. # define BCMCPU_RUNTIME_DETECT
  98. # else
  99. # define bcm63xx_get_cpu_id() BCM6368_CPU_ID
  100. # endif
  101. # define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
  102. #else
  103. # define BCMCPU_IS_6368() (0)
  104. #endif
  105. #ifndef bcm63xx_get_cpu_id
  106. #error "No CPU support configured"
  107. #endif
  108. /*
  109. * While registers sets are (mostly) the same across 63xx CPU, base
  110. * address of these sets do change.
  111. */
  112. enum bcm63xx_regs_set {
  113. RSET_DSL_LMEM = 0,
  114. RSET_PERF,
  115. RSET_TIMER,
  116. RSET_WDT,
  117. RSET_UART0,
  118. RSET_UART1,
  119. RSET_GPIO,
  120. RSET_SPI,
  121. RSET_UDC0,
  122. RSET_OHCI0,
  123. RSET_OHCI_PRIV,
  124. RSET_USBH_PRIV,
  125. RSET_USBD,
  126. RSET_USBDMA,
  127. RSET_MPI,
  128. RSET_PCMCIA,
  129. RSET_PCIE,
  130. RSET_DSL,
  131. RSET_ENET0,
  132. RSET_ENET1,
  133. RSET_ENETDMA,
  134. RSET_ENETDMAC,
  135. RSET_ENETDMAS,
  136. RSET_ENETSW,
  137. RSET_EHCI0,
  138. RSET_SDRAM,
  139. RSET_MEMC,
  140. RSET_DDR,
  141. RSET_M2M,
  142. RSET_ATM,
  143. RSET_XTM,
  144. RSET_XTMDMA,
  145. RSET_XTMDMAC,
  146. RSET_XTMDMAS,
  147. RSET_PCM,
  148. RSET_PCMDMA,
  149. RSET_PCMDMAC,
  150. RSET_PCMDMAS,
  151. RSET_RNG,
  152. RSET_MISC
  153. };
  154. #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
  155. #define RSET_DSL_SIZE 4096
  156. #define RSET_WDT_SIZE 12
  157. #define BCM_6338_RSET_SPI_SIZE 64
  158. #define BCM_6348_RSET_SPI_SIZE 64
  159. #define BCM_6358_RSET_SPI_SIZE 1804
  160. #define BCM_6368_RSET_SPI_SIZE 1804
  161. #define RSET_ENET_SIZE 2048
  162. #define RSET_ENETDMA_SIZE 2048
  163. #define RSET_ENETSW_SIZE 65536
  164. #define RSET_UART_SIZE 24
  165. #define RSET_UDC_SIZE 256
  166. #define RSET_OHCI_SIZE 256
  167. #define RSET_EHCI_SIZE 256
  168. #define RSET_USBD_SIZE 256
  169. #define RSET_USBDMA_SIZE 1280
  170. #define RSET_PCMCIA_SIZE 12
  171. #define RSET_M2M_SIZE 256
  172. #define RSET_ATM_SIZE 4096
  173. #define RSET_XTM_SIZE 10240
  174. #define RSET_XTMDMA_SIZE 256
  175. #define RSET_XTMDMAC_SIZE(chans) (16 * (chans))
  176. #define RSET_XTMDMAS_SIZE(chans) (16 * (chans))
  177. #define RSET_RNG_SIZE 20
  178. /*
  179. * 6328 register sets base address
  180. */
  181. #define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
  182. #define BCM_6328_PERF_BASE (0xb0000000)
  183. #define BCM_6328_TIMER_BASE (0xb0000040)
  184. #define BCM_6328_WDT_BASE (0xb000005c)
  185. #define BCM_6328_UART0_BASE (0xb0000100)
  186. #define BCM_6328_UART1_BASE (0xb0000120)
  187. #define BCM_6328_GPIO_BASE (0xb0000080)
  188. #define BCM_6328_SPI_BASE (0xdeadbeef)
  189. #define BCM_6328_UDC0_BASE (0xdeadbeef)
  190. #define BCM_6328_USBDMA_BASE (0xb000c000)
  191. #define BCM_6328_OHCI0_BASE (0xb0002600)
  192. #define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef)
  193. #define BCM_6328_USBH_PRIV_BASE (0xb0002700)
  194. #define BCM_6328_USBD_BASE (0xb0002400)
  195. #define BCM_6328_MPI_BASE (0xdeadbeef)
  196. #define BCM_6328_PCMCIA_BASE (0xdeadbeef)
  197. #define BCM_6328_PCIE_BASE (0xb0e40000)
  198. #define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef)
  199. #define BCM_6328_DSL_BASE (0xb0001900)
  200. #define BCM_6328_UBUS_BASE (0xdeadbeef)
  201. #define BCM_6328_ENET0_BASE (0xdeadbeef)
  202. #define BCM_6328_ENET1_BASE (0xdeadbeef)
  203. #define BCM_6328_ENETDMA_BASE (0xb000d800)
  204. #define BCM_6328_ENETDMAC_BASE (0xb000da00)
  205. #define BCM_6328_ENETDMAS_BASE (0xb000dc00)
  206. #define BCM_6328_ENETSW_BASE (0xb0e00000)
  207. #define BCM_6328_EHCI0_BASE (0xb0002500)
  208. #define BCM_6328_SDRAM_BASE (0xdeadbeef)
  209. #define BCM_6328_MEMC_BASE (0xdeadbeef)
  210. #define BCM_6328_DDR_BASE (0xb0003000)
  211. #define BCM_6328_M2M_BASE (0xdeadbeef)
  212. #define BCM_6328_ATM_BASE (0xdeadbeef)
  213. #define BCM_6328_XTM_BASE (0xdeadbeef)
  214. #define BCM_6328_XTMDMA_BASE (0xb000b800)
  215. #define BCM_6328_XTMDMAC_BASE (0xdeadbeef)
  216. #define BCM_6328_XTMDMAS_BASE (0xdeadbeef)
  217. #define BCM_6328_PCM_BASE (0xb000a800)
  218. #define BCM_6328_PCMDMA_BASE (0xdeadbeef)
  219. #define BCM_6328_PCMDMAC_BASE (0xdeadbeef)
  220. #define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
  221. #define BCM_6328_RNG_BASE (0xdeadbeef)
  222. #define BCM_6328_MISC_BASE (0xb0001800)
  223. /*
  224. * 6338 register sets base address
  225. */
  226. #define BCM_6338_DSL_LMEM_BASE (0xfff00000)
  227. #define BCM_6338_PERF_BASE (0xfffe0000)
  228. #define BCM_6338_BB_BASE (0xfffe0100)
  229. #define BCM_6338_TIMER_BASE (0xfffe0200)
  230. #define BCM_6338_WDT_BASE (0xfffe021c)
  231. #define BCM_6338_UART0_BASE (0xfffe0300)
  232. #define BCM_6338_UART1_BASE (0xdeadbeef)
  233. #define BCM_6338_GPIO_BASE (0xfffe0400)
  234. #define BCM_6338_SPI_BASE (0xfffe0c00)
  235. #define BCM_6338_UDC0_BASE (0xdeadbeef)
  236. #define BCM_6338_USBDMA_BASE (0xfffe2400)
  237. #define BCM_6338_OHCI0_BASE (0xdeadbeef)
  238. #define BCM_6338_OHCI_PRIV_BASE (0xfffe3000)
  239. #define BCM_6338_USBH_PRIV_BASE (0xdeadbeef)
  240. #define BCM_6338_USBD_BASE (0xdeadbeef)
  241. #define BCM_6338_MPI_BASE (0xfffe3160)
  242. #define BCM_6338_PCMCIA_BASE (0xdeadbeef)
  243. #define BCM_6338_PCIE_BASE (0xdeadbeef)
  244. #define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
  245. #define BCM_6338_DSL_BASE (0xfffe1000)
  246. #define BCM_6338_UBUS_BASE (0xdeadbeef)
  247. #define BCM_6338_ENET0_BASE (0xfffe2800)
  248. #define BCM_6338_ENET1_BASE (0xdeadbeef)
  249. #define BCM_6338_ENETDMA_BASE (0xfffe2400)
  250. #define BCM_6338_ENETDMAC_BASE (0xfffe2500)
  251. #define BCM_6338_ENETDMAS_BASE (0xfffe2600)
  252. #define BCM_6338_ENETSW_BASE (0xdeadbeef)
  253. #define BCM_6338_EHCI0_BASE (0xdeadbeef)
  254. #define BCM_6338_SDRAM_BASE (0xfffe3100)
  255. #define BCM_6338_MEMC_BASE (0xdeadbeef)
  256. #define BCM_6338_DDR_BASE (0xdeadbeef)
  257. #define BCM_6338_M2M_BASE (0xdeadbeef)
  258. #define BCM_6338_ATM_BASE (0xfffe2000)
  259. #define BCM_6338_XTM_BASE (0xdeadbeef)
  260. #define BCM_6338_XTMDMA_BASE (0xdeadbeef)
  261. #define BCM_6338_XTMDMAC_BASE (0xdeadbeef)
  262. #define BCM_6338_XTMDMAS_BASE (0xdeadbeef)
  263. #define BCM_6338_PCM_BASE (0xdeadbeef)
  264. #define BCM_6338_PCMDMA_BASE (0xdeadbeef)
  265. #define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
  266. #define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
  267. #define BCM_6338_RNG_BASE (0xdeadbeef)
  268. #define BCM_6338_MISC_BASE (0xdeadbeef)
  269. /*
  270. * 6345 register sets base address
  271. */
  272. #define BCM_6345_DSL_LMEM_BASE (0xfff00000)
  273. #define BCM_6345_PERF_BASE (0xfffe0000)
  274. #define BCM_6345_BB_BASE (0xfffe0100)
  275. #define BCM_6345_TIMER_BASE (0xfffe0200)
  276. #define BCM_6345_WDT_BASE (0xfffe021c)
  277. #define BCM_6345_UART0_BASE (0xfffe0300)
  278. #define BCM_6345_UART1_BASE (0xdeadbeef)
  279. #define BCM_6345_GPIO_BASE (0xfffe0400)
  280. #define BCM_6345_SPI_BASE (0xdeadbeef)
  281. #define BCM_6345_UDC0_BASE (0xdeadbeef)
  282. #define BCM_6345_USBDMA_BASE (0xfffe2800)
  283. #define BCM_6345_ENET0_BASE (0xfffe1800)
  284. #define BCM_6345_ENETDMA_BASE (0xfffe2800)
  285. #define BCM_6345_ENETDMAC_BASE (0xfffe2900)
  286. #define BCM_6345_ENETDMAS_BASE (0xfffe2a00)
  287. #define BCM_6345_ENETSW_BASE (0xdeadbeef)
  288. #define BCM_6345_PCMCIA_BASE (0xfffe2028)
  289. #define BCM_6345_MPI_BASE (0xfffe2000)
  290. #define BCM_6345_PCIE_BASE (0xdeadbeef)
  291. #define BCM_6345_OHCI0_BASE (0xfffe2100)
  292. #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
  293. #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
  294. #define BCM_6345_USBD_BASE (0xdeadbeef)
  295. #define BCM_6345_SDRAM_REGS_BASE (0xfffe2300)
  296. #define BCM_6345_DSL_BASE (0xdeadbeef)
  297. #define BCM_6345_UBUS_BASE (0xdeadbeef)
  298. #define BCM_6345_ENET1_BASE (0xdeadbeef)
  299. #define BCM_6345_EHCI0_BASE (0xdeadbeef)
  300. #define BCM_6345_SDRAM_BASE (0xfffe2300)
  301. #define BCM_6345_MEMC_BASE (0xdeadbeef)
  302. #define BCM_6345_DDR_BASE (0xdeadbeef)
  303. #define BCM_6345_M2M_BASE (0xdeadbeef)
  304. #define BCM_6345_ATM_BASE (0xfffe4000)
  305. #define BCM_6345_XTM_BASE (0xdeadbeef)
  306. #define BCM_6345_XTMDMA_BASE (0xdeadbeef)
  307. #define BCM_6345_XTMDMAC_BASE (0xdeadbeef)
  308. #define BCM_6345_XTMDMAS_BASE (0xdeadbeef)
  309. #define BCM_6345_PCM_BASE (0xdeadbeef)
  310. #define BCM_6345_PCMDMA_BASE (0xdeadbeef)
  311. #define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
  312. #define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
  313. #define BCM_6345_RNG_BASE (0xdeadbeef)
  314. #define BCM_6345_MISC_BASE (0xdeadbeef)
  315. /*
  316. * 6348 register sets base address
  317. */
  318. #define BCM_6348_DSL_LMEM_BASE (0xfff00000)
  319. #define BCM_6348_PERF_BASE (0xfffe0000)
  320. #define BCM_6348_TIMER_BASE (0xfffe0200)
  321. #define BCM_6348_WDT_BASE (0xfffe021c)
  322. #define BCM_6348_UART0_BASE (0xfffe0300)
  323. #define BCM_6348_UART1_BASE (0xdeadbeef)
  324. #define BCM_6348_GPIO_BASE (0xfffe0400)
  325. #define BCM_6348_SPI_BASE (0xfffe0c00)
  326. #define BCM_6348_UDC0_BASE (0xfffe1000)
  327. #define BCM_6348_USBDMA_BASE (0xdeadbeef)
  328. #define BCM_6348_OHCI0_BASE (0xfffe1b00)
  329. #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
  330. #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
  331. #define BCM_6348_USBD_BASE (0xdeadbeef)
  332. #define BCM_6348_MPI_BASE (0xfffe2000)
  333. #define BCM_6348_PCMCIA_BASE (0xfffe2054)
  334. #define BCM_6348_PCIE_BASE (0xdeadbeef)
  335. #define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
  336. #define BCM_6348_M2M_BASE (0xfffe2800)
  337. #define BCM_6348_DSL_BASE (0xfffe3000)
  338. #define BCM_6348_ENET0_BASE (0xfffe6000)
  339. #define BCM_6348_ENET1_BASE (0xfffe6800)
  340. #define BCM_6348_ENETDMA_BASE (0xfffe7000)
  341. #define BCM_6348_ENETDMAC_BASE (0xfffe7100)
  342. #define BCM_6348_ENETDMAS_BASE (0xfffe7200)
  343. #define BCM_6348_ENETSW_BASE (0xdeadbeef)
  344. #define BCM_6348_EHCI0_BASE (0xdeadbeef)
  345. #define BCM_6348_SDRAM_BASE (0xfffe2300)
  346. #define BCM_6348_MEMC_BASE (0xdeadbeef)
  347. #define BCM_6348_DDR_BASE (0xdeadbeef)
  348. #define BCM_6348_ATM_BASE (0xfffe4000)
  349. #define BCM_6348_XTM_BASE (0xdeadbeef)
  350. #define BCM_6348_XTMDMA_BASE (0xdeadbeef)
  351. #define BCM_6348_XTMDMAC_BASE (0xdeadbeef)
  352. #define BCM_6348_XTMDMAS_BASE (0xdeadbeef)
  353. #define BCM_6348_PCM_BASE (0xdeadbeef)
  354. #define BCM_6348_PCMDMA_BASE (0xdeadbeef)
  355. #define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
  356. #define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
  357. #define BCM_6348_RNG_BASE (0xdeadbeef)
  358. #define BCM_6348_MISC_BASE (0xdeadbeef)
  359. /*
  360. * 6358 register sets base address
  361. */
  362. #define BCM_6358_DSL_LMEM_BASE (0xfff00000)
  363. #define BCM_6358_PERF_BASE (0xfffe0000)
  364. #define BCM_6358_TIMER_BASE (0xfffe0040)
  365. #define BCM_6358_WDT_BASE (0xfffe005c)
  366. #define BCM_6358_UART0_BASE (0xfffe0100)
  367. #define BCM_6358_UART1_BASE (0xfffe0120)
  368. #define BCM_6358_GPIO_BASE (0xfffe0080)
  369. #define BCM_6358_SPI_BASE (0xfffe0800)
  370. #define BCM_6358_UDC0_BASE (0xfffe0800)
  371. #define BCM_6358_USBDMA_BASE (0xdeadbeef)
  372. #define BCM_6358_OHCI0_BASE (0xfffe1400)
  373. #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
  374. #define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
  375. #define BCM_6358_USBD_BASE (0xdeadbeef)
  376. #define BCM_6358_MPI_BASE (0xfffe1000)
  377. #define BCM_6358_PCMCIA_BASE (0xfffe1054)
  378. #define BCM_6358_PCIE_BASE (0xdeadbeef)
  379. #define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
  380. #define BCM_6358_M2M_BASE (0xdeadbeef)
  381. #define BCM_6358_DSL_BASE (0xfffe3000)
  382. #define BCM_6358_ENET0_BASE (0xfffe4000)
  383. #define BCM_6358_ENET1_BASE (0xfffe4800)
  384. #define BCM_6358_ENETDMA_BASE (0xfffe5000)
  385. #define BCM_6358_ENETDMAC_BASE (0xfffe5100)
  386. #define BCM_6358_ENETDMAS_BASE (0xfffe5200)
  387. #define BCM_6358_ENETSW_BASE (0xdeadbeef)
  388. #define BCM_6358_EHCI0_BASE (0xfffe1300)
  389. #define BCM_6358_SDRAM_BASE (0xdeadbeef)
  390. #define BCM_6358_MEMC_BASE (0xfffe1200)
  391. #define BCM_6358_DDR_BASE (0xfffe12a0)
  392. #define BCM_6358_ATM_BASE (0xfffe2000)
  393. #define BCM_6358_XTM_BASE (0xdeadbeef)
  394. #define BCM_6358_XTMDMA_BASE (0xdeadbeef)
  395. #define BCM_6358_XTMDMAC_BASE (0xdeadbeef)
  396. #define BCM_6358_XTMDMAS_BASE (0xdeadbeef)
  397. #define BCM_6358_PCM_BASE (0xfffe1600)
  398. #define BCM_6358_PCMDMA_BASE (0xfffe1800)
  399. #define BCM_6358_PCMDMAC_BASE (0xfffe1900)
  400. #define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
  401. #define BCM_6358_RNG_BASE (0xdeadbeef)
  402. #define BCM_6358_MISC_BASE (0xdeadbeef)
  403. /*
  404. * 6362 register sets base address
  405. */
  406. #define BCM_6362_DSL_LMEM_BASE (0xdeadbeef)
  407. #define BCM_6362_PERF_BASE (0xb0000000)
  408. #define BCM_6362_TIMER_BASE (0xb0000040)
  409. #define BCM_6362_WDT_BASE (0xb000005c)
  410. #define BCM_6362_UART0_BASE (0xb0000100)
  411. #define BCM_6362_UART1_BASE (0xb0000120)
  412. #define BCM_6362_GPIO_BASE (0xb0000080)
  413. #define BCM_6362_SPI_BASE (0xb0000800)
  414. #define BCM_6362_HSSPI_BASE (0xb0001000)
  415. #define BCM_6362_UDC0_BASE (0xdeadbeef)
  416. #define BCM_6362_USBDMA_BASE (0xb000c000)
  417. #define BCM_6362_OHCI0_BASE (0xb0002600)
  418. #define BCM_6362_OHCI_PRIV_BASE (0xdeadbeef)
  419. #define BCM_6362_USBH_PRIV_BASE (0xb0002700)
  420. #define BCM_6362_USBD_BASE (0xb0002400)
  421. #define BCM_6362_MPI_BASE (0xdeadbeef)
  422. #define BCM_6362_PCMCIA_BASE (0xdeadbeef)
  423. #define BCM_6362_PCIE_BASE (0xb0e40000)
  424. #define BCM_6362_SDRAM_REGS_BASE (0xdeadbeef)
  425. #define BCM_6362_DSL_BASE (0xdeadbeef)
  426. #define BCM_6362_UBUS_BASE (0xdeadbeef)
  427. #define BCM_6362_ENET0_BASE (0xdeadbeef)
  428. #define BCM_6362_ENET1_BASE (0xdeadbeef)
  429. #define BCM_6362_ENETDMA_BASE (0xb000d800)
  430. #define BCM_6362_ENETDMAC_BASE (0xb000da00)
  431. #define BCM_6362_ENETDMAS_BASE (0xb000dc00)
  432. #define BCM_6362_ENETSW_BASE (0xb0e00000)
  433. #define BCM_6362_EHCI0_BASE (0xb0002500)
  434. #define BCM_6362_SDRAM_BASE (0xdeadbeef)
  435. #define BCM_6362_MEMC_BASE (0xdeadbeef)
  436. #define BCM_6362_DDR_BASE (0xb0003000)
  437. #define BCM_6362_M2M_BASE (0xdeadbeef)
  438. #define BCM_6362_ATM_BASE (0xdeadbeef)
  439. #define BCM_6362_XTM_BASE (0xb0007800)
  440. #define BCM_6362_XTMDMA_BASE (0xb000b800)
  441. #define BCM_6362_XTMDMAC_BASE (0xdeadbeef)
  442. #define BCM_6362_XTMDMAS_BASE (0xdeadbeef)
  443. #define BCM_6362_PCM_BASE (0xb000a800)
  444. #define BCM_6362_PCMDMA_BASE (0xdeadbeef)
  445. #define BCM_6362_PCMDMAC_BASE (0xdeadbeef)
  446. #define BCM_6362_PCMDMAS_BASE (0xdeadbeef)
  447. #define BCM_6362_RNG_BASE (0xdeadbeef)
  448. #define BCM_6362_MISC_BASE (0xb0001800)
  449. #define BCM_6362_NAND_REG_BASE (0xb0000200)
  450. #define BCM_6362_NAND_CACHE_BASE (0xb0000600)
  451. #define BCM_6362_LED_BASE (0xb0001900)
  452. #define BCM_6362_IPSEC_BASE (0xb0002800)
  453. #define BCM_6362_IPSEC_DMA_BASE (0xb000d000)
  454. #define BCM_6362_WLAN_CHIPCOMMON_BASE (0xb0004000)
  455. #define BCM_6362_WLAN_D11_BASE (0xb0005000)
  456. #define BCM_6362_WLAN_SHIM_BASE (0xb0007000)
  457. /*
  458. * 6368 register sets base address
  459. */
  460. #define BCM_6368_DSL_LMEM_BASE (0xdeadbeef)
  461. #define BCM_6368_PERF_BASE (0xb0000000)
  462. #define BCM_6368_TIMER_BASE (0xb0000040)
  463. #define BCM_6368_WDT_BASE (0xb000005c)
  464. #define BCM_6368_UART0_BASE (0xb0000100)
  465. #define BCM_6368_UART1_BASE (0xb0000120)
  466. #define BCM_6368_GPIO_BASE (0xb0000080)
  467. #define BCM_6368_SPI_BASE (0xb0000800)
  468. #define BCM_6368_UDC0_BASE (0xdeadbeef)
  469. #define BCM_6368_USBDMA_BASE (0xb0004800)
  470. #define BCM_6368_OHCI0_BASE (0xb0001600)
  471. #define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)
  472. #define BCM_6368_USBH_PRIV_BASE (0xb0001700)
  473. #define BCM_6368_USBD_BASE (0xb0001400)
  474. #define BCM_6368_MPI_BASE (0xb0001000)
  475. #define BCM_6368_PCMCIA_BASE (0xb0001054)
  476. #define BCM_6368_PCIE_BASE (0xdeadbeef)
  477. #define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef)
  478. #define BCM_6368_M2M_BASE (0xdeadbeef)
  479. #define BCM_6368_DSL_BASE (0xdeadbeef)
  480. #define BCM_6368_ENET0_BASE (0xdeadbeef)
  481. #define BCM_6368_ENET1_BASE (0xdeadbeef)
  482. #define BCM_6368_ENETDMA_BASE (0xb0006800)
  483. #define BCM_6368_ENETDMAC_BASE (0xb0006a00)
  484. #define BCM_6368_ENETDMAS_BASE (0xb0006c00)
  485. #define BCM_6368_ENETSW_BASE (0xb0f00000)
  486. #define BCM_6368_EHCI0_BASE (0xb0001500)
  487. #define BCM_6368_SDRAM_BASE (0xdeadbeef)
  488. #define BCM_6368_MEMC_BASE (0xb0001200)
  489. #define BCM_6368_DDR_BASE (0xb0001280)
  490. #define BCM_6368_ATM_BASE (0xdeadbeef)
  491. #define BCM_6368_XTM_BASE (0xb0001800)
  492. #define BCM_6368_XTMDMA_BASE (0xb0005000)
  493. #define BCM_6368_XTMDMAC_BASE (0xb0005200)
  494. #define BCM_6368_XTMDMAS_BASE (0xb0005400)
  495. #define BCM_6368_PCM_BASE (0xb0004000)
  496. #define BCM_6368_PCMDMA_BASE (0xb0005800)
  497. #define BCM_6368_PCMDMAC_BASE (0xb0005a00)
  498. #define BCM_6368_PCMDMAS_BASE (0xb0005c00)
  499. #define BCM_6368_RNG_BASE (0xb0004180)
  500. #define BCM_6368_MISC_BASE (0xdeadbeef)
  501. extern const unsigned long *bcm63xx_regs_base;
  502. #define __GEN_RSET_BASE(__cpu, __rset) \
  503. case RSET_## __rset : \
  504. return BCM_## __cpu ##_## __rset ##_BASE;
  505. #define __GEN_RSET(__cpu) \
  506. switch (set) { \
  507. __GEN_RSET_BASE(__cpu, DSL_LMEM) \
  508. __GEN_RSET_BASE(__cpu, PERF) \
  509. __GEN_RSET_BASE(__cpu, TIMER) \
  510. __GEN_RSET_BASE(__cpu, WDT) \
  511. __GEN_RSET_BASE(__cpu, UART0) \
  512. __GEN_RSET_BASE(__cpu, UART1) \
  513. __GEN_RSET_BASE(__cpu, GPIO) \
  514. __GEN_RSET_BASE(__cpu, SPI) \
  515. __GEN_RSET_BASE(__cpu, UDC0) \
  516. __GEN_RSET_BASE(__cpu, OHCI0) \
  517. __GEN_RSET_BASE(__cpu, OHCI_PRIV) \
  518. __GEN_RSET_BASE(__cpu, USBH_PRIV) \
  519. __GEN_RSET_BASE(__cpu, USBD) \
  520. __GEN_RSET_BASE(__cpu, USBDMA) \
  521. __GEN_RSET_BASE(__cpu, MPI) \
  522. __GEN_RSET_BASE(__cpu, PCMCIA) \
  523. __GEN_RSET_BASE(__cpu, PCIE) \
  524. __GEN_RSET_BASE(__cpu, DSL) \
  525. __GEN_RSET_BASE(__cpu, ENET0) \
  526. __GEN_RSET_BASE(__cpu, ENET1) \
  527. __GEN_RSET_BASE(__cpu, ENETDMA) \
  528. __GEN_RSET_BASE(__cpu, ENETDMAC) \
  529. __GEN_RSET_BASE(__cpu, ENETDMAS) \
  530. __GEN_RSET_BASE(__cpu, ENETSW) \
  531. __GEN_RSET_BASE(__cpu, EHCI0) \
  532. __GEN_RSET_BASE(__cpu, SDRAM) \
  533. __GEN_RSET_BASE(__cpu, MEMC) \
  534. __GEN_RSET_BASE(__cpu, DDR) \
  535. __GEN_RSET_BASE(__cpu, M2M) \
  536. __GEN_RSET_BASE(__cpu, ATM) \
  537. __GEN_RSET_BASE(__cpu, XTM) \
  538. __GEN_RSET_BASE(__cpu, XTMDMA) \
  539. __GEN_RSET_BASE(__cpu, XTMDMAC) \
  540. __GEN_RSET_BASE(__cpu, XTMDMAS) \
  541. __GEN_RSET_BASE(__cpu, PCM) \
  542. __GEN_RSET_BASE(__cpu, PCMDMA) \
  543. __GEN_RSET_BASE(__cpu, PCMDMAC) \
  544. __GEN_RSET_BASE(__cpu, PCMDMAS) \
  545. __GEN_RSET_BASE(__cpu, RNG) \
  546. __GEN_RSET_BASE(__cpu, MISC) \
  547. }
  548. #define __GEN_CPU_REGS_TABLE(__cpu) \
  549. [RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \
  550. [RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \
  551. [RSET_TIMER] = BCM_## __cpu ##_TIMER_BASE, \
  552. [RSET_WDT] = BCM_## __cpu ##_WDT_BASE, \
  553. [RSET_UART0] = BCM_## __cpu ##_UART0_BASE, \
  554. [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
  555. [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
  556. [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
  557. [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
  558. [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
  559. [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
  560. [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \
  561. [RSET_USBD] = BCM_## __cpu ##_USBD_BASE, \
  562. [RSET_USBDMA] = BCM_## __cpu ##_USBDMA_BASE, \
  563. [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \
  564. [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \
  565. [RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \
  566. [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \
  567. [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \
  568. [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \
  569. [RSET_ENETDMA] = BCM_## __cpu ##_ENETDMA_BASE, \
  570. [RSET_ENETDMAC] = BCM_## __cpu ##_ENETDMAC_BASE, \
  571. [RSET_ENETDMAS] = BCM_## __cpu ##_ENETDMAS_BASE, \
  572. [RSET_ENETSW] = BCM_## __cpu ##_ENETSW_BASE, \
  573. [RSET_EHCI0] = BCM_## __cpu ##_EHCI0_BASE, \
  574. [RSET_SDRAM] = BCM_## __cpu ##_SDRAM_BASE, \
  575. [RSET_MEMC] = BCM_## __cpu ##_MEMC_BASE, \
  576. [RSET_DDR] = BCM_## __cpu ##_DDR_BASE, \
  577. [RSET_M2M] = BCM_## __cpu ##_M2M_BASE, \
  578. [RSET_ATM] = BCM_## __cpu ##_ATM_BASE, \
  579. [RSET_XTM] = BCM_## __cpu ##_XTM_BASE, \
  580. [RSET_XTMDMA] = BCM_## __cpu ##_XTMDMA_BASE, \
  581. [RSET_XTMDMAC] = BCM_## __cpu ##_XTMDMAC_BASE, \
  582. [RSET_XTMDMAS] = BCM_## __cpu ##_XTMDMAS_BASE, \
  583. [RSET_PCM] = BCM_## __cpu ##_PCM_BASE, \
  584. [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \
  585. [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \
  586. [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
  587. [RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \
  588. [RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \
  589. static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
  590. {
  591. #ifdef BCMCPU_RUNTIME_DETECT
  592. return bcm63xx_regs_base[set];
  593. #else
  594. #ifdef CONFIG_BCM63XX_CPU_6328
  595. __GEN_RSET(6328)
  596. #endif
  597. #ifdef CONFIG_BCM63XX_CPU_6338
  598. __GEN_RSET(6338)
  599. #endif
  600. #ifdef CONFIG_BCM63XX_CPU_6345
  601. __GEN_RSET(6345)
  602. #endif
  603. #ifdef CONFIG_BCM63XX_CPU_6348
  604. __GEN_RSET(6348)
  605. #endif
  606. #ifdef CONFIG_BCM63XX_CPU_6358
  607. __GEN_RSET(6358)
  608. #endif
  609. #ifdef CONFIG_BCM63XX_CPU_6362
  610. __GEN_RSET(6362)
  611. #endif
  612. #ifdef CONFIG_BCM63XX_CPU_6368
  613. __GEN_RSET(6368)
  614. #endif
  615. #endif
  616. /* unreached */
  617. return 0;
  618. }
  619. /*
  620. * IRQ number changes across CPU too
  621. */
  622. enum bcm63xx_irq {
  623. IRQ_TIMER = 0,
  624. IRQ_SPI,
  625. IRQ_UART0,
  626. IRQ_UART1,
  627. IRQ_DSL,
  628. IRQ_ENET0,
  629. IRQ_ENET1,
  630. IRQ_ENET_PHY,
  631. IRQ_OHCI0,
  632. IRQ_EHCI0,
  633. IRQ_USBD,
  634. IRQ_USBD_RXDMA0,
  635. IRQ_USBD_TXDMA0,
  636. IRQ_USBD_RXDMA1,
  637. IRQ_USBD_TXDMA1,
  638. IRQ_USBD_RXDMA2,
  639. IRQ_USBD_TXDMA2,
  640. IRQ_ENET0_RXDMA,
  641. IRQ_ENET0_TXDMA,
  642. IRQ_ENET1_RXDMA,
  643. IRQ_ENET1_TXDMA,
  644. IRQ_PCI,
  645. IRQ_PCMCIA,
  646. IRQ_ATM,
  647. IRQ_ENETSW_RXDMA0,
  648. IRQ_ENETSW_RXDMA1,
  649. IRQ_ENETSW_RXDMA2,
  650. IRQ_ENETSW_RXDMA3,
  651. IRQ_ENETSW_TXDMA0,
  652. IRQ_ENETSW_TXDMA1,
  653. IRQ_ENETSW_TXDMA2,
  654. IRQ_ENETSW_TXDMA3,
  655. IRQ_XTM,
  656. IRQ_XTM_DMA0,
  657. };
  658. /*
  659. * 6328 irqs
  660. */
  661. #define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
  662. #define BCM_6328_TIMER_IRQ (IRQ_INTERNAL_BASE + 31)
  663. #define BCM_6328_SPI_IRQ 0
  664. #define BCM_6328_UART0_IRQ (IRQ_INTERNAL_BASE + 28)
  665. #define BCM_6328_UART1_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)
  666. #define BCM_6328_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
  667. #define BCM_6328_UDC0_IRQ 0
  668. #define BCM_6328_ENET0_IRQ 0
  669. #define BCM_6328_ENET1_IRQ 0
  670. #define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
  671. #define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9)
  672. #define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10)
  673. #define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4)
  674. #define BCM_6328_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 5)
  675. #define BCM_6328_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 6)
  676. #define BCM_6328_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 7)
  677. #define BCM_6328_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 8)
  678. #define BCM_6328_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 9)
  679. #define BCM_6328_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 10)
  680. #define BCM_6328_PCMCIA_IRQ 0
  681. #define BCM_6328_ENET0_RXDMA_IRQ 0
  682. #define BCM_6328_ENET0_TXDMA_IRQ 0
  683. #define BCM_6328_ENET1_RXDMA_IRQ 0
  684. #define BCM_6328_ENET1_TXDMA_IRQ 0
  685. #define BCM_6328_PCI_IRQ (IRQ_INTERNAL_BASE + 23)
  686. #define BCM_6328_ATM_IRQ 0
  687. #define BCM_6328_ENETSW_RXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 0)
  688. #define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1)
  689. #define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2)
  690. #define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3)
  691. #define BCM_6328_ENETSW_TXDMA0_IRQ 0
  692. #define BCM_6328_ENETSW_TXDMA1_IRQ 0
  693. #define BCM_6328_ENETSW_TXDMA2_IRQ 0
  694. #define BCM_6328_ENETSW_TXDMA3_IRQ 0
  695. #define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31)
  696. #define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11)
  697. #define BCM_6328_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2)
  698. #define BCM_6328_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3)
  699. #define BCM_6328_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24)
  700. #define BCM_6328_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25)
  701. #define BCM_6328_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26)
  702. #define BCM_6328_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27)
  703. /*
  704. * 6338 irqs
  705. */
  706. #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
  707. #define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
  708. #define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
  709. #define BCM_6338_UART1_IRQ 0
  710. #define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
  711. #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
  712. #define BCM_6338_ENET1_IRQ 0
  713. #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
  714. #define BCM_6338_OHCI0_IRQ 0
  715. #define BCM_6338_EHCI0_IRQ 0
  716. #define BCM_6338_USBD_IRQ 0
  717. #define BCM_6338_USBD_RXDMA0_IRQ 0
  718. #define BCM_6338_USBD_TXDMA0_IRQ 0
  719. #define BCM_6338_USBD_RXDMA1_IRQ 0
  720. #define BCM_6338_USBD_TXDMA1_IRQ 0
  721. #define BCM_6338_USBD_RXDMA2_IRQ 0
  722. #define BCM_6338_USBD_TXDMA2_IRQ 0
  723. #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
  724. #define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
  725. #define BCM_6338_ENET1_RXDMA_IRQ 0
  726. #define BCM_6338_ENET1_TXDMA_IRQ 0
  727. #define BCM_6338_PCI_IRQ 0
  728. #define BCM_6338_PCMCIA_IRQ 0
  729. #define BCM_6338_ATM_IRQ 0
  730. #define BCM_6338_ENETSW_RXDMA0_IRQ 0
  731. #define BCM_6338_ENETSW_RXDMA1_IRQ 0
  732. #define BCM_6338_ENETSW_RXDMA2_IRQ 0
  733. #define BCM_6338_ENETSW_RXDMA3_IRQ 0
  734. #define BCM_6338_ENETSW_TXDMA0_IRQ 0
  735. #define BCM_6338_ENETSW_TXDMA1_IRQ 0
  736. #define BCM_6338_ENETSW_TXDMA2_IRQ 0
  737. #define BCM_6338_ENETSW_TXDMA3_IRQ 0
  738. #define BCM_6338_XTM_IRQ 0
  739. #define BCM_6338_XTM_DMA0_IRQ 0
  740. /*
  741. * 6345 irqs
  742. */
  743. #define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
  744. #define BCM_6345_SPI_IRQ 0
  745. #define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
  746. #define BCM_6345_UART1_IRQ 0
  747. #define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
  748. #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
  749. #define BCM_6345_ENET1_IRQ 0
  750. #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
  751. #define BCM_6345_OHCI0_IRQ 0
  752. #define BCM_6345_EHCI0_IRQ 0
  753. #define BCM_6345_USBD_IRQ 0
  754. #define BCM_6345_USBD_RXDMA0_IRQ 0
  755. #define BCM_6345_USBD_TXDMA0_IRQ 0
  756. #define BCM_6345_USBD_RXDMA1_IRQ 0
  757. #define BCM_6345_USBD_TXDMA1_IRQ 0
  758. #define BCM_6345_USBD_RXDMA2_IRQ 0
  759. #define BCM_6345_USBD_TXDMA2_IRQ 0
  760. #define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
  761. #define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)
  762. #define BCM_6345_ENET1_RXDMA_IRQ 0
  763. #define BCM_6345_ENET1_TXDMA_IRQ 0
  764. #define BCM_6345_PCI_IRQ 0
  765. #define BCM_6345_PCMCIA_IRQ 0
  766. #define BCM_6345_ATM_IRQ 0
  767. #define BCM_6345_ENETSW_RXDMA0_IRQ 0
  768. #define BCM_6345_ENETSW_RXDMA1_IRQ 0
  769. #define BCM_6345_ENETSW_RXDMA2_IRQ 0
  770. #define BCM_6345_ENETSW_RXDMA3_IRQ 0
  771. #define BCM_6345_ENETSW_TXDMA0_IRQ 0
  772. #define BCM_6345_ENETSW_TXDMA1_IRQ 0
  773. #define BCM_6345_ENETSW_TXDMA2_IRQ 0
  774. #define BCM_6345_ENETSW_TXDMA3_IRQ 0
  775. #define BCM_6345_XTM_IRQ 0
  776. #define BCM_6345_XTM_DMA0_IRQ 0
  777. /*
  778. * 6348 irqs
  779. */
  780. #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
  781. #define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
  782. #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
  783. #define BCM_6348_UART1_IRQ 0
  784. #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
  785. #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
  786. #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
  787. #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
  788. #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
  789. #define BCM_6348_EHCI0_IRQ 0
  790. #define BCM_6348_USBD_IRQ 0
  791. #define BCM_6348_USBD_RXDMA0_IRQ 0
  792. #define BCM_6348_USBD_TXDMA0_IRQ 0
  793. #define BCM_6348_USBD_RXDMA1_IRQ 0
  794. #define BCM_6348_USBD_TXDMA1_IRQ 0
  795. #define BCM_6348_USBD_RXDMA2_IRQ 0
  796. #define BCM_6348_USBD_TXDMA2_IRQ 0
  797. #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
  798. #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
  799. #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
  800. #define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
  801. #define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
  802. #define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
  803. #define BCM_6348_ATM_IRQ (IRQ_INTERNAL_BASE + 5)
  804. #define BCM_6348_ENETSW_RXDMA0_IRQ 0
  805. #define BCM_6348_ENETSW_RXDMA1_IRQ 0
  806. #define BCM_6348_ENETSW_RXDMA2_IRQ 0
  807. #define BCM_6348_ENETSW_RXDMA3_IRQ 0
  808. #define BCM_6348_ENETSW_TXDMA0_IRQ 0
  809. #define BCM_6348_ENETSW_TXDMA1_IRQ 0
  810. #define BCM_6348_ENETSW_TXDMA2_IRQ 0
  811. #define BCM_6348_ENETSW_TXDMA3_IRQ 0
  812. #define BCM_6348_XTM_IRQ 0
  813. #define BCM_6348_XTM_DMA0_IRQ 0
  814. /*
  815. * 6358 irqs
  816. */
  817. #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
  818. #define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
  819. #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
  820. #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
  821. #define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
  822. #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
  823. #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
  824. #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
  825. #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
  826. #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
  827. #define BCM_6358_USBD_IRQ 0
  828. #define BCM_6358_USBD_RXDMA0_IRQ 0
  829. #define BCM_6358_USBD_TXDMA0_IRQ 0
  830. #define BCM_6358_USBD_RXDMA1_IRQ 0
  831. #define BCM_6358_USBD_TXDMA1_IRQ 0
  832. #define BCM_6358_USBD_RXDMA2_IRQ 0
  833. #define BCM_6358_USBD_TXDMA2_IRQ 0
  834. #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
  835. #define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
  836. #define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
  837. #define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
  838. #define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
  839. #define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
  840. #define BCM_6358_ATM_IRQ (IRQ_INTERNAL_BASE + 19)
  841. #define BCM_6358_ENETSW_RXDMA0_IRQ 0
  842. #define BCM_6358_ENETSW_RXDMA1_IRQ 0
  843. #define BCM_6358_ENETSW_RXDMA2_IRQ 0
  844. #define BCM_6358_ENETSW_RXDMA3_IRQ 0
  845. #define BCM_6358_ENETSW_TXDMA0_IRQ 0
  846. #define BCM_6358_ENETSW_TXDMA1_IRQ 0
  847. #define BCM_6358_ENETSW_TXDMA2_IRQ 0
  848. #define BCM_6358_ENETSW_TXDMA3_IRQ 0
  849. #define BCM_6358_XTM_IRQ 0
  850. #define BCM_6358_XTM_DMA0_IRQ 0
  851. #define BCM_6358_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 23)
  852. #define BCM_6358_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 24)
  853. #define BCM_6358_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)
  854. #define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)
  855. #define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
  856. #define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
  857. /*
  858. * 6362 irqs
  859. */
  860. #define BCM_6362_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
  861. #define BCM_6362_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
  862. #define BCM_6362_SPI_IRQ (IRQ_INTERNAL_BASE + 2)
  863. #define BCM_6362_UART0_IRQ (IRQ_INTERNAL_BASE + 3)
  864. #define BCM_6362_UART1_IRQ (IRQ_INTERNAL_BASE + 4)
  865. #define BCM_6362_DSL_IRQ (IRQ_INTERNAL_BASE + 28)
  866. #define BCM_6362_UDC0_IRQ 0
  867. #define BCM_6362_ENET0_IRQ 0
  868. #define BCM_6362_ENET1_IRQ 0
  869. #define BCM_6362_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 14)
  870. #define BCM_6362_HSSPI_IRQ (IRQ_INTERNAL_BASE + 5)
  871. #define BCM_6362_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
  872. #define BCM_6362_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
  873. #define BCM_6362_USBD_IRQ (IRQ_INTERNAL_BASE + 11)
  874. #define BCM_6362_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 20)
  875. #define BCM_6362_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 21)
  876. #define BCM_6362_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 22)
  877. #define BCM_6362_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 23)
  878. #define BCM_6362_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 24)
  879. #define BCM_6362_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 25)
  880. #define BCM_6362_PCMCIA_IRQ 0
  881. #define BCM_6362_ENET0_RXDMA_IRQ 0
  882. #define BCM_6362_ENET0_TXDMA_IRQ 0
  883. #define BCM_6362_ENET1_RXDMA_IRQ 0
  884. #define BCM_6362_ENET1_TXDMA_IRQ 0
  885. #define BCM_6362_PCI_IRQ (IRQ_INTERNAL_BASE + 30)
  886. #define BCM_6362_ATM_IRQ 0
  887. #define BCM_6362_ENETSW_RXDMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 0)
  888. #define BCM_6362_ENETSW_RXDMA1_IRQ (BCM_6362_HIGH_IRQ_BASE + 1)
  889. #define BCM_6362_ENETSW_RXDMA2_IRQ (BCM_6362_HIGH_IRQ_BASE + 2)
  890. #define BCM_6362_ENETSW_RXDMA3_IRQ (BCM_6362_HIGH_IRQ_BASE + 3)
  891. #define BCM_6362_ENETSW_TXDMA0_IRQ 0
  892. #define BCM_6362_ENETSW_TXDMA1_IRQ 0
  893. #define BCM_6362_ENETSW_TXDMA2_IRQ 0
  894. #define BCM_6362_ENETSW_TXDMA3_IRQ 0
  895. #define BCM_6362_XTM_IRQ 0
  896. #define BCM_6362_XTM_DMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 12)
  897. #define BCM_6362_RING_OSC_IRQ (IRQ_INTERNAL_BASE + 1)
  898. #define BCM_6362_WLAN_GPIO_IRQ (IRQ_INTERNAL_BASE + 6)
  899. #define BCM_6362_WLAN_IRQ (IRQ_INTERNAL_BASE + 7)
  900. #define BCM_6362_IPSEC_IRQ (IRQ_INTERNAL_BASE + 8)
  901. #define BCM_6362_NAND_IRQ (IRQ_INTERNAL_BASE + 12)
  902. #define BCM_6362_PCM_IRQ (IRQ_INTERNAL_BASE + 13)
  903. #define BCM_6362_DG_IRQ (IRQ_INTERNAL_BASE + 15)
  904. #define BCM_6362_EPHY_ENERGY0_IRQ (IRQ_INTERNAL_BASE + 16)
  905. #define BCM_6362_EPHY_ENERGY1_IRQ (IRQ_INTERNAL_BASE + 17)
  906. #define BCM_6362_EPHY_ENERGY2_IRQ (IRQ_INTERNAL_BASE + 18)
  907. #define BCM_6362_EPHY_ENERGY3_IRQ (IRQ_INTERNAL_BASE + 19)
  908. #define BCM_6362_IPSEC_DMA0_IRQ (IRQ_INTERNAL_BASE + 26)
  909. #define BCM_6362_IPSEC_DMA1_IRQ (IRQ_INTERNAL_BASE + 27)
  910. #define BCM_6362_FAP0_IRQ (IRQ_INTERNAL_BASE + 29)
  911. #define BCM_6362_PCM_DMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 4)
  912. #define BCM_6362_PCM_DMA1_IRQ (BCM_6362_HIGH_IRQ_BASE + 5)
  913. #define BCM_6362_DECT0_IRQ (BCM_6362_HIGH_IRQ_BASE + 6)
  914. #define BCM_6362_DECT1_IRQ (BCM_6362_HIGH_IRQ_BASE + 7)
  915. #define BCM_6362_EXT_IRQ0 (BCM_6362_HIGH_IRQ_BASE + 8)
  916. #define BCM_6362_EXT_IRQ1 (BCM_6362_HIGH_IRQ_BASE + 9)
  917. #define BCM_6362_EXT_IRQ2 (BCM_6362_HIGH_IRQ_BASE + 10)
  918. #define BCM_6362_EXT_IRQ3 (BCM_6362_HIGH_IRQ_BASE + 11)
  919. /*
  920. * 6368 irqs
  921. */
  922. #define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
  923. #define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
  924. #define BCM_6368_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
  925. #define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
  926. #define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
  927. #define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
  928. #define BCM_6368_ENET0_IRQ 0
  929. #define BCM_6368_ENET1_IRQ 0
  930. #define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
  931. #define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
  932. #define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
  933. #define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8)
  934. #define BCM_6368_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 26)
  935. #define BCM_6368_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 27)
  936. #define BCM_6368_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 28)
  937. #define BCM_6368_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 29)
  938. #define BCM_6368_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 30)
  939. #define BCM_6368_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 31)
  940. #define BCM_6368_PCMCIA_IRQ 0
  941. #define BCM_6368_ENET0_RXDMA_IRQ 0
  942. #define BCM_6368_ENET0_TXDMA_IRQ 0
  943. #define BCM_6368_ENET1_RXDMA_IRQ 0
  944. #define BCM_6368_ENET1_TXDMA_IRQ 0
  945. #define BCM_6368_PCI_IRQ (IRQ_INTERNAL_BASE + 13)
  946. #define BCM_6368_ATM_IRQ 0
  947. #define BCM_6368_ENETSW_RXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 0)
  948. #define BCM_6368_ENETSW_RXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 1)
  949. #define BCM_6368_ENETSW_RXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 2)
  950. #define BCM_6368_ENETSW_RXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 3)
  951. #define BCM_6368_ENETSW_TXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 4)
  952. #define BCM_6368_ENETSW_TXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 5)
  953. #define BCM_6368_ENETSW_TXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 6)
  954. #define BCM_6368_ENETSW_TXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 7)
  955. #define BCM_6368_XTM_IRQ (IRQ_INTERNAL_BASE + 11)
  956. #define BCM_6368_XTM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 8)
  957. #define BCM_6368_PCM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 30)
  958. #define BCM_6368_PCM_DMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 31)
  959. #define BCM_6368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 20)
  960. #define BCM_6368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 21)
  961. #define BCM_6368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 22)
  962. #define BCM_6368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 23)
  963. #define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24)
  964. #define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25)
  965. extern const int *bcm63xx_irqs;
  966. #define __GEN_CPU_IRQ_TABLE(__cpu) \
  967. [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \
  968. [IRQ_SPI] = BCM_## __cpu ##_SPI_IRQ, \
  969. [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \
  970. [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \
  971. [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \
  972. [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
  973. [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
  974. [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
  975. [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
  976. [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
  977. [IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \
  978. [IRQ_USBD_RXDMA0] = BCM_## __cpu ##_USBD_RXDMA0_IRQ, \
  979. [IRQ_USBD_TXDMA0] = BCM_## __cpu ##_USBD_TXDMA0_IRQ, \
  980. [IRQ_USBD_RXDMA1] = BCM_## __cpu ##_USBD_RXDMA1_IRQ, \
  981. [IRQ_USBD_TXDMA1] = BCM_## __cpu ##_USBD_TXDMA1_IRQ, \
  982. [IRQ_USBD_RXDMA2] = BCM_## __cpu ##_USBD_RXDMA2_IRQ, \
  983. [IRQ_USBD_TXDMA2] = BCM_## __cpu ##_USBD_TXDMA2_IRQ, \
  984. [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \
  985. [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \
  986. [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \
  987. [IRQ_ENET1_TXDMA] = BCM_## __cpu ##_ENET1_TXDMA_IRQ, \
  988. [IRQ_PCI] = BCM_## __cpu ##_PCI_IRQ, \
  989. [IRQ_PCMCIA] = BCM_## __cpu ##_PCMCIA_IRQ, \
  990. [IRQ_ATM] = BCM_## __cpu ##_ATM_IRQ, \
  991. [IRQ_ENETSW_RXDMA0] = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ, \
  992. [IRQ_ENETSW_RXDMA1] = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ, \
  993. [IRQ_ENETSW_RXDMA2] = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ, \
  994. [IRQ_ENETSW_RXDMA3] = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ, \
  995. [IRQ_ENETSW_TXDMA0] = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ, \
  996. [IRQ_ENETSW_TXDMA1] = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ, \
  997. [IRQ_ENETSW_TXDMA2] = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ, \
  998. [IRQ_ENETSW_TXDMA3] = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ, \
  999. [IRQ_XTM] = BCM_## __cpu ##_XTM_IRQ, \
  1000. [IRQ_XTM_DMA0] = BCM_## __cpu ##_XTM_DMA0_IRQ, \
  1001. static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
  1002. {
  1003. return bcm63xx_irqs[irq];
  1004. }
  1005. /*
  1006. * return installed memory size
  1007. */
  1008. unsigned int bcm63xx_get_memory_size(void);
  1009. void bcm63xx_machine_halt(void);
  1010. void bcm63xx_machine_reboot(void);
  1011. #endif /* !BCM63XX_CPU_H_ */