rtsm_ve-aemv8a.dts 3.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159
  1. /*
  2. * ARM Ltd. Fast Models
  3. *
  4. * Architecture Envelope Model (AEM) ARMv8-A
  5. * ARMAEMv8AMPCT
  6. *
  7. * RTSM_VE_AEMv8A.lisa
  8. */
  9. /dts-v1/;
  10. /memreserve/ 0x80000000 0x00010000;
  11. / {
  12. model = "RTSM_VE_AEMv8A";
  13. compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress";
  14. interrupt-parent = <&gic>;
  15. #address-cells = <2>;
  16. #size-cells = <2>;
  17. chosen { };
  18. aliases {
  19. serial0 = &v2m_serial0;
  20. serial1 = &v2m_serial1;
  21. serial2 = &v2m_serial2;
  22. serial3 = &v2m_serial3;
  23. };
  24. cpus {
  25. #address-cells = <2>;
  26. #size-cells = <0>;
  27. cpu@0 {
  28. device_type = "cpu";
  29. compatible = "arm,armv8";
  30. reg = <0x0 0x0>;
  31. enable-method = "spin-table";
  32. cpu-release-addr = <0x0 0x8000fff8>;
  33. };
  34. cpu@1 {
  35. device_type = "cpu";
  36. compatible = "arm,armv8";
  37. reg = <0x0 0x1>;
  38. enable-method = "spin-table";
  39. cpu-release-addr = <0x0 0x8000fff8>;
  40. };
  41. cpu@2 {
  42. device_type = "cpu";
  43. compatible = "arm,armv8";
  44. reg = <0x0 0x2>;
  45. enable-method = "spin-table";
  46. cpu-release-addr = <0x0 0x8000fff8>;
  47. };
  48. cpu@3 {
  49. device_type = "cpu";
  50. compatible = "arm,armv8";
  51. reg = <0x0 0x3>;
  52. enable-method = "spin-table";
  53. cpu-release-addr = <0x0 0x8000fff8>;
  54. };
  55. };
  56. memory@80000000 {
  57. device_type = "memory";
  58. reg = <0x00000000 0x80000000 0 0x80000000>,
  59. <0x00000008 0x80000000 0 0x80000000>;
  60. };
  61. gic: interrupt-controller@2c001000 {
  62. compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  63. #interrupt-cells = <3>;
  64. #address-cells = <0>;
  65. interrupt-controller;
  66. reg = <0x0 0x2c001000 0 0x1000>,
  67. <0x0 0x2c002000 0 0x1000>,
  68. <0x0 0x2c004000 0 0x2000>,
  69. <0x0 0x2c006000 0 0x2000>;
  70. interrupts = <1 9 0xf04>;
  71. };
  72. timer {
  73. compatible = "arm,armv8-timer";
  74. interrupts = <1 13 0xff01>,
  75. <1 14 0xff01>,
  76. <1 11 0xff01>,
  77. <1 10 0xff01>;
  78. clock-frequency = <100000000>;
  79. };
  80. pmu {
  81. compatible = "arm,armv8-pmuv3";
  82. interrupts = <0 60 4>,
  83. <0 61 4>,
  84. <0 62 4>,
  85. <0 63 4>;
  86. };
  87. smb {
  88. compatible = "simple-bus";
  89. #address-cells = <2>;
  90. #size-cells = <1>;
  91. ranges = <0 0 0 0x08000000 0x04000000>,
  92. <1 0 0 0x14000000 0x04000000>,
  93. <2 0 0 0x18000000 0x04000000>,
  94. <3 0 0 0x1c000000 0x04000000>,
  95. <4 0 0 0x0c000000 0x04000000>,
  96. <5 0 0 0x10000000 0x04000000>;
  97. #interrupt-cells = <1>;
  98. interrupt-map-mask = <0 0 63>;
  99. interrupt-map = <0 0 0 &gic 0 0 4>,
  100. <0 0 1 &gic 0 1 4>,
  101. <0 0 2 &gic 0 2 4>,
  102. <0 0 3 &gic 0 3 4>,
  103. <0 0 4 &gic 0 4 4>,
  104. <0 0 5 &gic 0 5 4>,
  105. <0 0 6 &gic 0 6 4>,
  106. <0 0 7 &gic 0 7 4>,
  107. <0 0 8 &gic 0 8 4>,
  108. <0 0 9 &gic 0 9 4>,
  109. <0 0 10 &gic 0 10 4>,
  110. <0 0 11 &gic 0 11 4>,
  111. <0 0 12 &gic 0 12 4>,
  112. <0 0 13 &gic 0 13 4>,
  113. <0 0 14 &gic 0 14 4>,
  114. <0 0 15 &gic 0 15 4>,
  115. <0 0 16 &gic 0 16 4>,
  116. <0 0 17 &gic 0 17 4>,
  117. <0 0 18 &gic 0 18 4>,
  118. <0 0 19 &gic 0 19 4>,
  119. <0 0 20 &gic 0 20 4>,
  120. <0 0 21 &gic 0 21 4>,
  121. <0 0 22 &gic 0 22 4>,
  122. <0 0 23 &gic 0 23 4>,
  123. <0 0 24 &gic 0 24 4>,
  124. <0 0 25 &gic 0 25 4>,
  125. <0 0 26 &gic 0 26 4>,
  126. <0 0 27 &gic 0 27 4>,
  127. <0 0 28 &gic 0 28 4>,
  128. <0 0 29 &gic 0 29 4>,
  129. <0 0 30 &gic 0 30 4>,
  130. <0 0 31 &gic 0 31 4>,
  131. <0 0 32 &gic 0 32 4>,
  132. <0 0 33 &gic 0 33 4>,
  133. <0 0 34 &gic 0 34 4>,
  134. <0 0 35 &gic 0 35 4>,
  135. <0 0 36 &gic 0 36 4>,
  136. <0 0 37 &gic 0 37 4>,
  137. <0 0 38 &gic 0 38 4>,
  138. <0 0 39 &gic 0 39 4>,
  139. <0 0 40 &gic 0 40 4>,
  140. <0 0 41 &gic 0 41 4>,
  141. <0 0 42 &gic 0 42 4>;
  142. /include/ "rtsm_ve-motherboard.dtsi"
  143. };
  144. };