dma-mapping.c 50 KB

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  1. /*
  2. * linux/arch/arm/mm/dma-mapping.c
  3. *
  4. * Copyright (C) 2000-2004 Russell King
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * DMA uncached mapping support.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/mm.h>
  14. #include <linux/gfp.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/init.h>
  18. #include <linux/device.h>
  19. #include <linux/dma-mapping.h>
  20. #include <linux/dma-contiguous.h>
  21. #include <linux/highmem.h>
  22. #include <linux/memblock.h>
  23. #include <linux/slab.h>
  24. #include <linux/iommu.h>
  25. #include <linux/io.h>
  26. #include <linux/vmalloc.h>
  27. #include <linux/sizes.h>
  28. #include <asm/memory.h>
  29. #include <asm/highmem.h>
  30. #include <asm/cacheflush.h>
  31. #include <asm/tlbflush.h>
  32. #include <asm/mach/arch.h>
  33. #include <asm/dma-iommu.h>
  34. #include <asm/mach/map.h>
  35. #include <asm/system_info.h>
  36. #include <asm/dma-contiguous.h>
  37. #include "mm.h"
  38. /*
  39. * The DMA API is built upon the notion of "buffer ownership". A buffer
  40. * is either exclusively owned by the CPU (and therefore may be accessed
  41. * by it) or exclusively owned by the DMA device. These helper functions
  42. * represent the transitions between these two ownership states.
  43. *
  44. * Note, however, that on later ARMs, this notion does not work due to
  45. * speculative prefetches. We model our approach on the assumption that
  46. * the CPU does do speculative prefetches, which means we clean caches
  47. * before transfers and delay cache invalidation until transfer completion.
  48. *
  49. */
  50. static void __dma_page_cpu_to_dev(struct page *, unsigned long,
  51. size_t, enum dma_data_direction);
  52. static void __dma_page_dev_to_cpu(struct page *, unsigned long,
  53. size_t, enum dma_data_direction);
  54. /**
  55. * arm_dma_map_page - map a portion of a page for streaming DMA
  56. * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
  57. * @page: page that buffer resides in
  58. * @offset: offset into page for start of buffer
  59. * @size: size of buffer to map
  60. * @dir: DMA transfer direction
  61. *
  62. * Ensure that any data held in the cache is appropriately discarded
  63. * or written back.
  64. *
  65. * The device owns this memory once this call has completed. The CPU
  66. * can regain ownership by calling dma_unmap_page().
  67. */
  68. static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
  69. unsigned long offset, size_t size, enum dma_data_direction dir,
  70. struct dma_attrs *attrs)
  71. {
  72. if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
  73. __dma_page_cpu_to_dev(page, offset, size, dir);
  74. return pfn_to_dma(dev, page_to_pfn(page)) + offset;
  75. }
  76. static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
  77. unsigned long offset, size_t size, enum dma_data_direction dir,
  78. struct dma_attrs *attrs)
  79. {
  80. return pfn_to_dma(dev, page_to_pfn(page)) + offset;
  81. }
  82. /**
  83. * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
  84. * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
  85. * @handle: DMA address of buffer
  86. * @size: size of buffer (same as passed to dma_map_page)
  87. * @dir: DMA transfer direction (same as passed to dma_map_page)
  88. *
  89. * Unmap a page streaming mode DMA translation. The handle and size
  90. * must match what was provided in the previous dma_map_page() call.
  91. * All other usages are undefined.
  92. *
  93. * After this call, reads by the CPU to the buffer are guaranteed to see
  94. * whatever the device wrote there.
  95. */
  96. static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
  97. size_t size, enum dma_data_direction dir,
  98. struct dma_attrs *attrs)
  99. {
  100. if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
  101. __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
  102. handle & ~PAGE_MASK, size, dir);
  103. }
  104. static void arm_dma_sync_single_for_cpu(struct device *dev,
  105. dma_addr_t handle, size_t size, enum dma_data_direction dir)
  106. {
  107. unsigned int offset = handle & (PAGE_SIZE - 1);
  108. struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
  109. __dma_page_dev_to_cpu(page, offset, size, dir);
  110. }
  111. static void arm_dma_sync_single_for_device(struct device *dev,
  112. dma_addr_t handle, size_t size, enum dma_data_direction dir)
  113. {
  114. unsigned int offset = handle & (PAGE_SIZE - 1);
  115. struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
  116. __dma_page_cpu_to_dev(page, offset, size, dir);
  117. }
  118. struct dma_map_ops arm_dma_ops = {
  119. .alloc = arm_dma_alloc,
  120. .free = arm_dma_free,
  121. .mmap = arm_dma_mmap,
  122. .get_sgtable = arm_dma_get_sgtable,
  123. .map_page = arm_dma_map_page,
  124. .unmap_page = arm_dma_unmap_page,
  125. .map_sg = arm_dma_map_sg,
  126. .unmap_sg = arm_dma_unmap_sg,
  127. .sync_single_for_cpu = arm_dma_sync_single_for_cpu,
  128. .sync_single_for_device = arm_dma_sync_single_for_device,
  129. .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
  130. .sync_sg_for_device = arm_dma_sync_sg_for_device,
  131. .set_dma_mask = arm_dma_set_mask,
  132. };
  133. EXPORT_SYMBOL(arm_dma_ops);
  134. static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
  135. dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs);
  136. static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
  137. dma_addr_t handle, struct dma_attrs *attrs);
  138. struct dma_map_ops arm_coherent_dma_ops = {
  139. .alloc = arm_coherent_dma_alloc,
  140. .free = arm_coherent_dma_free,
  141. .mmap = arm_dma_mmap,
  142. .get_sgtable = arm_dma_get_sgtable,
  143. .map_page = arm_coherent_dma_map_page,
  144. .map_sg = arm_dma_map_sg,
  145. .set_dma_mask = arm_dma_set_mask,
  146. };
  147. EXPORT_SYMBOL(arm_coherent_dma_ops);
  148. static u64 get_coherent_dma_mask(struct device *dev)
  149. {
  150. u64 mask = (u64)arm_dma_limit;
  151. if (dev) {
  152. mask = dev->coherent_dma_mask;
  153. /*
  154. * Sanity check the DMA mask - it must be non-zero, and
  155. * must be able to be satisfied by a DMA allocation.
  156. */
  157. if (mask == 0) {
  158. dev_warn(dev, "coherent DMA mask is unset\n");
  159. return 0;
  160. }
  161. if ((~mask) & (u64)arm_dma_limit) {
  162. dev_warn(dev, "coherent DMA mask %#llx is smaller "
  163. "than system GFP_DMA mask %#llx\n",
  164. mask, (u64)arm_dma_limit);
  165. return 0;
  166. }
  167. }
  168. return mask;
  169. }
  170. static void __dma_clear_buffer(struct page *page, size_t size)
  171. {
  172. /*
  173. * Ensure that the allocated pages are zeroed, and that any data
  174. * lurking in the kernel direct-mapped region is invalidated.
  175. */
  176. if (PageHighMem(page)) {
  177. phys_addr_t base = __pfn_to_phys(page_to_pfn(page));
  178. phys_addr_t end = base + size;
  179. while (size > 0) {
  180. void *ptr = kmap_atomic(page);
  181. memset(ptr, 0, PAGE_SIZE);
  182. dmac_flush_range(ptr, ptr + PAGE_SIZE);
  183. kunmap_atomic(ptr);
  184. page++;
  185. size -= PAGE_SIZE;
  186. }
  187. outer_flush_range(base, end);
  188. } else {
  189. void *ptr = page_address(page);
  190. memset(ptr, 0, size);
  191. dmac_flush_range(ptr, ptr + size);
  192. outer_flush_range(__pa(ptr), __pa(ptr) + size);
  193. }
  194. }
  195. /*
  196. * Allocate a DMA buffer for 'dev' of size 'size' using the
  197. * specified gfp mask. Note that 'size' must be page aligned.
  198. */
  199. static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
  200. {
  201. unsigned long order = get_order(size);
  202. struct page *page, *p, *e;
  203. page = alloc_pages(gfp, order);
  204. if (!page)
  205. return NULL;
  206. /*
  207. * Now split the huge page and free the excess pages
  208. */
  209. split_page(page, order);
  210. for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
  211. __free_page(p);
  212. __dma_clear_buffer(page, size);
  213. return page;
  214. }
  215. /*
  216. * Free a DMA buffer. 'size' must be page aligned.
  217. */
  218. static void __dma_free_buffer(struct page *page, size_t size)
  219. {
  220. struct page *e = page + (size >> PAGE_SHIFT);
  221. while (page < e) {
  222. __free_page(page);
  223. page++;
  224. }
  225. }
  226. #ifdef CONFIG_MMU
  227. #ifdef CONFIG_HUGETLB_PAGE
  228. #error ARM Coherent DMA allocator does not (yet) support huge TLB
  229. #endif
  230. static void *__alloc_from_contiguous(struct device *dev, size_t size,
  231. pgprot_t prot, struct page **ret_page,
  232. const void *caller);
  233. static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
  234. pgprot_t prot, struct page **ret_page,
  235. const void *caller);
  236. static void *
  237. __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
  238. const void *caller)
  239. {
  240. struct vm_struct *area;
  241. unsigned long addr;
  242. /*
  243. * DMA allocation can be mapped to user space, so lets
  244. * set VM_USERMAP flags too.
  245. */
  246. area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
  247. caller);
  248. if (!area)
  249. return NULL;
  250. addr = (unsigned long)area->addr;
  251. area->phys_addr = __pfn_to_phys(page_to_pfn(page));
  252. if (ioremap_page_range(addr, addr + size, area->phys_addr, prot)) {
  253. vunmap((void *)addr);
  254. return NULL;
  255. }
  256. return (void *)addr;
  257. }
  258. static void __dma_free_remap(void *cpu_addr, size_t size)
  259. {
  260. unsigned int flags = VM_ARM_DMA_CONSISTENT | VM_USERMAP;
  261. struct vm_struct *area = find_vm_area(cpu_addr);
  262. if (!area || (area->flags & flags) != flags) {
  263. WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
  264. return;
  265. }
  266. unmap_kernel_range((unsigned long)cpu_addr, size);
  267. vunmap(cpu_addr);
  268. }
  269. #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
  270. struct dma_pool {
  271. size_t size;
  272. spinlock_t lock;
  273. unsigned long *bitmap;
  274. unsigned long nr_pages;
  275. void *vaddr;
  276. struct page **pages;
  277. };
  278. static struct dma_pool atomic_pool = {
  279. .size = DEFAULT_DMA_COHERENT_POOL_SIZE,
  280. };
  281. static int __init early_coherent_pool(char *p)
  282. {
  283. atomic_pool.size = memparse(p, &p);
  284. return 0;
  285. }
  286. early_param("coherent_pool", early_coherent_pool);
  287. void __init init_dma_coherent_pool_size(unsigned long size)
  288. {
  289. /*
  290. * Catch any attempt to set the pool size too late.
  291. */
  292. BUG_ON(atomic_pool.vaddr);
  293. /*
  294. * Set architecture specific coherent pool size only if
  295. * it has not been changed by kernel command line parameter.
  296. */
  297. if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE)
  298. atomic_pool.size = size;
  299. }
  300. /*
  301. * Initialise the coherent pool for atomic allocations.
  302. */
  303. static int __init atomic_pool_init(void)
  304. {
  305. struct dma_pool *pool = &atomic_pool;
  306. pgprot_t prot = pgprot_dmacoherent(pgprot_kernel);
  307. gfp_t gfp = GFP_KERNEL | GFP_DMA;
  308. unsigned long nr_pages = pool->size >> PAGE_SHIFT;
  309. unsigned long *bitmap;
  310. struct page *page;
  311. struct page **pages;
  312. void *ptr;
  313. int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long);
  314. bitmap = kzalloc(bitmap_size, GFP_KERNEL);
  315. if (!bitmap)
  316. goto no_bitmap;
  317. pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
  318. if (!pages)
  319. goto no_pages;
  320. if (IS_ENABLED(CONFIG_CMA))
  321. ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page,
  322. atomic_pool_init);
  323. else
  324. ptr = __alloc_remap_buffer(NULL, pool->size, gfp, prot, &page,
  325. atomic_pool_init);
  326. if (ptr) {
  327. int i;
  328. for (i = 0; i < nr_pages; i++)
  329. pages[i] = page + i;
  330. spin_lock_init(&pool->lock);
  331. pool->vaddr = ptr;
  332. pool->pages = pages;
  333. pool->bitmap = bitmap;
  334. pool->nr_pages = nr_pages;
  335. pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n",
  336. (unsigned)pool->size / 1024);
  337. return 0;
  338. }
  339. kfree(pages);
  340. no_pages:
  341. kfree(bitmap);
  342. no_bitmap:
  343. pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n",
  344. (unsigned)pool->size / 1024);
  345. return -ENOMEM;
  346. }
  347. /*
  348. * CMA is activated by core_initcall, so we must be called after it.
  349. */
  350. postcore_initcall(atomic_pool_init);
  351. struct dma_contig_early_reserve {
  352. phys_addr_t base;
  353. unsigned long size;
  354. };
  355. static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata;
  356. static int dma_mmu_remap_num __initdata;
  357. void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
  358. {
  359. dma_mmu_remap[dma_mmu_remap_num].base = base;
  360. dma_mmu_remap[dma_mmu_remap_num].size = size;
  361. dma_mmu_remap_num++;
  362. }
  363. void __init dma_contiguous_remap(void)
  364. {
  365. int i;
  366. for (i = 0; i < dma_mmu_remap_num; i++) {
  367. phys_addr_t start = dma_mmu_remap[i].base;
  368. phys_addr_t end = start + dma_mmu_remap[i].size;
  369. struct map_desc map;
  370. unsigned long addr;
  371. if (end > arm_lowmem_limit)
  372. end = arm_lowmem_limit;
  373. if (start >= end)
  374. continue;
  375. map.pfn = __phys_to_pfn(start);
  376. map.virtual = __phys_to_virt(start);
  377. map.length = end - start;
  378. map.type = MT_MEMORY_DMA_READY;
  379. /*
  380. * Clear previous low-memory mapping
  381. */
  382. for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
  383. addr += PMD_SIZE)
  384. pmd_clear(pmd_off_k(addr));
  385. iotable_init(&map, 1);
  386. }
  387. }
  388. static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr,
  389. void *data)
  390. {
  391. struct page *page = virt_to_page(addr);
  392. pgprot_t prot = *(pgprot_t *)data;
  393. set_pte_ext(pte, mk_pte(page, prot), 0);
  394. return 0;
  395. }
  396. static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
  397. {
  398. unsigned long start = (unsigned long) page_address(page);
  399. unsigned end = start + size;
  400. apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
  401. dsb();
  402. flush_tlb_kernel_range(start, end);
  403. }
  404. static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
  405. pgprot_t prot, struct page **ret_page,
  406. const void *caller)
  407. {
  408. struct page *page;
  409. void *ptr;
  410. page = __dma_alloc_buffer(dev, size, gfp);
  411. if (!page)
  412. return NULL;
  413. ptr = __dma_alloc_remap(page, size, gfp, prot, caller);
  414. if (!ptr) {
  415. __dma_free_buffer(page, size);
  416. return NULL;
  417. }
  418. *ret_page = page;
  419. return ptr;
  420. }
  421. static void *__alloc_from_pool(size_t size, struct page **ret_page)
  422. {
  423. struct dma_pool *pool = &atomic_pool;
  424. unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
  425. unsigned int pageno;
  426. unsigned long flags;
  427. void *ptr = NULL;
  428. unsigned long align_mask;
  429. if (!pool->vaddr) {
  430. WARN(1, "coherent pool not initialised!\n");
  431. return NULL;
  432. }
  433. /*
  434. * Align the region allocation - allocations from pool are rather
  435. * small, so align them to their order in pages, minimum is a page
  436. * size. This helps reduce fragmentation of the DMA space.
  437. */
  438. align_mask = (1 << get_order(size)) - 1;
  439. spin_lock_irqsave(&pool->lock, flags);
  440. pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages,
  441. 0, count, align_mask);
  442. if (pageno < pool->nr_pages) {
  443. bitmap_set(pool->bitmap, pageno, count);
  444. ptr = pool->vaddr + PAGE_SIZE * pageno;
  445. *ret_page = pool->pages[pageno];
  446. } else {
  447. pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n"
  448. "Please increase it with coherent_pool= kernel parameter!\n",
  449. (unsigned)pool->size / 1024);
  450. }
  451. spin_unlock_irqrestore(&pool->lock, flags);
  452. return ptr;
  453. }
  454. static bool __in_atomic_pool(void *start, size_t size)
  455. {
  456. struct dma_pool *pool = &atomic_pool;
  457. void *end = start + size;
  458. void *pool_start = pool->vaddr;
  459. void *pool_end = pool->vaddr + pool->size;
  460. if (start < pool_start || start >= pool_end)
  461. return false;
  462. if (end <= pool_end)
  463. return true;
  464. WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n",
  465. start, end - 1, pool_start, pool_end - 1);
  466. return false;
  467. }
  468. static int __free_from_pool(void *start, size_t size)
  469. {
  470. struct dma_pool *pool = &atomic_pool;
  471. unsigned long pageno, count;
  472. unsigned long flags;
  473. if (!__in_atomic_pool(start, size))
  474. return 0;
  475. pageno = (start - pool->vaddr) >> PAGE_SHIFT;
  476. count = size >> PAGE_SHIFT;
  477. spin_lock_irqsave(&pool->lock, flags);
  478. bitmap_clear(pool->bitmap, pageno, count);
  479. spin_unlock_irqrestore(&pool->lock, flags);
  480. return 1;
  481. }
  482. static void *__alloc_from_contiguous(struct device *dev, size_t size,
  483. pgprot_t prot, struct page **ret_page,
  484. const void *caller)
  485. {
  486. unsigned long order = get_order(size);
  487. size_t count = size >> PAGE_SHIFT;
  488. struct page *page;
  489. void *ptr;
  490. page = dma_alloc_from_contiguous(dev, count, order);
  491. if (!page)
  492. return NULL;
  493. __dma_clear_buffer(page, size);
  494. if (PageHighMem(page)) {
  495. ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller);
  496. if (!ptr) {
  497. dma_release_from_contiguous(dev, page, count);
  498. return NULL;
  499. }
  500. } else {
  501. __dma_remap(page, size, prot);
  502. ptr = page_address(page);
  503. }
  504. *ret_page = page;
  505. return ptr;
  506. }
  507. static void __free_from_contiguous(struct device *dev, struct page *page,
  508. void *cpu_addr, size_t size)
  509. {
  510. if (PageHighMem(page))
  511. __dma_free_remap(cpu_addr, size);
  512. else
  513. __dma_remap(page, size, pgprot_kernel);
  514. dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
  515. }
  516. static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot)
  517. {
  518. prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
  519. pgprot_writecombine(prot) :
  520. pgprot_dmacoherent(prot);
  521. return prot;
  522. }
  523. #define nommu() 0
  524. #else /* !CONFIG_MMU */
  525. #define nommu() 1
  526. #define __get_dma_pgprot(attrs, prot) __pgprot(0)
  527. #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL
  528. #define __alloc_from_pool(size, ret_page) NULL
  529. #define __alloc_from_contiguous(dev, size, prot, ret, c) NULL
  530. #define __free_from_pool(cpu_addr, size) 0
  531. #define __free_from_contiguous(dev, page, cpu_addr, size) do { } while (0)
  532. #define __dma_free_remap(cpu_addr, size) do { } while (0)
  533. #endif /* CONFIG_MMU */
  534. static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
  535. struct page **ret_page)
  536. {
  537. struct page *page;
  538. page = __dma_alloc_buffer(dev, size, gfp);
  539. if (!page)
  540. return NULL;
  541. *ret_page = page;
  542. return page_address(page);
  543. }
  544. static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
  545. gfp_t gfp, pgprot_t prot, bool is_coherent, const void *caller)
  546. {
  547. u64 mask = get_coherent_dma_mask(dev);
  548. struct page *page = NULL;
  549. void *addr;
  550. #ifdef CONFIG_DMA_API_DEBUG
  551. u64 limit = (mask + 1) & ~mask;
  552. if (limit && size >= limit) {
  553. dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
  554. size, mask);
  555. return NULL;
  556. }
  557. #endif
  558. if (!mask)
  559. return NULL;
  560. if (mask < 0xffffffffULL)
  561. gfp |= GFP_DMA;
  562. /*
  563. * Following is a work-around (a.k.a. hack) to prevent pages
  564. * with __GFP_COMP being passed to split_page() which cannot
  565. * handle them. The real problem is that this flag probably
  566. * should be 0 on ARM as it is not supported on this
  567. * platform; see CONFIG_HUGETLBFS.
  568. */
  569. gfp &= ~(__GFP_COMP);
  570. *handle = DMA_ERROR_CODE;
  571. size = PAGE_ALIGN(size);
  572. if (is_coherent || nommu())
  573. addr = __alloc_simple_buffer(dev, size, gfp, &page);
  574. else if (!(gfp & __GFP_WAIT))
  575. addr = __alloc_from_pool(size, &page);
  576. else if (!IS_ENABLED(CONFIG_CMA))
  577. addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
  578. else
  579. addr = __alloc_from_contiguous(dev, size, prot, &page, caller);
  580. if (addr)
  581. *handle = pfn_to_dma(dev, page_to_pfn(page));
  582. return addr;
  583. }
  584. /*
  585. * Allocate DMA-coherent memory space and return both the kernel remapped
  586. * virtual and bus address for that space.
  587. */
  588. void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
  589. gfp_t gfp, struct dma_attrs *attrs)
  590. {
  591. pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
  592. void *memory;
  593. if (dma_alloc_from_coherent(dev, size, handle, &memory))
  594. return memory;
  595. return __dma_alloc(dev, size, handle, gfp, prot, false,
  596. __builtin_return_address(0));
  597. }
  598. static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
  599. dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
  600. {
  601. pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
  602. void *memory;
  603. if (dma_alloc_from_coherent(dev, size, handle, &memory))
  604. return memory;
  605. return __dma_alloc(dev, size, handle, gfp, prot, true,
  606. __builtin_return_address(0));
  607. }
  608. /*
  609. * Create userspace mapping for the DMA-coherent memory.
  610. */
  611. int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
  612. void *cpu_addr, dma_addr_t dma_addr, size_t size,
  613. struct dma_attrs *attrs)
  614. {
  615. int ret = -ENXIO;
  616. #ifdef CONFIG_MMU
  617. unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
  618. unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
  619. unsigned long pfn = dma_to_pfn(dev, dma_addr);
  620. unsigned long off = vma->vm_pgoff;
  621. vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
  622. if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
  623. return ret;
  624. if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
  625. ret = remap_pfn_range(vma, vma->vm_start,
  626. pfn + off,
  627. vma->vm_end - vma->vm_start,
  628. vma->vm_page_prot);
  629. }
  630. #endif /* CONFIG_MMU */
  631. return ret;
  632. }
  633. /*
  634. * Free a buffer as defined by the above mapping.
  635. */
  636. static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
  637. dma_addr_t handle, struct dma_attrs *attrs,
  638. bool is_coherent)
  639. {
  640. struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
  641. if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
  642. return;
  643. size = PAGE_ALIGN(size);
  644. if (is_coherent || nommu()) {
  645. __dma_free_buffer(page, size);
  646. } else if (__free_from_pool(cpu_addr, size)) {
  647. return;
  648. } else if (!IS_ENABLED(CONFIG_CMA)) {
  649. __dma_free_remap(cpu_addr, size);
  650. __dma_free_buffer(page, size);
  651. } else {
  652. /*
  653. * Non-atomic allocations cannot be freed with IRQs disabled
  654. */
  655. WARN_ON(irqs_disabled());
  656. __free_from_contiguous(dev, page, cpu_addr, size);
  657. }
  658. }
  659. void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
  660. dma_addr_t handle, struct dma_attrs *attrs)
  661. {
  662. __arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
  663. }
  664. static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
  665. dma_addr_t handle, struct dma_attrs *attrs)
  666. {
  667. __arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
  668. }
  669. int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
  670. void *cpu_addr, dma_addr_t handle, size_t size,
  671. struct dma_attrs *attrs)
  672. {
  673. struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
  674. int ret;
  675. ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
  676. if (unlikely(ret))
  677. return ret;
  678. sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
  679. return 0;
  680. }
  681. static void dma_cache_maint_page(struct page *page, unsigned long offset,
  682. size_t size, enum dma_data_direction dir,
  683. void (*op)(const void *, size_t, int))
  684. {
  685. unsigned long pfn;
  686. size_t left = size;
  687. pfn = page_to_pfn(page) + offset / PAGE_SIZE;
  688. offset %= PAGE_SIZE;
  689. /*
  690. * A single sg entry may refer to multiple physically contiguous
  691. * pages. But we still need to process highmem pages individually.
  692. * If highmem is not configured then the bulk of this loop gets
  693. * optimized out.
  694. */
  695. do {
  696. size_t len = left;
  697. void *vaddr;
  698. page = pfn_to_page(pfn);
  699. if (PageHighMem(page)) {
  700. if (len + offset > PAGE_SIZE)
  701. len = PAGE_SIZE - offset;
  702. if (cache_is_vipt_nonaliasing()) {
  703. vaddr = kmap_atomic(page);
  704. op(vaddr + offset, len, dir);
  705. kunmap_atomic(vaddr);
  706. } else {
  707. vaddr = kmap_high_get(page);
  708. if (vaddr) {
  709. op(vaddr + offset, len, dir);
  710. kunmap_high(page);
  711. }
  712. }
  713. } else {
  714. vaddr = page_address(page) + offset;
  715. op(vaddr, len, dir);
  716. }
  717. offset = 0;
  718. pfn++;
  719. left -= len;
  720. } while (left);
  721. }
  722. /*
  723. * Make an area consistent for devices.
  724. * Note: Drivers should NOT use this function directly, as it will break
  725. * platforms with CONFIG_DMABOUNCE.
  726. * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
  727. */
  728. static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
  729. size_t size, enum dma_data_direction dir)
  730. {
  731. unsigned long paddr;
  732. dma_cache_maint_page(page, off, size, dir, dmac_map_area);
  733. paddr = page_to_phys(page) + off;
  734. if (dir == DMA_FROM_DEVICE) {
  735. outer_inv_range(paddr, paddr + size);
  736. } else {
  737. outer_clean_range(paddr, paddr + size);
  738. }
  739. /* FIXME: non-speculating: flush on bidirectional mappings? */
  740. }
  741. static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
  742. size_t size, enum dma_data_direction dir)
  743. {
  744. unsigned long paddr = page_to_phys(page) + off;
  745. /* FIXME: non-speculating: not required */
  746. /* don't bother invalidating if DMA to device */
  747. if (dir != DMA_TO_DEVICE)
  748. outer_inv_range(paddr, paddr + size);
  749. dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
  750. /*
  751. * Mark the D-cache clean for this page to avoid extra flushing.
  752. */
  753. if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE)
  754. set_bit(PG_dcache_clean, &page->flags);
  755. }
  756. /**
  757. * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA
  758. * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
  759. * @sg: list of buffers
  760. * @nents: number of buffers to map
  761. * @dir: DMA transfer direction
  762. *
  763. * Map a set of buffers described by scatterlist in streaming mode for DMA.
  764. * This is the scatter-gather version of the dma_map_single interface.
  765. * Here the scatter gather list elements are each tagged with the
  766. * appropriate dma address and length. They are obtained via
  767. * sg_dma_{address,length}.
  768. *
  769. * Device ownership issues as mentioned for dma_map_single are the same
  770. * here.
  771. */
  772. int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
  773. enum dma_data_direction dir, struct dma_attrs *attrs)
  774. {
  775. struct dma_map_ops *ops = get_dma_ops(dev);
  776. struct scatterlist *s;
  777. int i, j;
  778. for_each_sg(sg, s, nents, i) {
  779. #ifdef CONFIG_NEED_SG_DMA_LENGTH
  780. s->dma_length = s->length;
  781. #endif
  782. s->dma_address = ops->map_page(dev, sg_page(s), s->offset,
  783. s->length, dir, attrs);
  784. if (dma_mapping_error(dev, s->dma_address))
  785. goto bad_mapping;
  786. }
  787. return nents;
  788. bad_mapping:
  789. for_each_sg(sg, s, i, j)
  790. ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
  791. return 0;
  792. }
  793. /**
  794. * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
  795. * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
  796. * @sg: list of buffers
  797. * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
  798. * @dir: DMA transfer direction (same as was passed to dma_map_sg)
  799. *
  800. * Unmap a set of streaming mode DMA translations. Again, CPU access
  801. * rules concerning calls here are the same as for dma_unmap_single().
  802. */
  803. void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
  804. enum dma_data_direction dir, struct dma_attrs *attrs)
  805. {
  806. struct dma_map_ops *ops = get_dma_ops(dev);
  807. struct scatterlist *s;
  808. int i;
  809. for_each_sg(sg, s, nents, i)
  810. ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
  811. }
  812. /**
  813. * arm_dma_sync_sg_for_cpu
  814. * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
  815. * @sg: list of buffers
  816. * @nents: number of buffers to map (returned from dma_map_sg)
  817. * @dir: DMA transfer direction (same as was passed to dma_map_sg)
  818. */
  819. void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
  820. int nents, enum dma_data_direction dir)
  821. {
  822. struct dma_map_ops *ops = get_dma_ops(dev);
  823. struct scatterlist *s;
  824. int i;
  825. for_each_sg(sg, s, nents, i)
  826. ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length,
  827. dir);
  828. }
  829. /**
  830. * arm_dma_sync_sg_for_device
  831. * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
  832. * @sg: list of buffers
  833. * @nents: number of buffers to map (returned from dma_map_sg)
  834. * @dir: DMA transfer direction (same as was passed to dma_map_sg)
  835. */
  836. void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
  837. int nents, enum dma_data_direction dir)
  838. {
  839. struct dma_map_ops *ops = get_dma_ops(dev);
  840. struct scatterlist *s;
  841. int i;
  842. for_each_sg(sg, s, nents, i)
  843. ops->sync_single_for_device(dev, sg_dma_address(s), s->length,
  844. dir);
  845. }
  846. /*
  847. * Return whether the given device DMA address mask can be supported
  848. * properly. For example, if your device can only drive the low 24-bits
  849. * during bus mastering, then you would pass 0x00ffffff as the mask
  850. * to this function.
  851. */
  852. int dma_supported(struct device *dev, u64 mask)
  853. {
  854. if (mask < (u64)arm_dma_limit)
  855. return 0;
  856. return 1;
  857. }
  858. EXPORT_SYMBOL(dma_supported);
  859. int arm_dma_set_mask(struct device *dev, u64 dma_mask)
  860. {
  861. if (!dev->dma_mask || !dma_supported(dev, dma_mask))
  862. return -EIO;
  863. *dev->dma_mask = dma_mask;
  864. return 0;
  865. }
  866. #define PREALLOC_DMA_DEBUG_ENTRIES 4096
  867. static int __init dma_debug_do_init(void)
  868. {
  869. dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
  870. return 0;
  871. }
  872. fs_initcall(dma_debug_do_init);
  873. #ifdef CONFIG_ARM_DMA_USE_IOMMU
  874. /* IOMMU */
  875. static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
  876. size_t size)
  877. {
  878. unsigned int order = get_order(size);
  879. unsigned int align = 0;
  880. unsigned int count, start;
  881. unsigned long flags;
  882. if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT)
  883. order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT;
  884. count = ((PAGE_ALIGN(size) >> PAGE_SHIFT) +
  885. (1 << mapping->order) - 1) >> mapping->order;
  886. if (order > mapping->order)
  887. align = (1 << (order - mapping->order)) - 1;
  888. spin_lock_irqsave(&mapping->lock, flags);
  889. start = bitmap_find_next_zero_area(mapping->bitmap, mapping->bits, 0,
  890. count, align);
  891. if (start > mapping->bits) {
  892. spin_unlock_irqrestore(&mapping->lock, flags);
  893. return DMA_ERROR_CODE;
  894. }
  895. bitmap_set(mapping->bitmap, start, count);
  896. spin_unlock_irqrestore(&mapping->lock, flags);
  897. return mapping->base + (start << (mapping->order + PAGE_SHIFT));
  898. }
  899. static inline void __free_iova(struct dma_iommu_mapping *mapping,
  900. dma_addr_t addr, size_t size)
  901. {
  902. unsigned int start = (addr - mapping->base) >>
  903. (mapping->order + PAGE_SHIFT);
  904. unsigned int count = ((size >> PAGE_SHIFT) +
  905. (1 << mapping->order) - 1) >> mapping->order;
  906. unsigned long flags;
  907. spin_lock_irqsave(&mapping->lock, flags);
  908. bitmap_clear(mapping->bitmap, start, count);
  909. spin_unlock_irqrestore(&mapping->lock, flags);
  910. }
  911. static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
  912. gfp_t gfp, struct dma_attrs *attrs)
  913. {
  914. struct page **pages;
  915. int count = size >> PAGE_SHIFT;
  916. int array_size = count * sizeof(struct page *);
  917. int i = 0;
  918. if (array_size <= PAGE_SIZE)
  919. pages = kzalloc(array_size, gfp);
  920. else
  921. pages = vzalloc(array_size);
  922. if (!pages)
  923. return NULL;
  924. if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs))
  925. {
  926. unsigned long order = get_order(size);
  927. struct page *page;
  928. page = dma_alloc_from_contiguous(dev, count, order);
  929. if (!page)
  930. goto error;
  931. __dma_clear_buffer(page, size);
  932. for (i = 0; i < count; i++)
  933. pages[i] = page + i;
  934. return pages;
  935. }
  936. /*
  937. * IOMMU can map any pages, so himem can also be used here
  938. */
  939. gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
  940. while (count) {
  941. int j, order = __fls(count);
  942. pages[i] = alloc_pages(gfp, order);
  943. while (!pages[i] && order)
  944. pages[i] = alloc_pages(gfp, --order);
  945. if (!pages[i])
  946. goto error;
  947. if (order) {
  948. split_page(pages[i], order);
  949. j = 1 << order;
  950. while (--j)
  951. pages[i + j] = pages[i] + j;
  952. }
  953. __dma_clear_buffer(pages[i], PAGE_SIZE << order);
  954. i += 1 << order;
  955. count -= 1 << order;
  956. }
  957. return pages;
  958. error:
  959. while (i--)
  960. if (pages[i])
  961. __free_pages(pages[i], 0);
  962. if (array_size <= PAGE_SIZE)
  963. kfree(pages);
  964. else
  965. vfree(pages);
  966. return NULL;
  967. }
  968. static int __iommu_free_buffer(struct device *dev, struct page **pages,
  969. size_t size, struct dma_attrs *attrs)
  970. {
  971. int count = size >> PAGE_SHIFT;
  972. int array_size = count * sizeof(struct page *);
  973. int i;
  974. if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) {
  975. dma_release_from_contiguous(dev, pages[0], count);
  976. } else {
  977. for (i = 0; i < count; i++)
  978. if (pages[i])
  979. __free_pages(pages[i], 0);
  980. }
  981. if (array_size <= PAGE_SIZE)
  982. kfree(pages);
  983. else
  984. vfree(pages);
  985. return 0;
  986. }
  987. /*
  988. * Create a CPU mapping for a specified pages
  989. */
  990. static void *
  991. __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
  992. const void *caller)
  993. {
  994. unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
  995. struct vm_struct *area;
  996. unsigned long p;
  997. area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
  998. caller);
  999. if (!area)
  1000. return NULL;
  1001. area->pages = pages;
  1002. area->nr_pages = nr_pages;
  1003. p = (unsigned long)area->addr;
  1004. for (i = 0; i < nr_pages; i++) {
  1005. phys_addr_t phys = __pfn_to_phys(page_to_pfn(pages[i]));
  1006. if (ioremap_page_range(p, p + PAGE_SIZE, phys, prot))
  1007. goto err;
  1008. p += PAGE_SIZE;
  1009. }
  1010. return area->addr;
  1011. err:
  1012. unmap_kernel_range((unsigned long)area->addr, size);
  1013. vunmap(area->addr);
  1014. return NULL;
  1015. }
  1016. /*
  1017. * Create a mapping in device IO address space for specified pages
  1018. */
  1019. static dma_addr_t
  1020. __iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
  1021. {
  1022. struct dma_iommu_mapping *mapping = dev->archdata.mapping;
  1023. unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
  1024. dma_addr_t dma_addr, iova;
  1025. int i, ret = DMA_ERROR_CODE;
  1026. dma_addr = __alloc_iova(mapping, size);
  1027. if (dma_addr == DMA_ERROR_CODE)
  1028. return dma_addr;
  1029. iova = dma_addr;
  1030. for (i = 0; i < count; ) {
  1031. unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
  1032. phys_addr_t phys = page_to_phys(pages[i]);
  1033. unsigned int len, j;
  1034. for (j = i + 1; j < count; j++, next_pfn++)
  1035. if (page_to_pfn(pages[j]) != next_pfn)
  1036. break;
  1037. len = (j - i) << PAGE_SHIFT;
  1038. ret = iommu_map(mapping->domain, iova, phys, len, 0);
  1039. if (ret < 0)
  1040. goto fail;
  1041. iova += len;
  1042. i = j;
  1043. }
  1044. return dma_addr;
  1045. fail:
  1046. iommu_unmap(mapping->domain, dma_addr, iova-dma_addr);
  1047. __free_iova(mapping, dma_addr, size);
  1048. return DMA_ERROR_CODE;
  1049. }
  1050. static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size)
  1051. {
  1052. struct dma_iommu_mapping *mapping = dev->archdata.mapping;
  1053. /*
  1054. * add optional in-page offset from iova to size and align
  1055. * result to page size
  1056. */
  1057. size = PAGE_ALIGN((iova & ~PAGE_MASK) + size);
  1058. iova &= PAGE_MASK;
  1059. iommu_unmap(mapping->domain, iova, size);
  1060. __free_iova(mapping, iova, size);
  1061. return 0;
  1062. }
  1063. static struct page **__atomic_get_pages(void *addr)
  1064. {
  1065. struct dma_pool *pool = &atomic_pool;
  1066. struct page **pages = pool->pages;
  1067. int offs = (addr - pool->vaddr) >> PAGE_SHIFT;
  1068. return pages + offs;
  1069. }
  1070. static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
  1071. {
  1072. struct vm_struct *area;
  1073. if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
  1074. return __atomic_get_pages(cpu_addr);
  1075. if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
  1076. return cpu_addr;
  1077. area = find_vm_area(cpu_addr);
  1078. if (area && (area->flags & VM_ARM_DMA_CONSISTENT))
  1079. return area->pages;
  1080. return NULL;
  1081. }
  1082. static void *__iommu_alloc_atomic(struct device *dev, size_t size,
  1083. dma_addr_t *handle)
  1084. {
  1085. struct page *page;
  1086. void *addr;
  1087. addr = __alloc_from_pool(size, &page);
  1088. if (!addr)
  1089. return NULL;
  1090. *handle = __iommu_create_mapping(dev, &page, size);
  1091. if (*handle == DMA_ERROR_CODE)
  1092. goto err_mapping;
  1093. return addr;
  1094. err_mapping:
  1095. __free_from_pool(addr, size);
  1096. return NULL;
  1097. }
  1098. static void __iommu_free_atomic(struct device *dev, void *cpu_addr,
  1099. dma_addr_t handle, size_t size)
  1100. {
  1101. __iommu_remove_mapping(dev, handle, size);
  1102. __free_from_pool(cpu_addr, size);
  1103. }
  1104. static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
  1105. dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
  1106. {
  1107. pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
  1108. struct page **pages;
  1109. void *addr = NULL;
  1110. *handle = DMA_ERROR_CODE;
  1111. size = PAGE_ALIGN(size);
  1112. if (gfp & GFP_ATOMIC)
  1113. return __iommu_alloc_atomic(dev, size, handle);
  1114. pages = __iommu_alloc_buffer(dev, size, gfp, attrs);
  1115. if (!pages)
  1116. return NULL;
  1117. *handle = __iommu_create_mapping(dev, pages, size);
  1118. if (*handle == DMA_ERROR_CODE)
  1119. goto err_buffer;
  1120. if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
  1121. return pages;
  1122. addr = __iommu_alloc_remap(pages, size, gfp, prot,
  1123. __builtin_return_address(0));
  1124. if (!addr)
  1125. goto err_mapping;
  1126. return addr;
  1127. err_mapping:
  1128. __iommu_remove_mapping(dev, *handle, size);
  1129. err_buffer:
  1130. __iommu_free_buffer(dev, pages, size, attrs);
  1131. return NULL;
  1132. }
  1133. static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
  1134. void *cpu_addr, dma_addr_t dma_addr, size_t size,
  1135. struct dma_attrs *attrs)
  1136. {
  1137. unsigned long uaddr = vma->vm_start;
  1138. unsigned long usize = vma->vm_end - vma->vm_start;
  1139. struct page **pages = __iommu_get_pages(cpu_addr, attrs);
  1140. vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
  1141. if (!pages)
  1142. return -ENXIO;
  1143. do {
  1144. int ret = vm_insert_page(vma, uaddr, *pages++);
  1145. if (ret) {
  1146. pr_err("Remapping memory failed: %d\n", ret);
  1147. return ret;
  1148. }
  1149. uaddr += PAGE_SIZE;
  1150. usize -= PAGE_SIZE;
  1151. } while (usize > 0);
  1152. return 0;
  1153. }
  1154. /*
  1155. * free a page as defined by the above mapping.
  1156. * Must not be called with IRQs disabled.
  1157. */
  1158. void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
  1159. dma_addr_t handle, struct dma_attrs *attrs)
  1160. {
  1161. struct page **pages = __iommu_get_pages(cpu_addr, attrs);
  1162. size = PAGE_ALIGN(size);
  1163. if (!pages) {
  1164. WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
  1165. return;
  1166. }
  1167. if (__in_atomic_pool(cpu_addr, size)) {
  1168. __iommu_free_atomic(dev, cpu_addr, handle, size);
  1169. return;
  1170. }
  1171. if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
  1172. unmap_kernel_range((unsigned long)cpu_addr, size);
  1173. vunmap(cpu_addr);
  1174. }
  1175. __iommu_remove_mapping(dev, handle, size);
  1176. __iommu_free_buffer(dev, pages, size, attrs);
  1177. }
  1178. static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
  1179. void *cpu_addr, dma_addr_t dma_addr,
  1180. size_t size, struct dma_attrs *attrs)
  1181. {
  1182. unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
  1183. struct page **pages = __iommu_get_pages(cpu_addr, attrs);
  1184. if (!pages)
  1185. return -ENXIO;
  1186. return sg_alloc_table_from_pages(sgt, pages, count, 0, size,
  1187. GFP_KERNEL);
  1188. }
  1189. /*
  1190. * Map a part of the scatter-gather list into contiguous io address space
  1191. */
  1192. static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
  1193. size_t size, dma_addr_t *handle,
  1194. enum dma_data_direction dir, struct dma_attrs *attrs,
  1195. bool is_coherent)
  1196. {
  1197. struct dma_iommu_mapping *mapping = dev->archdata.mapping;
  1198. dma_addr_t iova, iova_base;
  1199. int ret = 0;
  1200. unsigned int count;
  1201. struct scatterlist *s;
  1202. size = PAGE_ALIGN(size);
  1203. *handle = DMA_ERROR_CODE;
  1204. iova_base = iova = __alloc_iova(mapping, size);
  1205. if (iova == DMA_ERROR_CODE)
  1206. return -ENOMEM;
  1207. for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) {
  1208. phys_addr_t phys = page_to_phys(sg_page(s));
  1209. unsigned int len = PAGE_ALIGN(s->offset + s->length);
  1210. if (!is_coherent &&
  1211. !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
  1212. __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
  1213. ret = iommu_map(mapping->domain, iova, phys, len, 0);
  1214. if (ret < 0)
  1215. goto fail;
  1216. count += len >> PAGE_SHIFT;
  1217. iova += len;
  1218. }
  1219. *handle = iova_base;
  1220. return 0;
  1221. fail:
  1222. iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
  1223. __free_iova(mapping, iova_base, size);
  1224. return ret;
  1225. }
  1226. static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
  1227. enum dma_data_direction dir, struct dma_attrs *attrs,
  1228. bool is_coherent)
  1229. {
  1230. struct scatterlist *s = sg, *dma = sg, *start = sg;
  1231. int i, count = 0;
  1232. unsigned int offset = s->offset;
  1233. unsigned int size = s->offset + s->length;
  1234. unsigned int max = dma_get_max_seg_size(dev);
  1235. for (i = 1; i < nents; i++) {
  1236. s = sg_next(s);
  1237. s->dma_address = DMA_ERROR_CODE;
  1238. s->dma_length = 0;
  1239. if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
  1240. if (__map_sg_chunk(dev, start, size, &dma->dma_address,
  1241. dir, attrs, is_coherent) < 0)
  1242. goto bad_mapping;
  1243. dma->dma_address += offset;
  1244. dma->dma_length = size - offset;
  1245. size = offset = s->offset;
  1246. start = s;
  1247. dma = sg_next(dma);
  1248. count += 1;
  1249. }
  1250. size += s->length;
  1251. }
  1252. if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs,
  1253. is_coherent) < 0)
  1254. goto bad_mapping;
  1255. dma->dma_address += offset;
  1256. dma->dma_length = size - offset;
  1257. return count+1;
  1258. bad_mapping:
  1259. for_each_sg(sg, s, count, i)
  1260. __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
  1261. return 0;
  1262. }
  1263. /**
  1264. * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA
  1265. * @dev: valid struct device pointer
  1266. * @sg: list of buffers
  1267. * @nents: number of buffers to map
  1268. * @dir: DMA transfer direction
  1269. *
  1270. * Map a set of i/o coherent buffers described by scatterlist in streaming
  1271. * mode for DMA. The scatter gather list elements are merged together (if
  1272. * possible) and tagged with the appropriate dma address and length. They are
  1273. * obtained via sg_dma_{address,length}.
  1274. */
  1275. int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
  1276. int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
  1277. {
  1278. return __iommu_map_sg(dev, sg, nents, dir, attrs, true);
  1279. }
  1280. /**
  1281. * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
  1282. * @dev: valid struct device pointer
  1283. * @sg: list of buffers
  1284. * @nents: number of buffers to map
  1285. * @dir: DMA transfer direction
  1286. *
  1287. * Map a set of buffers described by scatterlist in streaming mode for DMA.
  1288. * The scatter gather list elements are merged together (if possible) and
  1289. * tagged with the appropriate dma address and length. They are obtained via
  1290. * sg_dma_{address,length}.
  1291. */
  1292. int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
  1293. int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
  1294. {
  1295. return __iommu_map_sg(dev, sg, nents, dir, attrs, false);
  1296. }
  1297. static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
  1298. int nents, enum dma_data_direction dir, struct dma_attrs *attrs,
  1299. bool is_coherent)
  1300. {
  1301. struct scatterlist *s;
  1302. int i;
  1303. for_each_sg(sg, s, nents, i) {
  1304. if (sg_dma_len(s))
  1305. __iommu_remove_mapping(dev, sg_dma_address(s),
  1306. sg_dma_len(s));
  1307. if (!is_coherent &&
  1308. !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
  1309. __dma_page_dev_to_cpu(sg_page(s), s->offset,
  1310. s->length, dir);
  1311. }
  1312. }
  1313. /**
  1314. * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
  1315. * @dev: valid struct device pointer
  1316. * @sg: list of buffers
  1317. * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
  1318. * @dir: DMA transfer direction (same as was passed to dma_map_sg)
  1319. *
  1320. * Unmap a set of streaming mode DMA translations. Again, CPU access
  1321. * rules concerning calls here are the same as for dma_unmap_single().
  1322. */
  1323. void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
  1324. int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
  1325. {
  1326. __iommu_unmap_sg(dev, sg, nents, dir, attrs, true);
  1327. }
  1328. /**
  1329. * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
  1330. * @dev: valid struct device pointer
  1331. * @sg: list of buffers
  1332. * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
  1333. * @dir: DMA transfer direction (same as was passed to dma_map_sg)
  1334. *
  1335. * Unmap a set of streaming mode DMA translations. Again, CPU access
  1336. * rules concerning calls here are the same as for dma_unmap_single().
  1337. */
  1338. void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
  1339. enum dma_data_direction dir, struct dma_attrs *attrs)
  1340. {
  1341. __iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
  1342. }
  1343. /**
  1344. * arm_iommu_sync_sg_for_cpu
  1345. * @dev: valid struct device pointer
  1346. * @sg: list of buffers
  1347. * @nents: number of buffers to map (returned from dma_map_sg)
  1348. * @dir: DMA transfer direction (same as was passed to dma_map_sg)
  1349. */
  1350. void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
  1351. int nents, enum dma_data_direction dir)
  1352. {
  1353. struct scatterlist *s;
  1354. int i;
  1355. for_each_sg(sg, s, nents, i)
  1356. __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
  1357. }
  1358. /**
  1359. * arm_iommu_sync_sg_for_device
  1360. * @dev: valid struct device pointer
  1361. * @sg: list of buffers
  1362. * @nents: number of buffers to map (returned from dma_map_sg)
  1363. * @dir: DMA transfer direction (same as was passed to dma_map_sg)
  1364. */
  1365. void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
  1366. int nents, enum dma_data_direction dir)
  1367. {
  1368. struct scatterlist *s;
  1369. int i;
  1370. for_each_sg(sg, s, nents, i)
  1371. __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
  1372. }
  1373. /**
  1374. * arm_coherent_iommu_map_page
  1375. * @dev: valid struct device pointer
  1376. * @page: page that buffer resides in
  1377. * @offset: offset into page for start of buffer
  1378. * @size: size of buffer to map
  1379. * @dir: DMA transfer direction
  1380. *
  1381. * Coherent IOMMU aware version of arm_dma_map_page()
  1382. */
  1383. static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page,
  1384. unsigned long offset, size_t size, enum dma_data_direction dir,
  1385. struct dma_attrs *attrs)
  1386. {
  1387. struct dma_iommu_mapping *mapping = dev->archdata.mapping;
  1388. dma_addr_t dma_addr;
  1389. int ret, len = PAGE_ALIGN(size + offset);
  1390. dma_addr = __alloc_iova(mapping, len);
  1391. if (dma_addr == DMA_ERROR_CODE)
  1392. return dma_addr;
  1393. ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, 0);
  1394. if (ret < 0)
  1395. goto fail;
  1396. return dma_addr + offset;
  1397. fail:
  1398. __free_iova(mapping, dma_addr, len);
  1399. return DMA_ERROR_CODE;
  1400. }
  1401. /**
  1402. * arm_iommu_map_page
  1403. * @dev: valid struct device pointer
  1404. * @page: page that buffer resides in
  1405. * @offset: offset into page for start of buffer
  1406. * @size: size of buffer to map
  1407. * @dir: DMA transfer direction
  1408. *
  1409. * IOMMU aware version of arm_dma_map_page()
  1410. */
  1411. static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
  1412. unsigned long offset, size_t size, enum dma_data_direction dir,
  1413. struct dma_attrs *attrs)
  1414. {
  1415. if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
  1416. __dma_page_cpu_to_dev(page, offset, size, dir);
  1417. return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs);
  1418. }
  1419. /**
  1420. * arm_coherent_iommu_unmap_page
  1421. * @dev: valid struct device pointer
  1422. * @handle: DMA address of buffer
  1423. * @size: size of buffer (same as passed to dma_map_page)
  1424. * @dir: DMA transfer direction (same as passed to dma_map_page)
  1425. *
  1426. * Coherent IOMMU aware version of arm_dma_unmap_page()
  1427. */
  1428. static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle,
  1429. size_t size, enum dma_data_direction dir,
  1430. struct dma_attrs *attrs)
  1431. {
  1432. struct dma_iommu_mapping *mapping = dev->archdata.mapping;
  1433. dma_addr_t iova = handle & PAGE_MASK;
  1434. int offset = handle & ~PAGE_MASK;
  1435. int len = PAGE_ALIGN(size + offset);
  1436. if (!iova)
  1437. return;
  1438. iommu_unmap(mapping->domain, iova, len);
  1439. __free_iova(mapping, iova, len);
  1440. }
  1441. /**
  1442. * arm_iommu_unmap_page
  1443. * @dev: valid struct device pointer
  1444. * @handle: DMA address of buffer
  1445. * @size: size of buffer (same as passed to dma_map_page)
  1446. * @dir: DMA transfer direction (same as passed to dma_map_page)
  1447. *
  1448. * IOMMU aware version of arm_dma_unmap_page()
  1449. */
  1450. static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
  1451. size_t size, enum dma_data_direction dir,
  1452. struct dma_attrs *attrs)
  1453. {
  1454. struct dma_iommu_mapping *mapping = dev->archdata.mapping;
  1455. dma_addr_t iova = handle & PAGE_MASK;
  1456. struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
  1457. int offset = handle & ~PAGE_MASK;
  1458. int len = PAGE_ALIGN(size + offset);
  1459. if (!iova)
  1460. return;
  1461. if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
  1462. __dma_page_dev_to_cpu(page, offset, size, dir);
  1463. iommu_unmap(mapping->domain, iova, len);
  1464. __free_iova(mapping, iova, len);
  1465. }
  1466. static void arm_iommu_sync_single_for_cpu(struct device *dev,
  1467. dma_addr_t handle, size_t size, enum dma_data_direction dir)
  1468. {
  1469. struct dma_iommu_mapping *mapping = dev->archdata.mapping;
  1470. dma_addr_t iova = handle & PAGE_MASK;
  1471. struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
  1472. unsigned int offset = handle & ~PAGE_MASK;
  1473. if (!iova)
  1474. return;
  1475. __dma_page_dev_to_cpu(page, offset, size, dir);
  1476. }
  1477. static void arm_iommu_sync_single_for_device(struct device *dev,
  1478. dma_addr_t handle, size_t size, enum dma_data_direction dir)
  1479. {
  1480. struct dma_iommu_mapping *mapping = dev->archdata.mapping;
  1481. dma_addr_t iova = handle & PAGE_MASK;
  1482. struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
  1483. unsigned int offset = handle & ~PAGE_MASK;
  1484. if (!iova)
  1485. return;
  1486. __dma_page_cpu_to_dev(page, offset, size, dir);
  1487. }
  1488. struct dma_map_ops iommu_ops = {
  1489. .alloc = arm_iommu_alloc_attrs,
  1490. .free = arm_iommu_free_attrs,
  1491. .mmap = arm_iommu_mmap_attrs,
  1492. .get_sgtable = arm_iommu_get_sgtable,
  1493. .map_page = arm_iommu_map_page,
  1494. .unmap_page = arm_iommu_unmap_page,
  1495. .sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
  1496. .sync_single_for_device = arm_iommu_sync_single_for_device,
  1497. .map_sg = arm_iommu_map_sg,
  1498. .unmap_sg = arm_iommu_unmap_sg,
  1499. .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
  1500. .sync_sg_for_device = arm_iommu_sync_sg_for_device,
  1501. .set_dma_mask = arm_dma_set_mask,
  1502. };
  1503. struct dma_map_ops iommu_coherent_ops = {
  1504. .alloc = arm_iommu_alloc_attrs,
  1505. .free = arm_iommu_free_attrs,
  1506. .mmap = arm_iommu_mmap_attrs,
  1507. .get_sgtable = arm_iommu_get_sgtable,
  1508. .map_page = arm_coherent_iommu_map_page,
  1509. .unmap_page = arm_coherent_iommu_unmap_page,
  1510. .map_sg = arm_coherent_iommu_map_sg,
  1511. .unmap_sg = arm_coherent_iommu_unmap_sg,
  1512. .set_dma_mask = arm_dma_set_mask,
  1513. };
  1514. /**
  1515. * arm_iommu_create_mapping
  1516. * @bus: pointer to the bus holding the client device (for IOMMU calls)
  1517. * @base: start address of the valid IO address space
  1518. * @size: size of the valid IO address space
  1519. * @order: accuracy of the IO addresses allocations
  1520. *
  1521. * Creates a mapping structure which holds information about used/unused
  1522. * IO address ranges, which is required to perform memory allocation and
  1523. * mapping with IOMMU aware functions.
  1524. *
  1525. * The client device need to be attached to the mapping with
  1526. * arm_iommu_attach_device function.
  1527. */
  1528. struct dma_iommu_mapping *
  1529. arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
  1530. int order)
  1531. {
  1532. unsigned int count = size >> (PAGE_SHIFT + order);
  1533. unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
  1534. struct dma_iommu_mapping *mapping;
  1535. int err = -ENOMEM;
  1536. if (!count)
  1537. return ERR_PTR(-EINVAL);
  1538. mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
  1539. if (!mapping)
  1540. goto err;
  1541. mapping->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
  1542. if (!mapping->bitmap)
  1543. goto err2;
  1544. mapping->base = base;
  1545. mapping->bits = BITS_PER_BYTE * bitmap_size;
  1546. mapping->order = order;
  1547. spin_lock_init(&mapping->lock);
  1548. mapping->domain = iommu_domain_alloc(bus);
  1549. if (!mapping->domain)
  1550. goto err3;
  1551. kref_init(&mapping->kref);
  1552. return mapping;
  1553. err3:
  1554. kfree(mapping->bitmap);
  1555. err2:
  1556. kfree(mapping);
  1557. err:
  1558. return ERR_PTR(err);
  1559. }
  1560. EXPORT_SYMBOL_GPL(arm_iommu_create_mapping);
  1561. static void release_iommu_mapping(struct kref *kref)
  1562. {
  1563. struct dma_iommu_mapping *mapping =
  1564. container_of(kref, struct dma_iommu_mapping, kref);
  1565. iommu_domain_free(mapping->domain);
  1566. kfree(mapping->bitmap);
  1567. kfree(mapping);
  1568. }
  1569. void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
  1570. {
  1571. if (mapping)
  1572. kref_put(&mapping->kref, release_iommu_mapping);
  1573. }
  1574. EXPORT_SYMBOL_GPL(arm_iommu_release_mapping);
  1575. /**
  1576. * arm_iommu_attach_device
  1577. * @dev: valid struct device pointer
  1578. * @mapping: io address space mapping structure (returned from
  1579. * arm_iommu_create_mapping)
  1580. *
  1581. * Attaches specified io address space mapping to the provided device,
  1582. * this replaces the dma operations (dma_map_ops pointer) with the
  1583. * IOMMU aware version. More than one client might be attached to
  1584. * the same io address space mapping.
  1585. */
  1586. int arm_iommu_attach_device(struct device *dev,
  1587. struct dma_iommu_mapping *mapping)
  1588. {
  1589. int err;
  1590. err = iommu_attach_device(mapping->domain, dev);
  1591. if (err)
  1592. return err;
  1593. kref_get(&mapping->kref);
  1594. dev->archdata.mapping = mapping;
  1595. set_dma_ops(dev, &iommu_ops);
  1596. pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
  1597. return 0;
  1598. }
  1599. EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
  1600. /**
  1601. * arm_iommu_detach_device
  1602. * @dev: valid struct device pointer
  1603. *
  1604. * Detaches the provided device from a previously attached map.
  1605. * This voids the dma operations (dma_map_ops pointer)
  1606. */
  1607. void arm_iommu_detach_device(struct device *dev)
  1608. {
  1609. struct dma_iommu_mapping *mapping;
  1610. mapping = to_dma_iommu_mapping(dev);
  1611. if (!mapping) {
  1612. dev_warn(dev, "Not attached\n");
  1613. return;
  1614. }
  1615. iommu_detach_device(mapping->domain, dev);
  1616. kref_put(&mapping->kref, release_iommu_mapping);
  1617. mapping = NULL;
  1618. set_dma_ops(dev, NULL);
  1619. pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
  1620. }
  1621. EXPORT_SYMBOL_GPL(arm_iommu_detach_device);
  1622. #endif