setup-sh73a0.c 24 KB

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  1. /*
  2. * sh73a0 processor support
  3. *
  4. * Copyright (C) 2010 Takashi Yoshii
  5. * Copyright (C) 2010 Magnus Damm
  6. * Copyright (C) 2008 Yoshihiro Shimoda
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20. */
  21. #include <linux/kernel.h>
  22. #include <linux/init.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/irq.h>
  25. #include <linux/irqchip.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/of_platform.h>
  28. #include <linux/delay.h>
  29. #include <linux/input.h>
  30. #include <linux/io.h>
  31. #include <linux/serial_sci.h>
  32. #include <linux/sh_dma.h>
  33. #include <linux/sh_intc.h>
  34. #include <linux/sh_timer.h>
  35. #include <linux/platform_data/sh_ipmmu.h>
  36. #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  37. #include <mach/dma-register.h>
  38. #include <mach/hardware.h>
  39. #include <mach/irqs.h>
  40. #include <mach/sh73a0.h>
  41. #include <mach/common.h>
  42. #include <asm/mach-types.h>
  43. #include <asm/mach/map.h>
  44. #include <asm/mach/arch.h>
  45. #include <asm/mach/time.h>
  46. static struct map_desc sh73a0_io_desc[] __initdata = {
  47. /* create a 1:1 entity map for 0xe6xxxxxx
  48. * used by CPGA, INTC and PFC.
  49. */
  50. {
  51. .virtual = 0xe6000000,
  52. .pfn = __phys_to_pfn(0xe6000000),
  53. .length = 256 << 20,
  54. .type = MT_DEVICE_NONSHARED
  55. },
  56. };
  57. void __init sh73a0_map_io(void)
  58. {
  59. iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
  60. }
  61. static struct resource sh73a0_pfc_resources[] = {
  62. [0] = {
  63. .start = 0xe6050000,
  64. .end = 0xe6057fff,
  65. .flags = IORESOURCE_MEM,
  66. },
  67. [1] = {
  68. .start = 0xe605801c,
  69. .end = 0xe6058027,
  70. .flags = IORESOURCE_MEM,
  71. }
  72. };
  73. static struct platform_device sh73a0_pfc_device = {
  74. .name = "pfc-sh73a0",
  75. .id = -1,
  76. .resource = sh73a0_pfc_resources,
  77. .num_resources = ARRAY_SIZE(sh73a0_pfc_resources),
  78. };
  79. void __init sh73a0_pinmux_init(void)
  80. {
  81. platform_device_register(&sh73a0_pfc_device);
  82. }
  83. static struct plat_sci_port scif0_platform_data = {
  84. .mapbase = 0xe6c40000,
  85. .flags = UPF_BOOT_AUTOCONF,
  86. .scscr = SCSCR_RE | SCSCR_TE,
  87. .scbrr_algo_id = SCBRR_ALGO_4,
  88. .type = PORT_SCIFA,
  89. .irqs = { gic_spi(72), gic_spi(72),
  90. gic_spi(72), gic_spi(72) },
  91. };
  92. static struct platform_device scif0_device = {
  93. .name = "sh-sci",
  94. .id = 0,
  95. .dev = {
  96. .platform_data = &scif0_platform_data,
  97. },
  98. };
  99. static struct plat_sci_port scif1_platform_data = {
  100. .mapbase = 0xe6c50000,
  101. .flags = UPF_BOOT_AUTOCONF,
  102. .scscr = SCSCR_RE | SCSCR_TE,
  103. .scbrr_algo_id = SCBRR_ALGO_4,
  104. .type = PORT_SCIFA,
  105. .irqs = { gic_spi(73), gic_spi(73),
  106. gic_spi(73), gic_spi(73) },
  107. };
  108. static struct platform_device scif1_device = {
  109. .name = "sh-sci",
  110. .id = 1,
  111. .dev = {
  112. .platform_data = &scif1_platform_data,
  113. },
  114. };
  115. static struct plat_sci_port scif2_platform_data = {
  116. .mapbase = 0xe6c60000,
  117. .flags = UPF_BOOT_AUTOCONF,
  118. .scscr = SCSCR_RE | SCSCR_TE,
  119. .scbrr_algo_id = SCBRR_ALGO_4,
  120. .type = PORT_SCIFA,
  121. .irqs = { gic_spi(74), gic_spi(74),
  122. gic_spi(74), gic_spi(74) },
  123. };
  124. static struct platform_device scif2_device = {
  125. .name = "sh-sci",
  126. .id = 2,
  127. .dev = {
  128. .platform_data = &scif2_platform_data,
  129. },
  130. };
  131. static struct plat_sci_port scif3_platform_data = {
  132. .mapbase = 0xe6c70000,
  133. .flags = UPF_BOOT_AUTOCONF,
  134. .scscr = SCSCR_RE | SCSCR_TE,
  135. .scbrr_algo_id = SCBRR_ALGO_4,
  136. .type = PORT_SCIFA,
  137. .irqs = { gic_spi(75), gic_spi(75),
  138. gic_spi(75), gic_spi(75) },
  139. };
  140. static struct platform_device scif3_device = {
  141. .name = "sh-sci",
  142. .id = 3,
  143. .dev = {
  144. .platform_data = &scif3_platform_data,
  145. },
  146. };
  147. static struct plat_sci_port scif4_platform_data = {
  148. .mapbase = 0xe6c80000,
  149. .flags = UPF_BOOT_AUTOCONF,
  150. .scscr = SCSCR_RE | SCSCR_TE,
  151. .scbrr_algo_id = SCBRR_ALGO_4,
  152. .type = PORT_SCIFA,
  153. .irqs = { gic_spi(78), gic_spi(78),
  154. gic_spi(78), gic_spi(78) },
  155. };
  156. static struct platform_device scif4_device = {
  157. .name = "sh-sci",
  158. .id = 4,
  159. .dev = {
  160. .platform_data = &scif4_platform_data,
  161. },
  162. };
  163. static struct plat_sci_port scif5_platform_data = {
  164. .mapbase = 0xe6cb0000,
  165. .flags = UPF_BOOT_AUTOCONF,
  166. .scscr = SCSCR_RE | SCSCR_TE,
  167. .scbrr_algo_id = SCBRR_ALGO_4,
  168. .type = PORT_SCIFA,
  169. .irqs = { gic_spi(79), gic_spi(79),
  170. gic_spi(79), gic_spi(79) },
  171. };
  172. static struct platform_device scif5_device = {
  173. .name = "sh-sci",
  174. .id = 5,
  175. .dev = {
  176. .platform_data = &scif5_platform_data,
  177. },
  178. };
  179. static struct plat_sci_port scif6_platform_data = {
  180. .mapbase = 0xe6cc0000,
  181. .flags = UPF_BOOT_AUTOCONF,
  182. .scscr = SCSCR_RE | SCSCR_TE,
  183. .scbrr_algo_id = SCBRR_ALGO_4,
  184. .type = PORT_SCIFA,
  185. .irqs = { gic_spi(156), gic_spi(156),
  186. gic_spi(156), gic_spi(156) },
  187. };
  188. static struct platform_device scif6_device = {
  189. .name = "sh-sci",
  190. .id = 6,
  191. .dev = {
  192. .platform_data = &scif6_platform_data,
  193. },
  194. };
  195. static struct plat_sci_port scif7_platform_data = {
  196. .mapbase = 0xe6cd0000,
  197. .flags = UPF_BOOT_AUTOCONF,
  198. .scscr = SCSCR_RE | SCSCR_TE,
  199. .scbrr_algo_id = SCBRR_ALGO_4,
  200. .type = PORT_SCIFA,
  201. .irqs = { gic_spi(143), gic_spi(143),
  202. gic_spi(143), gic_spi(143) },
  203. };
  204. static struct platform_device scif7_device = {
  205. .name = "sh-sci",
  206. .id = 7,
  207. .dev = {
  208. .platform_data = &scif7_platform_data,
  209. },
  210. };
  211. static struct plat_sci_port scif8_platform_data = {
  212. .mapbase = 0xe6c30000,
  213. .flags = UPF_BOOT_AUTOCONF,
  214. .scscr = SCSCR_RE | SCSCR_TE,
  215. .scbrr_algo_id = SCBRR_ALGO_4,
  216. .type = PORT_SCIFB,
  217. .irqs = { gic_spi(80), gic_spi(80),
  218. gic_spi(80), gic_spi(80) },
  219. };
  220. static struct platform_device scif8_device = {
  221. .name = "sh-sci",
  222. .id = 8,
  223. .dev = {
  224. .platform_data = &scif8_platform_data,
  225. },
  226. };
  227. static struct sh_timer_config cmt10_platform_data = {
  228. .name = "CMT10",
  229. .channel_offset = 0x10,
  230. .timer_bit = 0,
  231. .clockevent_rating = 125,
  232. .clocksource_rating = 125,
  233. };
  234. static struct resource cmt10_resources[] = {
  235. [0] = {
  236. .name = "CMT10",
  237. .start = 0xe6138010,
  238. .end = 0xe613801b,
  239. .flags = IORESOURCE_MEM,
  240. },
  241. [1] = {
  242. .start = gic_spi(65),
  243. .flags = IORESOURCE_IRQ,
  244. },
  245. };
  246. static struct platform_device cmt10_device = {
  247. .name = "sh_cmt",
  248. .id = 10,
  249. .dev = {
  250. .platform_data = &cmt10_platform_data,
  251. },
  252. .resource = cmt10_resources,
  253. .num_resources = ARRAY_SIZE(cmt10_resources),
  254. };
  255. /* TMU */
  256. static struct sh_timer_config tmu00_platform_data = {
  257. .name = "TMU00",
  258. .channel_offset = 0x4,
  259. .timer_bit = 0,
  260. .clockevent_rating = 200,
  261. };
  262. static struct resource tmu00_resources[] = {
  263. [0] = {
  264. .name = "TMU00",
  265. .start = 0xfff60008,
  266. .end = 0xfff60013,
  267. .flags = IORESOURCE_MEM,
  268. },
  269. [1] = {
  270. .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
  271. .flags = IORESOURCE_IRQ,
  272. },
  273. };
  274. static struct platform_device tmu00_device = {
  275. .name = "sh_tmu",
  276. .id = 0,
  277. .dev = {
  278. .platform_data = &tmu00_platform_data,
  279. },
  280. .resource = tmu00_resources,
  281. .num_resources = ARRAY_SIZE(tmu00_resources),
  282. };
  283. static struct sh_timer_config tmu01_platform_data = {
  284. .name = "TMU01",
  285. .channel_offset = 0x10,
  286. .timer_bit = 1,
  287. .clocksource_rating = 200,
  288. };
  289. static struct resource tmu01_resources[] = {
  290. [0] = {
  291. .name = "TMU01",
  292. .start = 0xfff60014,
  293. .end = 0xfff6001f,
  294. .flags = IORESOURCE_MEM,
  295. },
  296. [1] = {
  297. .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
  298. .flags = IORESOURCE_IRQ,
  299. },
  300. };
  301. static struct platform_device tmu01_device = {
  302. .name = "sh_tmu",
  303. .id = 1,
  304. .dev = {
  305. .platform_data = &tmu01_platform_data,
  306. },
  307. .resource = tmu01_resources,
  308. .num_resources = ARRAY_SIZE(tmu01_resources),
  309. };
  310. static struct resource i2c0_resources[] = {
  311. [0] = {
  312. .name = "IIC0",
  313. .start = 0xe6820000,
  314. .end = 0xe6820425 - 1,
  315. .flags = IORESOURCE_MEM,
  316. },
  317. [1] = {
  318. .start = gic_spi(167),
  319. .end = gic_spi(170),
  320. .flags = IORESOURCE_IRQ,
  321. },
  322. };
  323. static struct resource i2c1_resources[] = {
  324. [0] = {
  325. .name = "IIC1",
  326. .start = 0xe6822000,
  327. .end = 0xe6822425 - 1,
  328. .flags = IORESOURCE_MEM,
  329. },
  330. [1] = {
  331. .start = gic_spi(51),
  332. .end = gic_spi(54),
  333. .flags = IORESOURCE_IRQ,
  334. },
  335. };
  336. static struct resource i2c2_resources[] = {
  337. [0] = {
  338. .name = "IIC2",
  339. .start = 0xe6824000,
  340. .end = 0xe6824425 - 1,
  341. .flags = IORESOURCE_MEM,
  342. },
  343. [1] = {
  344. .start = gic_spi(171),
  345. .end = gic_spi(174),
  346. .flags = IORESOURCE_IRQ,
  347. },
  348. };
  349. static struct resource i2c3_resources[] = {
  350. [0] = {
  351. .name = "IIC3",
  352. .start = 0xe6826000,
  353. .end = 0xe6826425 - 1,
  354. .flags = IORESOURCE_MEM,
  355. },
  356. [1] = {
  357. .start = gic_spi(183),
  358. .end = gic_spi(186),
  359. .flags = IORESOURCE_IRQ,
  360. },
  361. };
  362. static struct resource i2c4_resources[] = {
  363. [0] = {
  364. .name = "IIC4",
  365. .start = 0xe6828000,
  366. .end = 0xe6828425 - 1,
  367. .flags = IORESOURCE_MEM,
  368. },
  369. [1] = {
  370. .start = gic_spi(187),
  371. .end = gic_spi(190),
  372. .flags = IORESOURCE_IRQ,
  373. },
  374. };
  375. static struct platform_device i2c0_device = {
  376. .name = "i2c-sh_mobile",
  377. .id = 0,
  378. .resource = i2c0_resources,
  379. .num_resources = ARRAY_SIZE(i2c0_resources),
  380. };
  381. static struct platform_device i2c1_device = {
  382. .name = "i2c-sh_mobile",
  383. .id = 1,
  384. .resource = i2c1_resources,
  385. .num_resources = ARRAY_SIZE(i2c1_resources),
  386. };
  387. static struct platform_device i2c2_device = {
  388. .name = "i2c-sh_mobile",
  389. .id = 2,
  390. .resource = i2c2_resources,
  391. .num_resources = ARRAY_SIZE(i2c2_resources),
  392. };
  393. static struct platform_device i2c3_device = {
  394. .name = "i2c-sh_mobile",
  395. .id = 3,
  396. .resource = i2c3_resources,
  397. .num_resources = ARRAY_SIZE(i2c3_resources),
  398. };
  399. static struct platform_device i2c4_device = {
  400. .name = "i2c-sh_mobile",
  401. .id = 4,
  402. .resource = i2c4_resources,
  403. .num_resources = ARRAY_SIZE(i2c4_resources),
  404. };
  405. static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
  406. {
  407. .slave_id = SHDMA_SLAVE_SCIF0_TX,
  408. .addr = 0xe6c40020,
  409. .chcr = CHCR_TX(XMIT_SZ_8BIT),
  410. .mid_rid = 0x21,
  411. }, {
  412. .slave_id = SHDMA_SLAVE_SCIF0_RX,
  413. .addr = 0xe6c40024,
  414. .chcr = CHCR_RX(XMIT_SZ_8BIT),
  415. .mid_rid = 0x22,
  416. }, {
  417. .slave_id = SHDMA_SLAVE_SCIF1_TX,
  418. .addr = 0xe6c50020,
  419. .chcr = CHCR_TX(XMIT_SZ_8BIT),
  420. .mid_rid = 0x25,
  421. }, {
  422. .slave_id = SHDMA_SLAVE_SCIF1_RX,
  423. .addr = 0xe6c50024,
  424. .chcr = CHCR_RX(XMIT_SZ_8BIT),
  425. .mid_rid = 0x26,
  426. }, {
  427. .slave_id = SHDMA_SLAVE_SCIF2_TX,
  428. .addr = 0xe6c60020,
  429. .chcr = CHCR_TX(XMIT_SZ_8BIT),
  430. .mid_rid = 0x29,
  431. }, {
  432. .slave_id = SHDMA_SLAVE_SCIF2_RX,
  433. .addr = 0xe6c60024,
  434. .chcr = CHCR_RX(XMIT_SZ_8BIT),
  435. .mid_rid = 0x2a,
  436. }, {
  437. .slave_id = SHDMA_SLAVE_SCIF3_TX,
  438. .addr = 0xe6c70020,
  439. .chcr = CHCR_TX(XMIT_SZ_8BIT),
  440. .mid_rid = 0x2d,
  441. }, {
  442. .slave_id = SHDMA_SLAVE_SCIF3_RX,
  443. .addr = 0xe6c70024,
  444. .chcr = CHCR_RX(XMIT_SZ_8BIT),
  445. .mid_rid = 0x2e,
  446. }, {
  447. .slave_id = SHDMA_SLAVE_SCIF4_TX,
  448. .addr = 0xe6c80020,
  449. .chcr = CHCR_TX(XMIT_SZ_8BIT),
  450. .mid_rid = 0x39,
  451. }, {
  452. .slave_id = SHDMA_SLAVE_SCIF4_RX,
  453. .addr = 0xe6c80024,
  454. .chcr = CHCR_RX(XMIT_SZ_8BIT),
  455. .mid_rid = 0x3a,
  456. }, {
  457. .slave_id = SHDMA_SLAVE_SCIF5_TX,
  458. .addr = 0xe6cb0020,
  459. .chcr = CHCR_TX(XMIT_SZ_8BIT),
  460. .mid_rid = 0x35,
  461. }, {
  462. .slave_id = SHDMA_SLAVE_SCIF5_RX,
  463. .addr = 0xe6cb0024,
  464. .chcr = CHCR_RX(XMIT_SZ_8BIT),
  465. .mid_rid = 0x36,
  466. }, {
  467. .slave_id = SHDMA_SLAVE_SCIF6_TX,
  468. .addr = 0xe6cc0020,
  469. .chcr = CHCR_TX(XMIT_SZ_8BIT),
  470. .mid_rid = 0x1d,
  471. }, {
  472. .slave_id = SHDMA_SLAVE_SCIF6_RX,
  473. .addr = 0xe6cc0024,
  474. .chcr = CHCR_RX(XMIT_SZ_8BIT),
  475. .mid_rid = 0x1e,
  476. }, {
  477. .slave_id = SHDMA_SLAVE_SCIF7_TX,
  478. .addr = 0xe6cd0020,
  479. .chcr = CHCR_TX(XMIT_SZ_8BIT),
  480. .mid_rid = 0x19,
  481. }, {
  482. .slave_id = SHDMA_SLAVE_SCIF7_RX,
  483. .addr = 0xe6cd0024,
  484. .chcr = CHCR_RX(XMIT_SZ_8BIT),
  485. .mid_rid = 0x1a,
  486. }, {
  487. .slave_id = SHDMA_SLAVE_SCIF8_TX,
  488. .addr = 0xe6c30040,
  489. .chcr = CHCR_TX(XMIT_SZ_8BIT),
  490. .mid_rid = 0x3d,
  491. }, {
  492. .slave_id = SHDMA_SLAVE_SCIF8_RX,
  493. .addr = 0xe6c30060,
  494. .chcr = CHCR_RX(XMIT_SZ_8BIT),
  495. .mid_rid = 0x3e,
  496. }, {
  497. .slave_id = SHDMA_SLAVE_SDHI0_TX,
  498. .addr = 0xee100030,
  499. .chcr = CHCR_TX(XMIT_SZ_16BIT),
  500. .mid_rid = 0xc1,
  501. }, {
  502. .slave_id = SHDMA_SLAVE_SDHI0_RX,
  503. .addr = 0xee100030,
  504. .chcr = CHCR_RX(XMIT_SZ_16BIT),
  505. .mid_rid = 0xc2,
  506. }, {
  507. .slave_id = SHDMA_SLAVE_SDHI1_TX,
  508. .addr = 0xee120030,
  509. .chcr = CHCR_TX(XMIT_SZ_16BIT),
  510. .mid_rid = 0xc9,
  511. }, {
  512. .slave_id = SHDMA_SLAVE_SDHI1_RX,
  513. .addr = 0xee120030,
  514. .chcr = CHCR_RX(XMIT_SZ_16BIT),
  515. .mid_rid = 0xca,
  516. }, {
  517. .slave_id = SHDMA_SLAVE_SDHI2_TX,
  518. .addr = 0xee140030,
  519. .chcr = CHCR_TX(XMIT_SZ_16BIT),
  520. .mid_rid = 0xcd,
  521. }, {
  522. .slave_id = SHDMA_SLAVE_SDHI2_RX,
  523. .addr = 0xee140030,
  524. .chcr = CHCR_RX(XMIT_SZ_16BIT),
  525. .mid_rid = 0xce,
  526. }, {
  527. .slave_id = SHDMA_SLAVE_MMCIF_TX,
  528. .addr = 0xe6bd0034,
  529. .chcr = CHCR_TX(XMIT_SZ_32BIT),
  530. .mid_rid = 0xd1,
  531. }, {
  532. .slave_id = SHDMA_SLAVE_MMCIF_RX,
  533. .addr = 0xe6bd0034,
  534. .chcr = CHCR_RX(XMIT_SZ_32BIT),
  535. .mid_rid = 0xd2,
  536. },
  537. };
  538. #define DMAE_CHANNEL(_offset) \
  539. { \
  540. .offset = _offset - 0x20, \
  541. .dmars = _offset - 0x20 + 0x40, \
  542. }
  543. static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
  544. DMAE_CHANNEL(0x8000),
  545. DMAE_CHANNEL(0x8080),
  546. DMAE_CHANNEL(0x8100),
  547. DMAE_CHANNEL(0x8180),
  548. DMAE_CHANNEL(0x8200),
  549. DMAE_CHANNEL(0x8280),
  550. DMAE_CHANNEL(0x8300),
  551. DMAE_CHANNEL(0x8380),
  552. DMAE_CHANNEL(0x8400),
  553. DMAE_CHANNEL(0x8480),
  554. DMAE_CHANNEL(0x8500),
  555. DMAE_CHANNEL(0x8580),
  556. DMAE_CHANNEL(0x8600),
  557. DMAE_CHANNEL(0x8680),
  558. DMAE_CHANNEL(0x8700),
  559. DMAE_CHANNEL(0x8780),
  560. DMAE_CHANNEL(0x8800),
  561. DMAE_CHANNEL(0x8880),
  562. DMAE_CHANNEL(0x8900),
  563. DMAE_CHANNEL(0x8980),
  564. };
  565. static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
  566. .slave = sh73a0_dmae_slaves,
  567. .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves),
  568. .channel = sh73a0_dmae_channels,
  569. .channel_num = ARRAY_SIZE(sh73a0_dmae_channels),
  570. .ts_low_shift = TS_LOW_SHIFT,
  571. .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
  572. .ts_high_shift = TS_HI_SHIFT,
  573. .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
  574. .ts_shift = dma_ts_shift,
  575. .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
  576. .dmaor_init = DMAOR_DME,
  577. };
  578. static struct resource sh73a0_dmae_resources[] = {
  579. {
  580. /* Registers including DMAOR and channels including DMARSx */
  581. .start = 0xfe000020,
  582. .end = 0xfe008a00 - 1,
  583. .flags = IORESOURCE_MEM,
  584. },
  585. {
  586. .name = "error_irq",
  587. .start = gic_spi(129),
  588. .end = gic_spi(129),
  589. .flags = IORESOURCE_IRQ,
  590. },
  591. {
  592. /* IRQ for channels 0-19 */
  593. .start = gic_spi(109),
  594. .end = gic_spi(128),
  595. .flags = IORESOURCE_IRQ,
  596. },
  597. };
  598. static struct platform_device dma0_device = {
  599. .name = "sh-dma-engine",
  600. .id = 0,
  601. .resource = sh73a0_dmae_resources,
  602. .num_resources = ARRAY_SIZE(sh73a0_dmae_resources),
  603. .dev = {
  604. .platform_data = &sh73a0_dmae_platform_data,
  605. },
  606. };
  607. /* MPDMAC */
  608. static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
  609. {
  610. .slave_id = SHDMA_SLAVE_FSI2A_RX,
  611. .addr = 0xec230020,
  612. .chcr = CHCR_RX(XMIT_SZ_32BIT),
  613. .mid_rid = 0xd6, /* CHECK ME */
  614. }, {
  615. .slave_id = SHDMA_SLAVE_FSI2A_TX,
  616. .addr = 0xec230024,
  617. .chcr = CHCR_TX(XMIT_SZ_32BIT),
  618. .mid_rid = 0xd5, /* CHECK ME */
  619. }, {
  620. .slave_id = SHDMA_SLAVE_FSI2C_RX,
  621. .addr = 0xec230060,
  622. .chcr = CHCR_RX(XMIT_SZ_32BIT),
  623. .mid_rid = 0xda, /* CHECK ME */
  624. }, {
  625. .slave_id = SHDMA_SLAVE_FSI2C_TX,
  626. .addr = 0xec230064,
  627. .chcr = CHCR_TX(XMIT_SZ_32BIT),
  628. .mid_rid = 0xd9, /* CHECK ME */
  629. }, {
  630. .slave_id = SHDMA_SLAVE_FSI2B_RX,
  631. .addr = 0xec240020,
  632. .chcr = CHCR_RX(XMIT_SZ_32BIT),
  633. .mid_rid = 0x8e, /* CHECK ME */
  634. }, {
  635. .slave_id = SHDMA_SLAVE_FSI2B_TX,
  636. .addr = 0xec240024,
  637. .chcr = CHCR_RX(XMIT_SZ_32BIT),
  638. .mid_rid = 0x8d, /* CHECK ME */
  639. }, {
  640. .slave_id = SHDMA_SLAVE_FSI2D_RX,
  641. .addr = 0xec240060,
  642. .chcr = CHCR_RX(XMIT_SZ_32BIT),
  643. .mid_rid = 0x9a, /* CHECK ME */
  644. },
  645. };
  646. #define MPDMA_CHANNEL(a, b, c) \
  647. { \
  648. .offset = a, \
  649. .dmars = b, \
  650. .dmars_bit = c, \
  651. .chclr_offset = (0x220 - 0x20) + a \
  652. }
  653. static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
  654. MPDMA_CHANNEL(0x00, 0, 0),
  655. MPDMA_CHANNEL(0x10, 0, 8),
  656. MPDMA_CHANNEL(0x20, 4, 0),
  657. MPDMA_CHANNEL(0x30, 4, 8),
  658. MPDMA_CHANNEL(0x50, 8, 0),
  659. MPDMA_CHANNEL(0x70, 8, 8),
  660. };
  661. static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
  662. .slave = sh73a0_mpdma_slaves,
  663. .slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves),
  664. .channel = sh73a0_mpdma_channels,
  665. .channel_num = ARRAY_SIZE(sh73a0_mpdma_channels),
  666. .ts_low_shift = TS_LOW_SHIFT,
  667. .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
  668. .ts_high_shift = TS_HI_SHIFT,
  669. .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
  670. .ts_shift = dma_ts_shift,
  671. .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
  672. .dmaor_init = DMAOR_DME,
  673. .chclr_present = 1,
  674. };
  675. /* Resource order important! */
  676. static struct resource sh73a0_mpdma_resources[] = {
  677. {
  678. /* Channel registers and DMAOR */
  679. .start = 0xec618020,
  680. .end = 0xec61828f,
  681. .flags = IORESOURCE_MEM,
  682. },
  683. {
  684. /* DMARSx */
  685. .start = 0xec619000,
  686. .end = 0xec61900b,
  687. .flags = IORESOURCE_MEM,
  688. },
  689. {
  690. .name = "error_irq",
  691. .start = gic_spi(181),
  692. .end = gic_spi(181),
  693. .flags = IORESOURCE_IRQ,
  694. },
  695. {
  696. /* IRQ for channels 0-5 */
  697. .start = gic_spi(175),
  698. .end = gic_spi(180),
  699. .flags = IORESOURCE_IRQ,
  700. },
  701. };
  702. static struct platform_device mpdma0_device = {
  703. .name = "sh-dma-engine",
  704. .id = 1,
  705. .resource = sh73a0_mpdma_resources,
  706. .num_resources = ARRAY_SIZE(sh73a0_mpdma_resources),
  707. .dev = {
  708. .platform_data = &sh73a0_mpdma_platform_data,
  709. },
  710. };
  711. static struct resource pmu_resources[] = {
  712. [0] = {
  713. .start = gic_spi(55),
  714. .end = gic_spi(55),
  715. .flags = IORESOURCE_IRQ,
  716. },
  717. [1] = {
  718. .start = gic_spi(56),
  719. .end = gic_spi(56),
  720. .flags = IORESOURCE_IRQ,
  721. },
  722. };
  723. static struct platform_device pmu_device = {
  724. .name = "arm-pmu",
  725. .id = -1,
  726. .num_resources = ARRAY_SIZE(pmu_resources),
  727. .resource = pmu_resources,
  728. };
  729. /* an IPMMU module for ICB */
  730. static struct resource ipmmu_resources[] = {
  731. [0] = {
  732. .name = "IPMMU",
  733. .start = 0xfe951000,
  734. .end = 0xfe9510ff,
  735. .flags = IORESOURCE_MEM,
  736. },
  737. };
  738. static const char * const ipmmu_dev_names[] = {
  739. "sh_mobile_lcdc_fb.0",
  740. };
  741. static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
  742. .dev_names = ipmmu_dev_names,
  743. .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
  744. };
  745. static struct platform_device ipmmu_device = {
  746. .name = "ipmmu",
  747. .id = -1,
  748. .dev = {
  749. .platform_data = &ipmmu_platform_data,
  750. },
  751. .resource = ipmmu_resources,
  752. .num_resources = ARRAY_SIZE(ipmmu_resources),
  753. };
  754. static struct renesas_intc_irqpin_config irqpin0_platform_data = {
  755. .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
  756. };
  757. static struct resource irqpin0_resources[] = {
  758. DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
  759. DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
  760. DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
  761. DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
  762. DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
  763. DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
  764. DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
  765. DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
  766. DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
  767. DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
  768. DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
  769. DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
  770. DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
  771. };
  772. static struct platform_device irqpin0_device = {
  773. .name = "renesas_intc_irqpin",
  774. .id = 0,
  775. .resource = irqpin0_resources,
  776. .num_resources = ARRAY_SIZE(irqpin0_resources),
  777. .dev = {
  778. .platform_data = &irqpin0_platform_data,
  779. },
  780. };
  781. static struct renesas_intc_irqpin_config irqpin1_platform_data = {
  782. .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
  783. .control_parent = true, /* Disable spurious IRQ10 */
  784. };
  785. static struct resource irqpin1_resources[] = {
  786. DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
  787. DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
  788. DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
  789. DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
  790. DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
  791. DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
  792. DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
  793. DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
  794. DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
  795. DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
  796. DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
  797. DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
  798. DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
  799. };
  800. static struct platform_device irqpin1_device = {
  801. .name = "renesas_intc_irqpin",
  802. .id = 1,
  803. .resource = irqpin1_resources,
  804. .num_resources = ARRAY_SIZE(irqpin1_resources),
  805. .dev = {
  806. .platform_data = &irqpin1_platform_data,
  807. },
  808. };
  809. static struct renesas_intc_irqpin_config irqpin2_platform_data = {
  810. .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
  811. };
  812. static struct resource irqpin2_resources[] = {
  813. DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
  814. DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
  815. DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
  816. DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
  817. DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
  818. DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
  819. DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
  820. DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
  821. DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
  822. DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
  823. DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
  824. DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
  825. DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
  826. };
  827. static struct platform_device irqpin2_device = {
  828. .name = "renesas_intc_irqpin",
  829. .id = 2,
  830. .resource = irqpin2_resources,
  831. .num_resources = ARRAY_SIZE(irqpin2_resources),
  832. .dev = {
  833. .platform_data = &irqpin2_platform_data,
  834. },
  835. };
  836. static struct renesas_intc_irqpin_config irqpin3_platform_data = {
  837. .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
  838. };
  839. static struct resource irqpin3_resources[] = {
  840. DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
  841. DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
  842. DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
  843. DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
  844. DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
  845. DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
  846. DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
  847. DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
  848. DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
  849. DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
  850. DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
  851. DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
  852. DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
  853. };
  854. static struct platform_device irqpin3_device = {
  855. .name = "renesas_intc_irqpin",
  856. .id = 3,
  857. .resource = irqpin3_resources,
  858. .num_resources = ARRAY_SIZE(irqpin3_resources),
  859. .dev = {
  860. .platform_data = &irqpin3_platform_data,
  861. },
  862. };
  863. static struct platform_device *sh73a0_devices_dt[] __initdata = {
  864. &scif0_device,
  865. &scif1_device,
  866. &scif2_device,
  867. &scif3_device,
  868. &scif4_device,
  869. &scif5_device,
  870. &scif6_device,
  871. &scif7_device,
  872. &scif8_device,
  873. &cmt10_device,
  874. };
  875. static struct platform_device *sh73a0_early_devices[] __initdata = {
  876. &tmu00_device,
  877. &tmu01_device,
  878. &ipmmu_device,
  879. };
  880. static struct platform_device *sh73a0_late_devices[] __initdata = {
  881. &i2c0_device,
  882. &i2c1_device,
  883. &i2c2_device,
  884. &i2c3_device,
  885. &i2c4_device,
  886. &dma0_device,
  887. &mpdma0_device,
  888. &pmu_device,
  889. &irqpin0_device,
  890. &irqpin1_device,
  891. &irqpin2_device,
  892. &irqpin3_device,
  893. };
  894. #define SRCR2 IOMEM(0xe61580b0)
  895. void __init sh73a0_add_standard_devices(void)
  896. {
  897. /* Clear software reset bit on SY-DMAC module */
  898. __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
  899. platform_add_devices(sh73a0_devices_dt,
  900. ARRAY_SIZE(sh73a0_devices_dt));
  901. platform_add_devices(sh73a0_early_devices,
  902. ARRAY_SIZE(sh73a0_early_devices));
  903. platform_add_devices(sh73a0_late_devices,
  904. ARRAY_SIZE(sh73a0_late_devices));
  905. }
  906. /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
  907. void __init __weak sh73a0_register_twd(void) { }
  908. void __init sh73a0_earlytimer_init(void)
  909. {
  910. sh73a0_clock_init();
  911. shmobile_earlytimer_init();
  912. sh73a0_register_twd();
  913. }
  914. void __init sh73a0_add_early_devices(void)
  915. {
  916. early_platform_add_devices(sh73a0_devices_dt,
  917. ARRAY_SIZE(sh73a0_devices_dt));
  918. early_platform_add_devices(sh73a0_early_devices,
  919. ARRAY_SIZE(sh73a0_early_devices));
  920. /* setup early console here as well */
  921. shmobile_setup_console();
  922. }
  923. #ifdef CONFIG_USE_OF
  924. void __init sh73a0_init_delay(void)
  925. {
  926. shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
  927. }
  928. static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
  929. {},
  930. };
  931. void __init sh73a0_add_standard_devices_dt(void)
  932. {
  933. /* clocks are setup late during boot in the case of DT */
  934. sh73a0_clock_init();
  935. platform_add_devices(sh73a0_devices_dt,
  936. ARRAY_SIZE(sh73a0_devices_dt));
  937. of_platform_populate(NULL, of_default_bus_match_table,
  938. sh73a0_auxdata_lookup, NULL);
  939. }
  940. static const char *sh73a0_boards_compat_dt[] __initdata = {
  941. "renesas,sh73a0",
  942. NULL,
  943. };
  944. DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
  945. .smp = smp_ops(sh73a0_smp_ops),
  946. .map_io = sh73a0_map_io,
  947. .init_early = sh73a0_init_delay,
  948. .nr_irqs = NR_IRQS_LEGACY,
  949. .init_irq = irqchip_init,
  950. .init_machine = sh73a0_add_standard_devices_dt,
  951. .dt_compat = sh73a0_boards_compat_dt,
  952. MACHINE_END
  953. #endif /* CONFIG_USE_OF */