omap_hwmod_33xx_data.c 84 KB

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  1. /*
  2. * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
  3. *
  4. * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This file is automatically generated from the AM33XX hardware databases.
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation version 2.
  10. *
  11. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12. * kind, whether express or implied; without even the implied warranty
  13. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/i2c-omap.h>
  17. #include "omap_hwmod.h"
  18. #include <linux/platform_data/gpio-omap.h>
  19. #include <linux/platform_data/spi-omap2-mcspi.h>
  20. #include "omap_hwmod_common_data.h"
  21. #include "control.h"
  22. #include "cm33xx.h"
  23. #include "prm33xx.h"
  24. #include "prm-regbits-33xx.h"
  25. #include "i2c.h"
  26. #include "mmc.h"
  27. #include "wd_timer.h"
  28. /*
  29. * IP blocks
  30. */
  31. /*
  32. * 'emif_fw' class
  33. * instance(s): emif_fw
  34. */
  35. static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
  36. .name = "emif_fw",
  37. };
  38. /* emif_fw */
  39. static struct omap_hwmod am33xx_emif_fw_hwmod = {
  40. .name = "emif_fw",
  41. .class = &am33xx_emif_fw_hwmod_class,
  42. .clkdm_name = "l4fw_clkdm",
  43. .main_clk = "l4fw_gclk",
  44. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  45. .prcm = {
  46. .omap4 = {
  47. .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
  48. .modulemode = MODULEMODE_SWCTRL,
  49. },
  50. },
  51. };
  52. /*
  53. * 'emif' class
  54. * instance(s): emif
  55. */
  56. static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
  57. .rev_offs = 0x0000,
  58. };
  59. static struct omap_hwmod_class am33xx_emif_hwmod_class = {
  60. .name = "emif",
  61. .sysc = &am33xx_emif_sysc,
  62. };
  63. static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
  64. { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
  65. { .irq = -1 },
  66. };
  67. /* emif */
  68. static struct omap_hwmod am33xx_emif_hwmod = {
  69. .name = "emif",
  70. .class = &am33xx_emif_hwmod_class,
  71. .clkdm_name = "l3_clkdm",
  72. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  73. .mpu_irqs = am33xx_emif_irqs,
  74. .main_clk = "dpll_ddr_m2_div2_ck",
  75. .prcm = {
  76. .omap4 = {
  77. .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
  78. .modulemode = MODULEMODE_SWCTRL,
  79. },
  80. },
  81. };
  82. /*
  83. * 'l3' class
  84. * instance(s): l3_main, l3_s, l3_instr
  85. */
  86. static struct omap_hwmod_class am33xx_l3_hwmod_class = {
  87. .name = "l3",
  88. };
  89. /* l3_main (l3_fast) */
  90. static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
  91. { .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
  92. { .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
  93. { .irq = -1 },
  94. };
  95. static struct omap_hwmod am33xx_l3_main_hwmod = {
  96. .name = "l3_main",
  97. .class = &am33xx_l3_hwmod_class,
  98. .clkdm_name = "l3_clkdm",
  99. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  100. .mpu_irqs = am33xx_l3_main_irqs,
  101. .main_clk = "l3_gclk",
  102. .prcm = {
  103. .omap4 = {
  104. .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
  105. .modulemode = MODULEMODE_SWCTRL,
  106. },
  107. },
  108. };
  109. /* l3_s */
  110. static struct omap_hwmod am33xx_l3_s_hwmod = {
  111. .name = "l3_s",
  112. .class = &am33xx_l3_hwmod_class,
  113. .clkdm_name = "l3s_clkdm",
  114. };
  115. /* l3_instr */
  116. static struct omap_hwmod am33xx_l3_instr_hwmod = {
  117. .name = "l3_instr",
  118. .class = &am33xx_l3_hwmod_class,
  119. .clkdm_name = "l3_clkdm",
  120. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  121. .main_clk = "l3_gclk",
  122. .prcm = {
  123. .omap4 = {
  124. .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
  125. .modulemode = MODULEMODE_SWCTRL,
  126. },
  127. },
  128. };
  129. /*
  130. * 'l4' class
  131. * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
  132. */
  133. static struct omap_hwmod_class am33xx_l4_hwmod_class = {
  134. .name = "l4",
  135. };
  136. /* l4_ls */
  137. static struct omap_hwmod am33xx_l4_ls_hwmod = {
  138. .name = "l4_ls",
  139. .class = &am33xx_l4_hwmod_class,
  140. .clkdm_name = "l4ls_clkdm",
  141. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  142. .main_clk = "l4ls_gclk",
  143. .prcm = {
  144. .omap4 = {
  145. .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
  146. .modulemode = MODULEMODE_SWCTRL,
  147. },
  148. },
  149. };
  150. /* l4_hs */
  151. static struct omap_hwmod am33xx_l4_hs_hwmod = {
  152. .name = "l4_hs",
  153. .class = &am33xx_l4_hwmod_class,
  154. .clkdm_name = "l4hs_clkdm",
  155. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  156. .main_clk = "l4hs_gclk",
  157. .prcm = {
  158. .omap4 = {
  159. .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
  160. .modulemode = MODULEMODE_SWCTRL,
  161. },
  162. },
  163. };
  164. /* l4_wkup */
  165. static struct omap_hwmod am33xx_l4_wkup_hwmod = {
  166. .name = "l4_wkup",
  167. .class = &am33xx_l4_hwmod_class,
  168. .clkdm_name = "l4_wkup_clkdm",
  169. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  170. .prcm = {
  171. .omap4 = {
  172. .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
  173. .modulemode = MODULEMODE_SWCTRL,
  174. },
  175. },
  176. };
  177. /* l4_fw */
  178. static struct omap_hwmod am33xx_l4_fw_hwmod = {
  179. .name = "l4_fw",
  180. .class = &am33xx_l4_hwmod_class,
  181. .clkdm_name = "l4fw_clkdm",
  182. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  183. .prcm = {
  184. .omap4 = {
  185. .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
  186. .modulemode = MODULEMODE_SWCTRL,
  187. },
  188. },
  189. };
  190. /*
  191. * 'mpu' class
  192. */
  193. static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
  194. .name = "mpu",
  195. };
  196. /* mpu */
  197. static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
  198. { .name = "emuint", .irq = 0 + OMAP_INTC_START, },
  199. { .name = "commtx", .irq = 1 + OMAP_INTC_START, },
  200. { .name = "commrx", .irq = 2 + OMAP_INTC_START, },
  201. { .name = "bench", .irq = 3 + OMAP_INTC_START, },
  202. { .irq = -1 },
  203. };
  204. static struct omap_hwmod am33xx_mpu_hwmod = {
  205. .name = "mpu",
  206. .class = &am33xx_mpu_hwmod_class,
  207. .clkdm_name = "mpu_clkdm",
  208. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  209. .mpu_irqs = am33xx_mpu_irqs,
  210. .main_clk = "dpll_mpu_m2_ck",
  211. .prcm = {
  212. .omap4 = {
  213. .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
  214. .modulemode = MODULEMODE_SWCTRL,
  215. },
  216. },
  217. };
  218. /*
  219. * 'wakeup m3' class
  220. * Wakeup controller sub-system under wakeup domain
  221. */
  222. static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
  223. .name = "wkup_m3",
  224. };
  225. static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
  226. { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
  227. };
  228. static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
  229. { .name = "txev", .irq = 78 + OMAP_INTC_START, },
  230. { .irq = -1 },
  231. };
  232. /* wkup_m3 */
  233. static struct omap_hwmod am33xx_wkup_m3_hwmod = {
  234. .name = "wkup_m3",
  235. .class = &am33xx_wkup_m3_hwmod_class,
  236. .clkdm_name = "l4_wkup_aon_clkdm",
  237. /* Keep hardreset asserted */
  238. .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
  239. .mpu_irqs = am33xx_wkup_m3_irqs,
  240. .main_clk = "dpll_core_m4_div2_ck",
  241. .prcm = {
  242. .omap4 = {
  243. .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
  244. .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
  245. .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
  246. .modulemode = MODULEMODE_SWCTRL,
  247. },
  248. },
  249. .rst_lines = am33xx_wkup_m3_resets,
  250. .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
  251. };
  252. /*
  253. * 'pru-icss' class
  254. * Programmable Real-Time Unit and Industrial Communication Subsystem
  255. */
  256. static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
  257. .name = "pruss",
  258. };
  259. static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
  260. { .name = "pruss", .rst_shift = 1 },
  261. };
  262. static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
  263. { .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
  264. { .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
  265. { .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
  266. { .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
  267. { .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
  268. { .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
  269. { .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
  270. { .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
  271. { .irq = -1 },
  272. };
  273. /* pru-icss */
  274. /* Pseudo hwmod for reset control purpose only */
  275. static struct omap_hwmod am33xx_pruss_hwmod = {
  276. .name = "pruss",
  277. .class = &am33xx_pruss_hwmod_class,
  278. .clkdm_name = "pruss_ocp_clkdm",
  279. .mpu_irqs = am33xx_pruss_irqs,
  280. .main_clk = "pruss_ocp_gclk",
  281. .prcm = {
  282. .omap4 = {
  283. .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
  284. .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
  285. .modulemode = MODULEMODE_SWCTRL,
  286. },
  287. },
  288. .rst_lines = am33xx_pruss_resets,
  289. .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
  290. };
  291. /* gfx */
  292. /* Pseudo hwmod for reset control purpose only */
  293. static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
  294. .name = "gfx",
  295. };
  296. static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
  297. { .name = "gfx", .rst_shift = 0 },
  298. };
  299. static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
  300. { .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
  301. { .irq = -1 },
  302. };
  303. static struct omap_hwmod am33xx_gfx_hwmod = {
  304. .name = "gfx",
  305. .class = &am33xx_gfx_hwmod_class,
  306. .clkdm_name = "gfx_l3_clkdm",
  307. .mpu_irqs = am33xx_gfx_irqs,
  308. .main_clk = "gfx_fck_div_ck",
  309. .prcm = {
  310. .omap4 = {
  311. .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
  312. .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
  313. .modulemode = MODULEMODE_SWCTRL,
  314. },
  315. },
  316. .rst_lines = am33xx_gfx_resets,
  317. .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
  318. };
  319. /*
  320. * 'prcm' class
  321. * power and reset manager (whole prcm infrastructure)
  322. */
  323. static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
  324. .name = "prcm",
  325. };
  326. /* prcm */
  327. static struct omap_hwmod am33xx_prcm_hwmod = {
  328. .name = "prcm",
  329. .class = &am33xx_prcm_hwmod_class,
  330. .clkdm_name = "l4_wkup_clkdm",
  331. };
  332. /*
  333. * 'adc/tsc' class
  334. * TouchScreen Controller (Anolog-To-Digital Converter)
  335. */
  336. static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
  337. .rev_offs = 0x00,
  338. .sysc_offs = 0x10,
  339. .sysc_flags = SYSC_HAS_SIDLEMODE,
  340. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  341. SIDLE_SMART_WKUP),
  342. .sysc_fields = &omap_hwmod_sysc_type2,
  343. };
  344. static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
  345. .name = "adc_tsc",
  346. .sysc = &am33xx_adc_tsc_sysc,
  347. };
  348. static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
  349. { .irq = 16 + OMAP_INTC_START, },
  350. { .irq = -1 },
  351. };
  352. static struct omap_hwmod am33xx_adc_tsc_hwmod = {
  353. .name = "adc_tsc",
  354. .class = &am33xx_adc_tsc_hwmod_class,
  355. .clkdm_name = "l4_wkup_clkdm",
  356. .mpu_irqs = am33xx_adc_tsc_irqs,
  357. .main_clk = "adc_tsc_fck",
  358. .prcm = {
  359. .omap4 = {
  360. .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
  361. .modulemode = MODULEMODE_SWCTRL,
  362. },
  363. },
  364. };
  365. /*
  366. * Modules omap_hwmod structures
  367. *
  368. * The following IPs are excluded for the moment because:
  369. * - They do not need an explicit SW control using omap_hwmod API.
  370. * - They still need to be validated with the driver
  371. * properly adapted to omap_hwmod / omap_device
  372. *
  373. * - cEFUSE (doesn't fall under any ocp_if)
  374. * - clkdiv32k
  375. * - debugss
  376. * - ocp watch point
  377. */
  378. #if 0
  379. /*
  380. * 'cefuse' class
  381. */
  382. static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
  383. .name = "cefuse",
  384. };
  385. static struct omap_hwmod am33xx_cefuse_hwmod = {
  386. .name = "cefuse",
  387. .class = &am33xx_cefuse_hwmod_class,
  388. .clkdm_name = "l4_cefuse_clkdm",
  389. .main_clk = "cefuse_fck",
  390. .prcm = {
  391. .omap4 = {
  392. .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
  393. .modulemode = MODULEMODE_SWCTRL,
  394. },
  395. },
  396. };
  397. /*
  398. * 'clkdiv32k' class
  399. */
  400. static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
  401. .name = "clkdiv32k",
  402. };
  403. static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
  404. .name = "clkdiv32k",
  405. .class = &am33xx_clkdiv32k_hwmod_class,
  406. .clkdm_name = "clk_24mhz_clkdm",
  407. .main_clk = "clkdiv32k_ick",
  408. .prcm = {
  409. .omap4 = {
  410. .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
  411. .modulemode = MODULEMODE_SWCTRL,
  412. },
  413. },
  414. };
  415. /*
  416. * 'debugss' class
  417. * debug sub system
  418. */
  419. static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
  420. .name = "debugss",
  421. };
  422. static struct omap_hwmod am33xx_debugss_hwmod = {
  423. .name = "debugss",
  424. .class = &am33xx_debugss_hwmod_class,
  425. .clkdm_name = "l3_aon_clkdm",
  426. .main_clk = "debugss_ick",
  427. .prcm = {
  428. .omap4 = {
  429. .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
  430. .modulemode = MODULEMODE_SWCTRL,
  431. },
  432. },
  433. };
  434. /* ocpwp */
  435. static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
  436. .name = "ocpwp",
  437. };
  438. static struct omap_hwmod am33xx_ocpwp_hwmod = {
  439. .name = "ocpwp",
  440. .class = &am33xx_ocpwp_hwmod_class,
  441. .clkdm_name = "l4ls_clkdm",
  442. .main_clk = "l4ls_gclk",
  443. .prcm = {
  444. .omap4 = {
  445. .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
  446. .modulemode = MODULEMODE_SWCTRL,
  447. },
  448. },
  449. };
  450. #endif
  451. /*
  452. * 'aes0' class
  453. */
  454. static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
  455. .rev_offs = 0x80,
  456. .sysc_offs = 0x84,
  457. .syss_offs = 0x88,
  458. .sysc_flags = SYSS_HAS_RESET_STATUS,
  459. };
  460. static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
  461. .name = "aes0",
  462. .sysc = &am33xx_aes0_sysc,
  463. };
  464. static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
  465. { .irq = 103 + OMAP_INTC_START, },
  466. { .irq = -1 },
  467. };
  468. static struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = {
  469. { .name = "tx", .dma_req = 6, },
  470. { .name = "rx", .dma_req = 5, },
  471. { .dma_req = -1 }
  472. };
  473. static struct omap_hwmod am33xx_aes0_hwmod = {
  474. .name = "aes",
  475. .class = &am33xx_aes0_hwmod_class,
  476. .clkdm_name = "l3_clkdm",
  477. .mpu_irqs = am33xx_aes0_irqs,
  478. .sdma_reqs = am33xx_aes0_edma_reqs,
  479. .main_clk = "aes0_fck",
  480. .prcm = {
  481. .omap4 = {
  482. .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
  483. .modulemode = MODULEMODE_SWCTRL,
  484. },
  485. },
  486. };
  487. /* sha0 HIB2 (the 'P' (public) device) */
  488. static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
  489. .rev_offs = 0x100,
  490. .sysc_offs = 0x110,
  491. .syss_offs = 0x114,
  492. .sysc_flags = SYSS_HAS_RESET_STATUS,
  493. };
  494. static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
  495. .name = "sha0",
  496. .sysc = &am33xx_sha0_sysc,
  497. };
  498. static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
  499. { .irq = 109 + OMAP_INTC_START, },
  500. { .irq = -1 },
  501. };
  502. static struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = {
  503. { .name = "rx", .dma_req = 36, },
  504. { .dma_req = -1 }
  505. };
  506. static struct omap_hwmod am33xx_sha0_hwmod = {
  507. .name = "sham",
  508. .class = &am33xx_sha0_hwmod_class,
  509. .clkdm_name = "l3_clkdm",
  510. .mpu_irqs = am33xx_sha0_irqs,
  511. .sdma_reqs = am33xx_sha0_edma_reqs,
  512. .main_clk = "l3_gclk",
  513. .prcm = {
  514. .omap4 = {
  515. .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
  516. .modulemode = MODULEMODE_SWCTRL,
  517. },
  518. },
  519. };
  520. /* ocmcram */
  521. static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
  522. .name = "ocmcram",
  523. };
  524. static struct omap_hwmod am33xx_ocmcram_hwmod = {
  525. .name = "ocmcram",
  526. .class = &am33xx_ocmcram_hwmod_class,
  527. .clkdm_name = "l3_clkdm",
  528. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  529. .main_clk = "l3_gclk",
  530. .prcm = {
  531. .omap4 = {
  532. .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
  533. .modulemode = MODULEMODE_SWCTRL,
  534. },
  535. },
  536. };
  537. /* 'smartreflex' class */
  538. static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
  539. .name = "smartreflex",
  540. };
  541. /* smartreflex0 */
  542. static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
  543. { .irq = 120 + OMAP_INTC_START, },
  544. { .irq = -1 },
  545. };
  546. static struct omap_hwmod am33xx_smartreflex0_hwmod = {
  547. .name = "smartreflex0",
  548. .class = &am33xx_smartreflex_hwmod_class,
  549. .clkdm_name = "l4_wkup_clkdm",
  550. .mpu_irqs = am33xx_smartreflex0_irqs,
  551. .main_clk = "smartreflex0_fck",
  552. .prcm = {
  553. .omap4 = {
  554. .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
  555. .modulemode = MODULEMODE_SWCTRL,
  556. },
  557. },
  558. };
  559. /* smartreflex1 */
  560. static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
  561. { .irq = 121 + OMAP_INTC_START, },
  562. { .irq = -1 },
  563. };
  564. static struct omap_hwmod am33xx_smartreflex1_hwmod = {
  565. .name = "smartreflex1",
  566. .class = &am33xx_smartreflex_hwmod_class,
  567. .clkdm_name = "l4_wkup_clkdm",
  568. .mpu_irqs = am33xx_smartreflex1_irqs,
  569. .main_clk = "smartreflex1_fck",
  570. .prcm = {
  571. .omap4 = {
  572. .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
  573. .modulemode = MODULEMODE_SWCTRL,
  574. },
  575. },
  576. };
  577. /*
  578. * 'control' module class
  579. */
  580. static struct omap_hwmod_class am33xx_control_hwmod_class = {
  581. .name = "control",
  582. };
  583. static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
  584. { .irq = 8 + OMAP_INTC_START, },
  585. { .irq = -1 },
  586. };
  587. static struct omap_hwmod am33xx_control_hwmod = {
  588. .name = "control",
  589. .class = &am33xx_control_hwmod_class,
  590. .clkdm_name = "l4_wkup_clkdm",
  591. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  592. .mpu_irqs = am33xx_control_irqs,
  593. .main_clk = "dpll_core_m4_div2_ck",
  594. .prcm = {
  595. .omap4 = {
  596. .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
  597. .modulemode = MODULEMODE_SWCTRL,
  598. },
  599. },
  600. };
  601. /*
  602. * 'cpgmac' class
  603. * cpsw/cpgmac sub system
  604. */
  605. static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
  606. .rev_offs = 0x0,
  607. .sysc_offs = 0x8,
  608. .syss_offs = 0x4,
  609. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
  610. SYSS_HAS_RESET_STATUS),
  611. .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
  612. MSTANDBY_NO),
  613. .sysc_fields = &omap_hwmod_sysc_type3,
  614. };
  615. static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
  616. .name = "cpgmac0",
  617. .sysc = &am33xx_cpgmac_sysc,
  618. };
  619. static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
  620. { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
  621. { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
  622. { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
  623. { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
  624. { .irq = -1 },
  625. };
  626. static struct omap_hwmod am33xx_cpgmac0_hwmod = {
  627. .name = "cpgmac0",
  628. .class = &am33xx_cpgmac0_hwmod_class,
  629. .clkdm_name = "cpsw_125mhz_clkdm",
  630. .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
  631. .mpu_irqs = am33xx_cpgmac0_irqs,
  632. .main_clk = "cpsw_125mhz_gclk",
  633. .prcm = {
  634. .omap4 = {
  635. .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
  636. .modulemode = MODULEMODE_SWCTRL,
  637. },
  638. },
  639. };
  640. /*
  641. * mdio class
  642. */
  643. static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
  644. .name = "davinci_mdio",
  645. };
  646. static struct omap_hwmod am33xx_mdio_hwmod = {
  647. .name = "davinci_mdio",
  648. .class = &am33xx_mdio_hwmod_class,
  649. .clkdm_name = "cpsw_125mhz_clkdm",
  650. .main_clk = "cpsw_125mhz_gclk",
  651. };
  652. /*
  653. * dcan class
  654. */
  655. static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
  656. .name = "d_can",
  657. };
  658. /* dcan0 */
  659. static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
  660. { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
  661. { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
  662. { .irq = -1 },
  663. };
  664. static struct omap_hwmod am33xx_dcan0_hwmod = {
  665. .name = "d_can0",
  666. .class = &am33xx_dcan_hwmod_class,
  667. .clkdm_name = "l4ls_clkdm",
  668. .mpu_irqs = am33xx_dcan0_irqs,
  669. .main_clk = "dcan0_fck",
  670. .prcm = {
  671. .omap4 = {
  672. .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
  673. .modulemode = MODULEMODE_SWCTRL,
  674. },
  675. },
  676. };
  677. /* dcan1 */
  678. static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
  679. { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
  680. { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
  681. { .irq = -1 },
  682. };
  683. static struct omap_hwmod am33xx_dcan1_hwmod = {
  684. .name = "d_can1",
  685. .class = &am33xx_dcan_hwmod_class,
  686. .clkdm_name = "l4ls_clkdm",
  687. .mpu_irqs = am33xx_dcan1_irqs,
  688. .main_clk = "dcan1_fck",
  689. .prcm = {
  690. .omap4 = {
  691. .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
  692. .modulemode = MODULEMODE_SWCTRL,
  693. },
  694. },
  695. };
  696. /* elm */
  697. static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
  698. .rev_offs = 0x0000,
  699. .sysc_offs = 0x0010,
  700. .syss_offs = 0x0014,
  701. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  702. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  703. SYSS_HAS_RESET_STATUS),
  704. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  705. .sysc_fields = &omap_hwmod_sysc_type1,
  706. };
  707. static struct omap_hwmod_class am33xx_elm_hwmod_class = {
  708. .name = "elm",
  709. .sysc = &am33xx_elm_sysc,
  710. };
  711. static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
  712. { .irq = 4 + OMAP_INTC_START, },
  713. { .irq = -1 },
  714. };
  715. static struct omap_hwmod am33xx_elm_hwmod = {
  716. .name = "elm",
  717. .class = &am33xx_elm_hwmod_class,
  718. .clkdm_name = "l4ls_clkdm",
  719. .mpu_irqs = am33xx_elm_irqs,
  720. .main_clk = "l4ls_gclk",
  721. .prcm = {
  722. .omap4 = {
  723. .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
  724. .modulemode = MODULEMODE_SWCTRL,
  725. },
  726. },
  727. };
  728. /* pwmss */
  729. static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
  730. .rev_offs = 0x0,
  731. .sysc_offs = 0x4,
  732. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
  733. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  734. SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
  735. MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
  736. .sysc_fields = &omap_hwmod_sysc_type2,
  737. };
  738. static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
  739. .name = "epwmss",
  740. .sysc = &am33xx_epwmss_sysc,
  741. };
  742. static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
  743. .name = "ecap",
  744. };
  745. static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
  746. .name = "eqep",
  747. };
  748. static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
  749. .name = "ehrpwm",
  750. };
  751. /* epwmss0 */
  752. static struct omap_hwmod am33xx_epwmss0_hwmod = {
  753. .name = "epwmss0",
  754. .class = &am33xx_epwmss_hwmod_class,
  755. .clkdm_name = "l4ls_clkdm",
  756. .main_clk = "l4ls_gclk",
  757. .prcm = {
  758. .omap4 = {
  759. .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
  760. .modulemode = MODULEMODE_SWCTRL,
  761. },
  762. },
  763. };
  764. /* ecap0 */
  765. static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
  766. { .irq = 31 + OMAP_INTC_START, },
  767. { .irq = -1 },
  768. };
  769. static struct omap_hwmod am33xx_ecap0_hwmod = {
  770. .name = "ecap0",
  771. .class = &am33xx_ecap_hwmod_class,
  772. .clkdm_name = "l4ls_clkdm",
  773. .mpu_irqs = am33xx_ecap0_irqs,
  774. .main_clk = "l4ls_gclk",
  775. };
  776. /* eqep0 */
  777. static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
  778. { .irq = 79 + OMAP_INTC_START, },
  779. { .irq = -1 },
  780. };
  781. static struct omap_hwmod am33xx_eqep0_hwmod = {
  782. .name = "eqep0",
  783. .class = &am33xx_eqep_hwmod_class,
  784. .clkdm_name = "l4ls_clkdm",
  785. .mpu_irqs = am33xx_eqep0_irqs,
  786. .main_clk = "l4ls_gclk",
  787. };
  788. /* ehrpwm0 */
  789. static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
  790. { .name = "int", .irq = 86 + OMAP_INTC_START, },
  791. { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
  792. { .irq = -1 },
  793. };
  794. static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
  795. .name = "ehrpwm0",
  796. .class = &am33xx_ehrpwm_hwmod_class,
  797. .clkdm_name = "l4ls_clkdm",
  798. .mpu_irqs = am33xx_ehrpwm0_irqs,
  799. .main_clk = "l4ls_gclk",
  800. };
  801. /* epwmss1 */
  802. static struct omap_hwmod am33xx_epwmss1_hwmod = {
  803. .name = "epwmss1",
  804. .class = &am33xx_epwmss_hwmod_class,
  805. .clkdm_name = "l4ls_clkdm",
  806. .main_clk = "l4ls_gclk",
  807. .prcm = {
  808. .omap4 = {
  809. .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
  810. .modulemode = MODULEMODE_SWCTRL,
  811. },
  812. },
  813. };
  814. /* ecap1 */
  815. static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
  816. { .irq = 47 + OMAP_INTC_START, },
  817. { .irq = -1 },
  818. };
  819. static struct omap_hwmod am33xx_ecap1_hwmod = {
  820. .name = "ecap1",
  821. .class = &am33xx_ecap_hwmod_class,
  822. .clkdm_name = "l4ls_clkdm",
  823. .mpu_irqs = am33xx_ecap1_irqs,
  824. .main_clk = "l4ls_gclk",
  825. };
  826. /* eqep1 */
  827. static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
  828. { .irq = 88 + OMAP_INTC_START, },
  829. { .irq = -1 },
  830. };
  831. static struct omap_hwmod am33xx_eqep1_hwmod = {
  832. .name = "eqep1",
  833. .class = &am33xx_eqep_hwmod_class,
  834. .clkdm_name = "l4ls_clkdm",
  835. .mpu_irqs = am33xx_eqep1_irqs,
  836. .main_clk = "l4ls_gclk",
  837. };
  838. /* ehrpwm1 */
  839. static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
  840. { .name = "int", .irq = 87 + OMAP_INTC_START, },
  841. { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
  842. { .irq = -1 },
  843. };
  844. static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
  845. .name = "ehrpwm1",
  846. .class = &am33xx_ehrpwm_hwmod_class,
  847. .clkdm_name = "l4ls_clkdm",
  848. .mpu_irqs = am33xx_ehrpwm1_irqs,
  849. .main_clk = "l4ls_gclk",
  850. };
  851. /* epwmss2 */
  852. static struct omap_hwmod am33xx_epwmss2_hwmod = {
  853. .name = "epwmss2",
  854. .class = &am33xx_epwmss_hwmod_class,
  855. .clkdm_name = "l4ls_clkdm",
  856. .main_clk = "l4ls_gclk",
  857. .prcm = {
  858. .omap4 = {
  859. .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
  860. .modulemode = MODULEMODE_SWCTRL,
  861. },
  862. },
  863. };
  864. /* ecap2 */
  865. static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
  866. { .irq = 61 + OMAP_INTC_START, },
  867. { .irq = -1 },
  868. };
  869. static struct omap_hwmod am33xx_ecap2_hwmod = {
  870. .name = "ecap2",
  871. .class = &am33xx_ecap_hwmod_class,
  872. .clkdm_name = "l4ls_clkdm",
  873. .mpu_irqs = am33xx_ecap2_irqs,
  874. .main_clk = "l4ls_gclk",
  875. };
  876. /* eqep2 */
  877. static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
  878. { .irq = 89 + OMAP_INTC_START, },
  879. { .irq = -1 },
  880. };
  881. static struct omap_hwmod am33xx_eqep2_hwmod = {
  882. .name = "eqep2",
  883. .class = &am33xx_eqep_hwmod_class,
  884. .clkdm_name = "l4ls_clkdm",
  885. .mpu_irqs = am33xx_eqep2_irqs,
  886. .main_clk = "l4ls_gclk",
  887. };
  888. /* ehrpwm2 */
  889. static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
  890. { .name = "int", .irq = 39 + OMAP_INTC_START, },
  891. { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
  892. { .irq = -1 },
  893. };
  894. static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
  895. .name = "ehrpwm2",
  896. .class = &am33xx_ehrpwm_hwmod_class,
  897. .clkdm_name = "l4ls_clkdm",
  898. .mpu_irqs = am33xx_ehrpwm2_irqs,
  899. .main_clk = "l4ls_gclk",
  900. };
  901. /*
  902. * 'gpio' class: for gpio 0,1,2,3
  903. */
  904. static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
  905. .rev_offs = 0x0000,
  906. .sysc_offs = 0x0010,
  907. .syss_offs = 0x0114,
  908. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
  909. SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
  910. SYSS_HAS_RESET_STATUS),
  911. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  912. SIDLE_SMART_WKUP),
  913. .sysc_fields = &omap_hwmod_sysc_type1,
  914. };
  915. static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
  916. .name = "gpio",
  917. .sysc = &am33xx_gpio_sysc,
  918. .rev = 2,
  919. };
  920. static struct omap_gpio_dev_attr gpio_dev_attr = {
  921. .bank_width = 32,
  922. .dbck_flag = true,
  923. };
  924. /* gpio0 */
  925. static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
  926. { .role = "dbclk", .clk = "gpio0_dbclk" },
  927. };
  928. static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
  929. { .irq = 96 + OMAP_INTC_START, },
  930. { .irq = -1 },
  931. };
  932. static struct omap_hwmod am33xx_gpio0_hwmod = {
  933. .name = "gpio1",
  934. .class = &am33xx_gpio_hwmod_class,
  935. .clkdm_name = "l4_wkup_clkdm",
  936. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  937. .mpu_irqs = am33xx_gpio0_irqs,
  938. .main_clk = "dpll_core_m4_div2_ck",
  939. .prcm = {
  940. .omap4 = {
  941. .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
  942. .modulemode = MODULEMODE_SWCTRL,
  943. },
  944. },
  945. .opt_clks = gpio0_opt_clks,
  946. .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
  947. .dev_attr = &gpio_dev_attr,
  948. };
  949. /* gpio1 */
  950. static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
  951. { .irq = 98 + OMAP_INTC_START, },
  952. { .irq = -1 },
  953. };
  954. static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
  955. { .role = "dbclk", .clk = "gpio1_dbclk" },
  956. };
  957. static struct omap_hwmod am33xx_gpio1_hwmod = {
  958. .name = "gpio2",
  959. .class = &am33xx_gpio_hwmod_class,
  960. .clkdm_name = "l4ls_clkdm",
  961. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  962. .mpu_irqs = am33xx_gpio1_irqs,
  963. .main_clk = "l4ls_gclk",
  964. .prcm = {
  965. .omap4 = {
  966. .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
  967. .modulemode = MODULEMODE_SWCTRL,
  968. },
  969. },
  970. .opt_clks = gpio1_opt_clks,
  971. .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
  972. .dev_attr = &gpio_dev_attr,
  973. };
  974. /* gpio2 */
  975. static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
  976. { .irq = 32 + OMAP_INTC_START, },
  977. { .irq = -1 },
  978. };
  979. static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
  980. { .role = "dbclk", .clk = "gpio2_dbclk" },
  981. };
  982. static struct omap_hwmod am33xx_gpio2_hwmod = {
  983. .name = "gpio3",
  984. .class = &am33xx_gpio_hwmod_class,
  985. .clkdm_name = "l4ls_clkdm",
  986. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  987. .mpu_irqs = am33xx_gpio2_irqs,
  988. .main_clk = "l4ls_gclk",
  989. .prcm = {
  990. .omap4 = {
  991. .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
  992. .modulemode = MODULEMODE_SWCTRL,
  993. },
  994. },
  995. .opt_clks = gpio2_opt_clks,
  996. .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
  997. .dev_attr = &gpio_dev_attr,
  998. };
  999. /* gpio3 */
  1000. static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
  1001. { .irq = 62 + OMAP_INTC_START, },
  1002. { .irq = -1 },
  1003. };
  1004. static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
  1005. { .role = "dbclk", .clk = "gpio3_dbclk" },
  1006. };
  1007. static struct omap_hwmod am33xx_gpio3_hwmod = {
  1008. .name = "gpio4",
  1009. .class = &am33xx_gpio_hwmod_class,
  1010. .clkdm_name = "l4ls_clkdm",
  1011. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  1012. .mpu_irqs = am33xx_gpio3_irqs,
  1013. .main_clk = "l4ls_gclk",
  1014. .prcm = {
  1015. .omap4 = {
  1016. .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
  1017. .modulemode = MODULEMODE_SWCTRL,
  1018. },
  1019. },
  1020. .opt_clks = gpio3_opt_clks,
  1021. .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
  1022. .dev_attr = &gpio_dev_attr,
  1023. };
  1024. /* gpmc */
  1025. static struct omap_hwmod_class_sysconfig gpmc_sysc = {
  1026. .rev_offs = 0x0,
  1027. .sysc_offs = 0x10,
  1028. .syss_offs = 0x14,
  1029. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
  1030. SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  1031. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1032. .sysc_fields = &omap_hwmod_sysc_type1,
  1033. };
  1034. static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
  1035. .name = "gpmc",
  1036. .sysc = &gpmc_sysc,
  1037. };
  1038. static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
  1039. { .irq = 100 + OMAP_INTC_START, },
  1040. { .irq = -1 },
  1041. };
  1042. static struct omap_hwmod am33xx_gpmc_hwmod = {
  1043. .name = "gpmc",
  1044. .class = &am33xx_gpmc_hwmod_class,
  1045. .clkdm_name = "l3s_clkdm",
  1046. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  1047. .mpu_irqs = am33xx_gpmc_irqs,
  1048. .main_clk = "l3s_gclk",
  1049. .prcm = {
  1050. .omap4 = {
  1051. .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
  1052. .modulemode = MODULEMODE_SWCTRL,
  1053. },
  1054. },
  1055. };
  1056. /* 'i2c' class */
  1057. static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
  1058. .sysc_offs = 0x0010,
  1059. .syss_offs = 0x0090,
  1060. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
  1061. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  1062. SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  1063. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1064. SIDLE_SMART_WKUP),
  1065. .sysc_fields = &omap_hwmod_sysc_type1,
  1066. };
  1067. static struct omap_hwmod_class i2c_class = {
  1068. .name = "i2c",
  1069. .sysc = &am33xx_i2c_sysc,
  1070. .rev = OMAP_I2C_IP_VERSION_2,
  1071. .reset = &omap_i2c_reset,
  1072. };
  1073. static struct omap_i2c_dev_attr i2c_dev_attr = {
  1074. .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
  1075. };
  1076. /* i2c1 */
  1077. static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
  1078. { .irq = 70 + OMAP_INTC_START, },
  1079. { .irq = -1 },
  1080. };
  1081. static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
  1082. { .name = "tx", .dma_req = 0, },
  1083. { .name = "rx", .dma_req = 0, },
  1084. { .dma_req = -1 }
  1085. };
  1086. static struct omap_hwmod am33xx_i2c1_hwmod = {
  1087. .name = "i2c1",
  1088. .class = &i2c_class,
  1089. .clkdm_name = "l4_wkup_clkdm",
  1090. .mpu_irqs = i2c1_mpu_irqs,
  1091. .sdma_reqs = i2c1_edma_reqs,
  1092. .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
  1093. .main_clk = "dpll_per_m2_div4_wkupdm_ck",
  1094. .prcm = {
  1095. .omap4 = {
  1096. .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
  1097. .modulemode = MODULEMODE_SWCTRL,
  1098. },
  1099. },
  1100. .dev_attr = &i2c_dev_attr,
  1101. };
  1102. /* i2c1 */
  1103. static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
  1104. { .irq = 71 + OMAP_INTC_START, },
  1105. { .irq = -1 },
  1106. };
  1107. static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
  1108. { .name = "tx", .dma_req = 0, },
  1109. { .name = "rx", .dma_req = 0, },
  1110. { .dma_req = -1 }
  1111. };
  1112. static struct omap_hwmod am33xx_i2c2_hwmod = {
  1113. .name = "i2c2",
  1114. .class = &i2c_class,
  1115. .clkdm_name = "l4ls_clkdm",
  1116. .mpu_irqs = i2c2_mpu_irqs,
  1117. .sdma_reqs = i2c2_edma_reqs,
  1118. .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
  1119. .main_clk = "dpll_per_m2_div4_ck",
  1120. .prcm = {
  1121. .omap4 = {
  1122. .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
  1123. .modulemode = MODULEMODE_SWCTRL,
  1124. },
  1125. },
  1126. .dev_attr = &i2c_dev_attr,
  1127. };
  1128. /* i2c3 */
  1129. static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
  1130. { .name = "tx", .dma_req = 0, },
  1131. { .name = "rx", .dma_req = 0, },
  1132. { .dma_req = -1 }
  1133. };
  1134. static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
  1135. { .irq = 30 + OMAP_INTC_START, },
  1136. { .irq = -1 },
  1137. };
  1138. static struct omap_hwmod am33xx_i2c3_hwmod = {
  1139. .name = "i2c3",
  1140. .class = &i2c_class,
  1141. .clkdm_name = "l4ls_clkdm",
  1142. .mpu_irqs = i2c3_mpu_irqs,
  1143. .sdma_reqs = i2c3_edma_reqs,
  1144. .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
  1145. .main_clk = "dpll_per_m2_div4_ck",
  1146. .prcm = {
  1147. .omap4 = {
  1148. .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
  1149. .modulemode = MODULEMODE_SWCTRL,
  1150. },
  1151. },
  1152. .dev_attr = &i2c_dev_attr,
  1153. };
  1154. /* lcdc */
  1155. static struct omap_hwmod_class_sysconfig lcdc_sysc = {
  1156. .rev_offs = 0x0,
  1157. .sysc_offs = 0x54,
  1158. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
  1159. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1160. .sysc_fields = &omap_hwmod_sysc_type2,
  1161. };
  1162. static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
  1163. .name = "lcdc",
  1164. .sysc = &lcdc_sysc,
  1165. };
  1166. static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
  1167. { .irq = 36 + OMAP_INTC_START, },
  1168. { .irq = -1 },
  1169. };
  1170. static struct omap_hwmod am33xx_lcdc_hwmod = {
  1171. .name = "lcdc",
  1172. .class = &am33xx_lcdc_hwmod_class,
  1173. .clkdm_name = "lcdc_clkdm",
  1174. .mpu_irqs = am33xx_lcdc_irqs,
  1175. .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
  1176. .main_clk = "lcd_gclk",
  1177. .prcm = {
  1178. .omap4 = {
  1179. .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
  1180. .modulemode = MODULEMODE_SWCTRL,
  1181. },
  1182. },
  1183. };
  1184. /*
  1185. * 'mailbox' class
  1186. * mailbox module allowing communication between the on-chip processors using a
  1187. * queued mailbox-interrupt mechanism.
  1188. */
  1189. static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
  1190. .rev_offs = 0x0000,
  1191. .sysc_offs = 0x0010,
  1192. .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
  1193. SYSC_HAS_SOFTRESET),
  1194. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1195. .sysc_fields = &omap_hwmod_sysc_type2,
  1196. };
  1197. static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
  1198. .name = "mailbox",
  1199. .sysc = &am33xx_mailbox_sysc,
  1200. };
  1201. static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
  1202. { .irq = 77 + OMAP_INTC_START, },
  1203. { .irq = -1 },
  1204. };
  1205. static struct omap_hwmod am33xx_mailbox_hwmod = {
  1206. .name = "mailbox",
  1207. .class = &am33xx_mailbox_hwmod_class,
  1208. .clkdm_name = "l4ls_clkdm",
  1209. .mpu_irqs = am33xx_mailbox_irqs,
  1210. .main_clk = "l4ls_gclk",
  1211. .prcm = {
  1212. .omap4 = {
  1213. .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
  1214. .modulemode = MODULEMODE_SWCTRL,
  1215. },
  1216. },
  1217. };
  1218. /*
  1219. * 'mcasp' class
  1220. */
  1221. static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
  1222. .rev_offs = 0x0,
  1223. .sysc_offs = 0x4,
  1224. .sysc_flags = SYSC_HAS_SIDLEMODE,
  1225. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1226. .sysc_fields = &omap_hwmod_sysc_type3,
  1227. };
  1228. static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
  1229. .name = "mcasp",
  1230. .sysc = &am33xx_mcasp_sysc,
  1231. };
  1232. /* mcasp0 */
  1233. static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
  1234. { .name = "ax", .irq = 80 + OMAP_INTC_START, },
  1235. { .name = "ar", .irq = 81 + OMAP_INTC_START, },
  1236. { .irq = -1 },
  1237. };
  1238. static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
  1239. { .name = "tx", .dma_req = 8, },
  1240. { .name = "rx", .dma_req = 9, },
  1241. { .dma_req = -1 }
  1242. };
  1243. static struct omap_hwmod am33xx_mcasp0_hwmod = {
  1244. .name = "mcasp0",
  1245. .class = &am33xx_mcasp_hwmod_class,
  1246. .clkdm_name = "l3s_clkdm",
  1247. .mpu_irqs = am33xx_mcasp0_irqs,
  1248. .sdma_reqs = am33xx_mcasp0_edma_reqs,
  1249. .main_clk = "mcasp0_fck",
  1250. .prcm = {
  1251. .omap4 = {
  1252. .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
  1253. .modulemode = MODULEMODE_SWCTRL,
  1254. },
  1255. },
  1256. };
  1257. /* mcasp1 */
  1258. static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
  1259. { .name = "ax", .irq = 82 + OMAP_INTC_START, },
  1260. { .name = "ar", .irq = 83 + OMAP_INTC_START, },
  1261. { .irq = -1 },
  1262. };
  1263. static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
  1264. { .name = "tx", .dma_req = 10, },
  1265. { .name = "rx", .dma_req = 11, },
  1266. { .dma_req = -1 }
  1267. };
  1268. static struct omap_hwmod am33xx_mcasp1_hwmod = {
  1269. .name = "mcasp1",
  1270. .class = &am33xx_mcasp_hwmod_class,
  1271. .clkdm_name = "l3s_clkdm",
  1272. .mpu_irqs = am33xx_mcasp1_irqs,
  1273. .sdma_reqs = am33xx_mcasp1_edma_reqs,
  1274. .main_clk = "mcasp1_fck",
  1275. .prcm = {
  1276. .omap4 = {
  1277. .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
  1278. .modulemode = MODULEMODE_SWCTRL,
  1279. },
  1280. },
  1281. };
  1282. /* 'mmc' class */
  1283. static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
  1284. .rev_offs = 0x1fc,
  1285. .sysc_offs = 0x10,
  1286. .syss_offs = 0x14,
  1287. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  1288. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  1289. SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  1290. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1291. .sysc_fields = &omap_hwmod_sysc_type1,
  1292. };
  1293. static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
  1294. .name = "mmc",
  1295. .sysc = &am33xx_mmc_sysc,
  1296. };
  1297. /* mmc0 */
  1298. static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
  1299. { .irq = 64 + OMAP_INTC_START, },
  1300. { .irq = -1 },
  1301. };
  1302. static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
  1303. { .name = "tx", .dma_req = 24, },
  1304. { .name = "rx", .dma_req = 25, },
  1305. { .dma_req = -1 }
  1306. };
  1307. static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
  1308. .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
  1309. };
  1310. static struct omap_hwmod am33xx_mmc0_hwmod = {
  1311. .name = "mmc1",
  1312. .class = &am33xx_mmc_hwmod_class,
  1313. .clkdm_name = "l4ls_clkdm",
  1314. .mpu_irqs = am33xx_mmc0_irqs,
  1315. .sdma_reqs = am33xx_mmc0_edma_reqs,
  1316. .main_clk = "mmc_clk",
  1317. .prcm = {
  1318. .omap4 = {
  1319. .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
  1320. .modulemode = MODULEMODE_SWCTRL,
  1321. },
  1322. },
  1323. .dev_attr = &am33xx_mmc0_dev_attr,
  1324. };
  1325. /* mmc1 */
  1326. static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
  1327. { .irq = 28 + OMAP_INTC_START, },
  1328. { .irq = -1 },
  1329. };
  1330. static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
  1331. { .name = "tx", .dma_req = 2, },
  1332. { .name = "rx", .dma_req = 3, },
  1333. { .dma_req = -1 }
  1334. };
  1335. static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
  1336. .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
  1337. };
  1338. static struct omap_hwmod am33xx_mmc1_hwmod = {
  1339. .name = "mmc2",
  1340. .class = &am33xx_mmc_hwmod_class,
  1341. .clkdm_name = "l4ls_clkdm",
  1342. .mpu_irqs = am33xx_mmc1_irqs,
  1343. .sdma_reqs = am33xx_mmc1_edma_reqs,
  1344. .main_clk = "mmc_clk",
  1345. .prcm = {
  1346. .omap4 = {
  1347. .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
  1348. .modulemode = MODULEMODE_SWCTRL,
  1349. },
  1350. },
  1351. .dev_attr = &am33xx_mmc1_dev_attr,
  1352. };
  1353. /* mmc2 */
  1354. static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
  1355. { .irq = 29 + OMAP_INTC_START, },
  1356. { .irq = -1 },
  1357. };
  1358. static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
  1359. { .name = "tx", .dma_req = 64, },
  1360. { .name = "rx", .dma_req = 65, },
  1361. { .dma_req = -1 }
  1362. };
  1363. static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
  1364. .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
  1365. };
  1366. static struct omap_hwmod am33xx_mmc2_hwmod = {
  1367. .name = "mmc3",
  1368. .class = &am33xx_mmc_hwmod_class,
  1369. .clkdm_name = "l3s_clkdm",
  1370. .mpu_irqs = am33xx_mmc2_irqs,
  1371. .sdma_reqs = am33xx_mmc2_edma_reqs,
  1372. .main_clk = "mmc_clk",
  1373. .prcm = {
  1374. .omap4 = {
  1375. .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
  1376. .modulemode = MODULEMODE_SWCTRL,
  1377. },
  1378. },
  1379. .dev_attr = &am33xx_mmc2_dev_attr,
  1380. };
  1381. /*
  1382. * 'rtc' class
  1383. * rtc subsystem
  1384. */
  1385. static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
  1386. .rev_offs = 0x0074,
  1387. .sysc_offs = 0x0078,
  1388. .sysc_flags = SYSC_HAS_SIDLEMODE,
  1389. .idlemodes = (SIDLE_FORCE | SIDLE_NO |
  1390. SIDLE_SMART | SIDLE_SMART_WKUP),
  1391. .sysc_fields = &omap_hwmod_sysc_type3,
  1392. };
  1393. static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
  1394. .name = "rtc",
  1395. .sysc = &am33xx_rtc_sysc,
  1396. };
  1397. static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
  1398. { .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
  1399. { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
  1400. { .irq = -1 },
  1401. };
  1402. static struct omap_hwmod am33xx_rtc_hwmod = {
  1403. .name = "rtc",
  1404. .class = &am33xx_rtc_hwmod_class,
  1405. .clkdm_name = "l4_rtc_clkdm",
  1406. .mpu_irqs = am33xx_rtc_irqs,
  1407. .main_clk = "clk_32768_ck",
  1408. .prcm = {
  1409. .omap4 = {
  1410. .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
  1411. .modulemode = MODULEMODE_SWCTRL,
  1412. },
  1413. },
  1414. };
  1415. /* 'spi' class */
  1416. static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
  1417. .rev_offs = 0x0000,
  1418. .sysc_offs = 0x0110,
  1419. .syss_offs = 0x0114,
  1420. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  1421. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  1422. SYSS_HAS_RESET_STATUS),
  1423. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1424. .sysc_fields = &omap_hwmod_sysc_type1,
  1425. };
  1426. static struct omap_hwmod_class am33xx_spi_hwmod_class = {
  1427. .name = "mcspi",
  1428. .sysc = &am33xx_mcspi_sysc,
  1429. .rev = OMAP4_MCSPI_REV,
  1430. };
  1431. /* spi0 */
  1432. static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
  1433. { .irq = 65 + OMAP_INTC_START, },
  1434. { .irq = -1 },
  1435. };
  1436. static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
  1437. { .name = "rx0", .dma_req = 17 },
  1438. { .name = "tx0", .dma_req = 16 },
  1439. { .name = "rx1", .dma_req = 19 },
  1440. { .name = "tx1", .dma_req = 18 },
  1441. { .dma_req = -1 }
  1442. };
  1443. static struct omap2_mcspi_dev_attr mcspi_attrib = {
  1444. .num_chipselect = 2,
  1445. };
  1446. static struct omap_hwmod am33xx_spi0_hwmod = {
  1447. .name = "spi0",
  1448. .class = &am33xx_spi_hwmod_class,
  1449. .clkdm_name = "l4ls_clkdm",
  1450. .mpu_irqs = am33xx_spi0_irqs,
  1451. .sdma_reqs = am33xx_mcspi0_edma_reqs,
  1452. .main_clk = "dpll_per_m2_div4_ck",
  1453. .prcm = {
  1454. .omap4 = {
  1455. .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
  1456. .modulemode = MODULEMODE_SWCTRL,
  1457. },
  1458. },
  1459. .dev_attr = &mcspi_attrib,
  1460. };
  1461. /* spi1 */
  1462. static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
  1463. { .irq = 125 + OMAP_INTC_START, },
  1464. { .irq = -1 },
  1465. };
  1466. static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
  1467. { .name = "rx0", .dma_req = 43 },
  1468. { .name = "tx0", .dma_req = 42 },
  1469. { .name = "rx1", .dma_req = 45 },
  1470. { .name = "tx1", .dma_req = 44 },
  1471. { .dma_req = -1 }
  1472. };
  1473. static struct omap_hwmod am33xx_spi1_hwmod = {
  1474. .name = "spi1",
  1475. .class = &am33xx_spi_hwmod_class,
  1476. .clkdm_name = "l4ls_clkdm",
  1477. .mpu_irqs = am33xx_spi1_irqs,
  1478. .sdma_reqs = am33xx_mcspi1_edma_reqs,
  1479. .main_clk = "dpll_per_m2_div4_ck",
  1480. .prcm = {
  1481. .omap4 = {
  1482. .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
  1483. .modulemode = MODULEMODE_SWCTRL,
  1484. },
  1485. },
  1486. .dev_attr = &mcspi_attrib,
  1487. };
  1488. /*
  1489. * 'spinlock' class
  1490. * spinlock provides hardware assistance for synchronizing the
  1491. * processes running on multiple processors
  1492. */
  1493. static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
  1494. .name = "spinlock",
  1495. };
  1496. static struct omap_hwmod am33xx_spinlock_hwmod = {
  1497. .name = "spinlock",
  1498. .class = &am33xx_spinlock_hwmod_class,
  1499. .clkdm_name = "l4ls_clkdm",
  1500. .main_clk = "l4ls_gclk",
  1501. .prcm = {
  1502. .omap4 = {
  1503. .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
  1504. .modulemode = MODULEMODE_SWCTRL,
  1505. },
  1506. },
  1507. };
  1508. /* 'timer 2-7' class */
  1509. static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
  1510. .rev_offs = 0x0000,
  1511. .sysc_offs = 0x0010,
  1512. .syss_offs = 0x0014,
  1513. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
  1514. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1515. SIDLE_SMART_WKUP),
  1516. .sysc_fields = &omap_hwmod_sysc_type2,
  1517. };
  1518. static struct omap_hwmod_class am33xx_timer_hwmod_class = {
  1519. .name = "timer",
  1520. .sysc = &am33xx_timer_sysc,
  1521. };
  1522. /* timer1 1ms */
  1523. static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
  1524. .rev_offs = 0x0000,
  1525. .sysc_offs = 0x0010,
  1526. .syss_offs = 0x0014,
  1527. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  1528. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  1529. SYSS_HAS_RESET_STATUS),
  1530. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1531. .sysc_fields = &omap_hwmod_sysc_type1,
  1532. };
  1533. static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
  1534. .name = "timer",
  1535. .sysc = &am33xx_timer1ms_sysc,
  1536. };
  1537. static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
  1538. { .irq = 67 + OMAP_INTC_START, },
  1539. { .irq = -1 },
  1540. };
  1541. static struct omap_hwmod am33xx_timer1_hwmod = {
  1542. .name = "timer1",
  1543. .class = &am33xx_timer1ms_hwmod_class,
  1544. .clkdm_name = "l4_wkup_clkdm",
  1545. .mpu_irqs = am33xx_timer1_irqs,
  1546. .main_clk = "timer1_fck",
  1547. .prcm = {
  1548. .omap4 = {
  1549. .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
  1550. .modulemode = MODULEMODE_SWCTRL,
  1551. },
  1552. },
  1553. };
  1554. static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
  1555. { .irq = 68 + OMAP_INTC_START, },
  1556. { .irq = -1 },
  1557. };
  1558. static struct omap_hwmod am33xx_timer2_hwmod = {
  1559. .name = "timer2",
  1560. .class = &am33xx_timer_hwmod_class,
  1561. .clkdm_name = "l4ls_clkdm",
  1562. .mpu_irqs = am33xx_timer2_irqs,
  1563. .main_clk = "timer2_fck",
  1564. .prcm = {
  1565. .omap4 = {
  1566. .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
  1567. .modulemode = MODULEMODE_SWCTRL,
  1568. },
  1569. },
  1570. };
  1571. static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
  1572. { .irq = 69 + OMAP_INTC_START, },
  1573. { .irq = -1 },
  1574. };
  1575. static struct omap_hwmod am33xx_timer3_hwmod = {
  1576. .name = "timer3",
  1577. .class = &am33xx_timer_hwmod_class,
  1578. .clkdm_name = "l4ls_clkdm",
  1579. .mpu_irqs = am33xx_timer3_irqs,
  1580. .main_clk = "timer3_fck",
  1581. .prcm = {
  1582. .omap4 = {
  1583. .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
  1584. .modulemode = MODULEMODE_SWCTRL,
  1585. },
  1586. },
  1587. };
  1588. static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
  1589. { .irq = 92 + OMAP_INTC_START, },
  1590. { .irq = -1 },
  1591. };
  1592. static struct omap_hwmod am33xx_timer4_hwmod = {
  1593. .name = "timer4",
  1594. .class = &am33xx_timer_hwmod_class,
  1595. .clkdm_name = "l4ls_clkdm",
  1596. .mpu_irqs = am33xx_timer4_irqs,
  1597. .main_clk = "timer4_fck",
  1598. .prcm = {
  1599. .omap4 = {
  1600. .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
  1601. .modulemode = MODULEMODE_SWCTRL,
  1602. },
  1603. },
  1604. };
  1605. static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
  1606. { .irq = 93 + OMAP_INTC_START, },
  1607. { .irq = -1 },
  1608. };
  1609. static struct omap_hwmod am33xx_timer5_hwmod = {
  1610. .name = "timer5",
  1611. .class = &am33xx_timer_hwmod_class,
  1612. .clkdm_name = "l4ls_clkdm",
  1613. .mpu_irqs = am33xx_timer5_irqs,
  1614. .main_clk = "timer5_fck",
  1615. .prcm = {
  1616. .omap4 = {
  1617. .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
  1618. .modulemode = MODULEMODE_SWCTRL,
  1619. },
  1620. },
  1621. };
  1622. static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
  1623. { .irq = 94 + OMAP_INTC_START, },
  1624. { .irq = -1 },
  1625. };
  1626. static struct omap_hwmod am33xx_timer6_hwmod = {
  1627. .name = "timer6",
  1628. .class = &am33xx_timer_hwmod_class,
  1629. .clkdm_name = "l4ls_clkdm",
  1630. .mpu_irqs = am33xx_timer6_irqs,
  1631. .main_clk = "timer6_fck",
  1632. .prcm = {
  1633. .omap4 = {
  1634. .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
  1635. .modulemode = MODULEMODE_SWCTRL,
  1636. },
  1637. },
  1638. };
  1639. static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
  1640. { .irq = 95 + OMAP_INTC_START, },
  1641. { .irq = -1 },
  1642. };
  1643. static struct omap_hwmod am33xx_timer7_hwmod = {
  1644. .name = "timer7",
  1645. .class = &am33xx_timer_hwmod_class,
  1646. .clkdm_name = "l4ls_clkdm",
  1647. .mpu_irqs = am33xx_timer7_irqs,
  1648. .main_clk = "timer7_fck",
  1649. .prcm = {
  1650. .omap4 = {
  1651. .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
  1652. .modulemode = MODULEMODE_SWCTRL,
  1653. },
  1654. },
  1655. };
  1656. /* tpcc */
  1657. static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
  1658. .name = "tpcc",
  1659. };
  1660. static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
  1661. { .name = "edma0", .irq = 12 + OMAP_INTC_START, },
  1662. { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
  1663. { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
  1664. { .irq = -1 },
  1665. };
  1666. static struct omap_hwmod am33xx_tpcc_hwmod = {
  1667. .name = "tpcc",
  1668. .class = &am33xx_tpcc_hwmod_class,
  1669. .clkdm_name = "l3_clkdm",
  1670. .mpu_irqs = am33xx_tpcc_irqs,
  1671. .main_clk = "l3_gclk",
  1672. .prcm = {
  1673. .omap4 = {
  1674. .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
  1675. .modulemode = MODULEMODE_SWCTRL,
  1676. },
  1677. },
  1678. };
  1679. static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
  1680. .rev_offs = 0x0,
  1681. .sysc_offs = 0x10,
  1682. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
  1683. SYSC_HAS_MIDLEMODE),
  1684. .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
  1685. .sysc_fields = &omap_hwmod_sysc_type2,
  1686. };
  1687. /* 'tptc' class */
  1688. static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
  1689. .name = "tptc",
  1690. .sysc = &am33xx_tptc_sysc,
  1691. };
  1692. /* tptc0 */
  1693. static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
  1694. { .irq = 112 + OMAP_INTC_START, },
  1695. { .irq = -1 },
  1696. };
  1697. static struct omap_hwmod am33xx_tptc0_hwmod = {
  1698. .name = "tptc0",
  1699. .class = &am33xx_tptc_hwmod_class,
  1700. .clkdm_name = "l3_clkdm",
  1701. .mpu_irqs = am33xx_tptc0_irqs,
  1702. .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
  1703. .main_clk = "l3_gclk",
  1704. .prcm = {
  1705. .omap4 = {
  1706. .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
  1707. .modulemode = MODULEMODE_SWCTRL,
  1708. },
  1709. },
  1710. };
  1711. /* tptc1 */
  1712. static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
  1713. { .irq = 113 + OMAP_INTC_START, },
  1714. { .irq = -1 },
  1715. };
  1716. static struct omap_hwmod am33xx_tptc1_hwmod = {
  1717. .name = "tptc1",
  1718. .class = &am33xx_tptc_hwmod_class,
  1719. .clkdm_name = "l3_clkdm",
  1720. .mpu_irqs = am33xx_tptc1_irqs,
  1721. .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
  1722. .main_clk = "l3_gclk",
  1723. .prcm = {
  1724. .omap4 = {
  1725. .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
  1726. .modulemode = MODULEMODE_SWCTRL,
  1727. },
  1728. },
  1729. };
  1730. /* tptc2 */
  1731. static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
  1732. { .irq = 114 + OMAP_INTC_START, },
  1733. { .irq = -1 },
  1734. };
  1735. static struct omap_hwmod am33xx_tptc2_hwmod = {
  1736. .name = "tptc2",
  1737. .class = &am33xx_tptc_hwmod_class,
  1738. .clkdm_name = "l3_clkdm",
  1739. .mpu_irqs = am33xx_tptc2_irqs,
  1740. .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
  1741. .main_clk = "l3_gclk",
  1742. .prcm = {
  1743. .omap4 = {
  1744. .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
  1745. .modulemode = MODULEMODE_SWCTRL,
  1746. },
  1747. },
  1748. };
  1749. /* 'uart' class */
  1750. static struct omap_hwmod_class_sysconfig uart_sysc = {
  1751. .rev_offs = 0x50,
  1752. .sysc_offs = 0x54,
  1753. .syss_offs = 0x58,
  1754. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
  1755. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  1756. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1757. SIDLE_SMART_WKUP),
  1758. .sysc_fields = &omap_hwmod_sysc_type1,
  1759. };
  1760. static struct omap_hwmod_class uart_class = {
  1761. .name = "uart",
  1762. .sysc = &uart_sysc,
  1763. };
  1764. /* uart1 */
  1765. static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
  1766. { .name = "tx", .dma_req = 26, },
  1767. { .name = "rx", .dma_req = 27, },
  1768. { .dma_req = -1 }
  1769. };
  1770. static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
  1771. { .irq = 72 + OMAP_INTC_START, },
  1772. { .irq = -1 },
  1773. };
  1774. static struct omap_hwmod am33xx_uart1_hwmod = {
  1775. .name = "uart1",
  1776. .class = &uart_class,
  1777. .clkdm_name = "l4_wkup_clkdm",
  1778. .mpu_irqs = am33xx_uart1_irqs,
  1779. .sdma_reqs = uart1_edma_reqs,
  1780. .main_clk = "dpll_per_m2_div4_wkupdm_ck",
  1781. .prcm = {
  1782. .omap4 = {
  1783. .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
  1784. .modulemode = MODULEMODE_SWCTRL,
  1785. },
  1786. },
  1787. };
  1788. static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
  1789. { .irq = 73 + OMAP_INTC_START, },
  1790. { .irq = -1 },
  1791. };
  1792. static struct omap_hwmod am33xx_uart2_hwmod = {
  1793. .name = "uart2",
  1794. .class = &uart_class,
  1795. .clkdm_name = "l4ls_clkdm",
  1796. .mpu_irqs = am33xx_uart2_irqs,
  1797. .sdma_reqs = uart1_edma_reqs,
  1798. .main_clk = "dpll_per_m2_div4_ck",
  1799. .prcm = {
  1800. .omap4 = {
  1801. .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
  1802. .modulemode = MODULEMODE_SWCTRL,
  1803. },
  1804. },
  1805. };
  1806. /* uart3 */
  1807. static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
  1808. { .name = "tx", .dma_req = 30, },
  1809. { .name = "rx", .dma_req = 31, },
  1810. { .dma_req = -1 }
  1811. };
  1812. static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
  1813. { .irq = 74 + OMAP_INTC_START, },
  1814. { .irq = -1 },
  1815. };
  1816. static struct omap_hwmod am33xx_uart3_hwmod = {
  1817. .name = "uart3",
  1818. .class = &uart_class,
  1819. .clkdm_name = "l4ls_clkdm",
  1820. .mpu_irqs = am33xx_uart3_irqs,
  1821. .sdma_reqs = uart3_edma_reqs,
  1822. .main_clk = "dpll_per_m2_div4_ck",
  1823. .prcm = {
  1824. .omap4 = {
  1825. .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
  1826. .modulemode = MODULEMODE_SWCTRL,
  1827. },
  1828. },
  1829. };
  1830. static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
  1831. { .irq = 44 + OMAP_INTC_START, },
  1832. { .irq = -1 },
  1833. };
  1834. static struct omap_hwmod am33xx_uart4_hwmod = {
  1835. .name = "uart4",
  1836. .class = &uart_class,
  1837. .clkdm_name = "l4ls_clkdm",
  1838. .mpu_irqs = am33xx_uart4_irqs,
  1839. .sdma_reqs = uart1_edma_reqs,
  1840. .main_clk = "dpll_per_m2_div4_ck",
  1841. .prcm = {
  1842. .omap4 = {
  1843. .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
  1844. .modulemode = MODULEMODE_SWCTRL,
  1845. },
  1846. },
  1847. };
  1848. static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
  1849. { .irq = 45 + OMAP_INTC_START, },
  1850. { .irq = -1 },
  1851. };
  1852. static struct omap_hwmod am33xx_uart5_hwmod = {
  1853. .name = "uart5",
  1854. .class = &uart_class,
  1855. .clkdm_name = "l4ls_clkdm",
  1856. .mpu_irqs = am33xx_uart5_irqs,
  1857. .sdma_reqs = uart1_edma_reqs,
  1858. .main_clk = "dpll_per_m2_div4_ck",
  1859. .prcm = {
  1860. .omap4 = {
  1861. .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
  1862. .modulemode = MODULEMODE_SWCTRL,
  1863. },
  1864. },
  1865. };
  1866. static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
  1867. { .irq = 46 + OMAP_INTC_START, },
  1868. { .irq = -1 },
  1869. };
  1870. static struct omap_hwmod am33xx_uart6_hwmod = {
  1871. .name = "uart6",
  1872. .class = &uart_class,
  1873. .clkdm_name = "l4ls_clkdm",
  1874. .mpu_irqs = am33xx_uart6_irqs,
  1875. .sdma_reqs = uart1_edma_reqs,
  1876. .main_clk = "dpll_per_m2_div4_ck",
  1877. .prcm = {
  1878. .omap4 = {
  1879. .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
  1880. .modulemode = MODULEMODE_SWCTRL,
  1881. },
  1882. },
  1883. };
  1884. /* 'wd_timer' class */
  1885. static struct omap_hwmod_class_sysconfig wdt_sysc = {
  1886. .rev_offs = 0x0,
  1887. .sysc_offs = 0x10,
  1888. .syss_offs = 0x14,
  1889. .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
  1890. SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  1891. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1892. SIDLE_SMART_WKUP),
  1893. .sysc_fields = &omap_hwmod_sysc_type1,
  1894. };
  1895. static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
  1896. .name = "wd_timer",
  1897. .sysc = &wdt_sysc,
  1898. .pre_shutdown = &omap2_wd_timer_disable,
  1899. };
  1900. /*
  1901. * XXX: device.c file uses hardcoded name for watchdog timer
  1902. * driver "wd_timer2, so we are also using same name as of now...
  1903. */
  1904. static struct omap_hwmod am33xx_wd_timer1_hwmod = {
  1905. .name = "wd_timer2",
  1906. .class = &am33xx_wd_timer_hwmod_class,
  1907. .clkdm_name = "l4_wkup_clkdm",
  1908. .flags = HWMOD_SWSUP_SIDLE,
  1909. .main_clk = "wdt1_fck",
  1910. .prcm = {
  1911. .omap4 = {
  1912. .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
  1913. .modulemode = MODULEMODE_SWCTRL,
  1914. },
  1915. },
  1916. };
  1917. /*
  1918. * 'usb_otg' class
  1919. * high-speed on-the-go universal serial bus (usb_otg) controller
  1920. */
  1921. static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
  1922. .rev_offs = 0x0,
  1923. .sysc_offs = 0x10,
  1924. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
  1925. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1926. MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  1927. .sysc_fields = &omap_hwmod_sysc_type2,
  1928. };
  1929. static struct omap_hwmod_class am33xx_usbotg_class = {
  1930. .name = "usbotg",
  1931. .sysc = &am33xx_usbhsotg_sysc,
  1932. };
  1933. static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
  1934. { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
  1935. { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
  1936. { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
  1937. { .irq = -1, },
  1938. };
  1939. static struct omap_hwmod am33xx_usbss_hwmod = {
  1940. .name = "usb_otg_hs",
  1941. .class = &am33xx_usbotg_class,
  1942. .clkdm_name = "l3s_clkdm",
  1943. .mpu_irqs = am33xx_usbss_mpu_irqs,
  1944. .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
  1945. .main_clk = "usbotg_fck",
  1946. .prcm = {
  1947. .omap4 = {
  1948. .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
  1949. .modulemode = MODULEMODE_SWCTRL,
  1950. },
  1951. },
  1952. };
  1953. /*
  1954. * Interfaces
  1955. */
  1956. /* l4 fw -> emif fw */
  1957. static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
  1958. .master = &am33xx_l4_fw_hwmod,
  1959. .slave = &am33xx_emif_fw_hwmod,
  1960. .clk = "l4fw_gclk",
  1961. .user = OCP_USER_MPU,
  1962. };
  1963. static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
  1964. {
  1965. .pa_start = 0x4c000000,
  1966. .pa_end = 0x4c000fff,
  1967. .flags = ADDR_TYPE_RT
  1968. },
  1969. { }
  1970. };
  1971. /* l3 main -> emif */
  1972. static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
  1973. .master = &am33xx_l3_main_hwmod,
  1974. .slave = &am33xx_emif_hwmod,
  1975. .clk = "dpll_core_m4_ck",
  1976. .addr = am33xx_emif_addrs,
  1977. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1978. };
  1979. /* mpu -> l3 main */
  1980. static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
  1981. .master = &am33xx_mpu_hwmod,
  1982. .slave = &am33xx_l3_main_hwmod,
  1983. .clk = "dpll_mpu_m2_ck",
  1984. .user = OCP_USER_MPU,
  1985. };
  1986. /* l3 main -> l4 hs */
  1987. static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
  1988. .master = &am33xx_l3_main_hwmod,
  1989. .slave = &am33xx_l4_hs_hwmod,
  1990. .clk = "l3s_gclk",
  1991. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1992. };
  1993. /* l3 main -> l3 s */
  1994. static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
  1995. .master = &am33xx_l3_main_hwmod,
  1996. .slave = &am33xx_l3_s_hwmod,
  1997. .clk = "l3s_gclk",
  1998. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1999. };
  2000. /* l3 s -> l4 per/ls */
  2001. static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
  2002. .master = &am33xx_l3_s_hwmod,
  2003. .slave = &am33xx_l4_ls_hwmod,
  2004. .clk = "l3s_gclk",
  2005. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2006. };
  2007. /* l3 s -> l4 wkup */
  2008. static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
  2009. .master = &am33xx_l3_s_hwmod,
  2010. .slave = &am33xx_l4_wkup_hwmod,
  2011. .clk = "l3s_gclk",
  2012. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2013. };
  2014. /* l3 s -> l4 fw */
  2015. static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
  2016. .master = &am33xx_l3_s_hwmod,
  2017. .slave = &am33xx_l4_fw_hwmod,
  2018. .clk = "l3s_gclk",
  2019. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2020. };
  2021. /* l3 main -> l3 instr */
  2022. static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
  2023. .master = &am33xx_l3_main_hwmod,
  2024. .slave = &am33xx_l3_instr_hwmod,
  2025. .clk = "l3s_gclk",
  2026. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2027. };
  2028. /* mpu -> prcm */
  2029. static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
  2030. .master = &am33xx_mpu_hwmod,
  2031. .slave = &am33xx_prcm_hwmod,
  2032. .clk = "dpll_mpu_m2_ck",
  2033. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2034. };
  2035. /* l3 s -> l3 main*/
  2036. static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
  2037. .master = &am33xx_l3_s_hwmod,
  2038. .slave = &am33xx_l3_main_hwmod,
  2039. .clk = "l3s_gclk",
  2040. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2041. };
  2042. /* pru-icss -> l3 main */
  2043. static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
  2044. .master = &am33xx_pruss_hwmod,
  2045. .slave = &am33xx_l3_main_hwmod,
  2046. .clk = "l3_gclk",
  2047. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2048. };
  2049. /* wkup m3 -> l4 wkup */
  2050. static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
  2051. .master = &am33xx_wkup_m3_hwmod,
  2052. .slave = &am33xx_l4_wkup_hwmod,
  2053. .clk = "dpll_core_m4_div2_ck",
  2054. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2055. };
  2056. /* gfx -> l3 main */
  2057. static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
  2058. .master = &am33xx_gfx_hwmod,
  2059. .slave = &am33xx_l3_main_hwmod,
  2060. .clk = "dpll_core_m4_ck",
  2061. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2062. };
  2063. /* l4 wkup -> wkup m3 */
  2064. static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
  2065. {
  2066. .name = "umem",
  2067. .pa_start = 0x44d00000,
  2068. .pa_end = 0x44d00000 + SZ_16K - 1,
  2069. .flags = ADDR_TYPE_RT
  2070. },
  2071. {
  2072. .name = "dmem",
  2073. .pa_start = 0x44d80000,
  2074. .pa_end = 0x44d80000 + SZ_8K - 1,
  2075. .flags = ADDR_TYPE_RT
  2076. },
  2077. { }
  2078. };
  2079. static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
  2080. .master = &am33xx_l4_wkup_hwmod,
  2081. .slave = &am33xx_wkup_m3_hwmod,
  2082. .clk = "dpll_core_m4_div2_ck",
  2083. .addr = am33xx_wkup_m3_addrs,
  2084. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2085. };
  2086. /* l4 hs -> pru-icss */
  2087. static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
  2088. {
  2089. .pa_start = 0x4a300000,
  2090. .pa_end = 0x4a300000 + SZ_512K - 1,
  2091. .flags = ADDR_TYPE_RT
  2092. },
  2093. { }
  2094. };
  2095. static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
  2096. .master = &am33xx_l4_hs_hwmod,
  2097. .slave = &am33xx_pruss_hwmod,
  2098. .clk = "dpll_core_m4_ck",
  2099. .addr = am33xx_pruss_addrs,
  2100. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2101. };
  2102. /* l3 main -> gfx */
  2103. static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
  2104. {
  2105. .pa_start = 0x56000000,
  2106. .pa_end = 0x56000000 + SZ_16M - 1,
  2107. .flags = ADDR_TYPE_RT
  2108. },
  2109. { }
  2110. };
  2111. static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
  2112. .master = &am33xx_l3_main_hwmod,
  2113. .slave = &am33xx_gfx_hwmod,
  2114. .clk = "dpll_core_m4_ck",
  2115. .addr = am33xx_gfx_addrs,
  2116. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2117. };
  2118. /* l4 wkup -> smartreflex0 */
  2119. static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
  2120. {
  2121. .pa_start = 0x44e37000,
  2122. .pa_end = 0x44e37000 + SZ_4K - 1,
  2123. .flags = ADDR_TYPE_RT
  2124. },
  2125. { }
  2126. };
  2127. static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
  2128. .master = &am33xx_l4_wkup_hwmod,
  2129. .slave = &am33xx_smartreflex0_hwmod,
  2130. .clk = "dpll_core_m4_div2_ck",
  2131. .addr = am33xx_smartreflex0_addrs,
  2132. .user = OCP_USER_MPU,
  2133. };
  2134. /* l4 wkup -> smartreflex1 */
  2135. static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
  2136. {
  2137. .pa_start = 0x44e39000,
  2138. .pa_end = 0x44e39000 + SZ_4K - 1,
  2139. .flags = ADDR_TYPE_RT
  2140. },
  2141. { }
  2142. };
  2143. static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
  2144. .master = &am33xx_l4_wkup_hwmod,
  2145. .slave = &am33xx_smartreflex1_hwmod,
  2146. .clk = "dpll_core_m4_div2_ck",
  2147. .addr = am33xx_smartreflex1_addrs,
  2148. .user = OCP_USER_MPU,
  2149. };
  2150. /* l4 wkup -> control */
  2151. static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
  2152. {
  2153. .pa_start = 0x44e10000,
  2154. .pa_end = 0x44e10000 + SZ_8K - 1,
  2155. .flags = ADDR_TYPE_RT
  2156. },
  2157. { }
  2158. };
  2159. static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
  2160. .master = &am33xx_l4_wkup_hwmod,
  2161. .slave = &am33xx_control_hwmod,
  2162. .clk = "dpll_core_m4_div2_ck",
  2163. .addr = am33xx_control_addrs,
  2164. .user = OCP_USER_MPU,
  2165. };
  2166. /* l4 wkup -> rtc */
  2167. static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
  2168. {
  2169. .pa_start = 0x44e3e000,
  2170. .pa_end = 0x44e3e000 + SZ_4K - 1,
  2171. .flags = ADDR_TYPE_RT
  2172. },
  2173. { }
  2174. };
  2175. static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
  2176. .master = &am33xx_l4_wkup_hwmod,
  2177. .slave = &am33xx_rtc_hwmod,
  2178. .clk = "clkdiv32k_ick",
  2179. .addr = am33xx_rtc_addrs,
  2180. .user = OCP_USER_MPU,
  2181. };
  2182. /* l4 per/ls -> DCAN0 */
  2183. static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
  2184. {
  2185. .pa_start = 0x481CC000,
  2186. .pa_end = 0x481CC000 + SZ_4K - 1,
  2187. .flags = ADDR_TYPE_RT
  2188. },
  2189. { }
  2190. };
  2191. static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
  2192. .master = &am33xx_l4_ls_hwmod,
  2193. .slave = &am33xx_dcan0_hwmod,
  2194. .clk = "l4ls_gclk",
  2195. .addr = am33xx_dcan0_addrs,
  2196. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2197. };
  2198. /* l4 per/ls -> DCAN1 */
  2199. static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
  2200. {
  2201. .pa_start = 0x481D0000,
  2202. .pa_end = 0x481D0000 + SZ_4K - 1,
  2203. .flags = ADDR_TYPE_RT
  2204. },
  2205. { }
  2206. };
  2207. static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
  2208. .master = &am33xx_l4_ls_hwmod,
  2209. .slave = &am33xx_dcan1_hwmod,
  2210. .clk = "l4ls_gclk",
  2211. .addr = am33xx_dcan1_addrs,
  2212. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2213. };
  2214. /* l4 per/ls -> GPIO2 */
  2215. static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
  2216. {
  2217. .pa_start = 0x4804C000,
  2218. .pa_end = 0x4804C000 + SZ_4K - 1,
  2219. .flags = ADDR_TYPE_RT,
  2220. },
  2221. { }
  2222. };
  2223. static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
  2224. .master = &am33xx_l4_ls_hwmod,
  2225. .slave = &am33xx_gpio1_hwmod,
  2226. .clk = "l4ls_gclk",
  2227. .addr = am33xx_gpio1_addrs,
  2228. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2229. };
  2230. /* l4 per/ls -> gpio3 */
  2231. static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
  2232. {
  2233. .pa_start = 0x481AC000,
  2234. .pa_end = 0x481AC000 + SZ_4K - 1,
  2235. .flags = ADDR_TYPE_RT,
  2236. },
  2237. { }
  2238. };
  2239. static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
  2240. .master = &am33xx_l4_ls_hwmod,
  2241. .slave = &am33xx_gpio2_hwmod,
  2242. .clk = "l4ls_gclk",
  2243. .addr = am33xx_gpio2_addrs,
  2244. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2245. };
  2246. /* l4 per/ls -> gpio4 */
  2247. static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
  2248. {
  2249. .pa_start = 0x481AE000,
  2250. .pa_end = 0x481AE000 + SZ_4K - 1,
  2251. .flags = ADDR_TYPE_RT,
  2252. },
  2253. { }
  2254. };
  2255. static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
  2256. .master = &am33xx_l4_ls_hwmod,
  2257. .slave = &am33xx_gpio3_hwmod,
  2258. .clk = "l4ls_gclk",
  2259. .addr = am33xx_gpio3_addrs,
  2260. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2261. };
  2262. /* L4 WKUP -> I2C1 */
  2263. static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
  2264. {
  2265. .pa_start = 0x44E0B000,
  2266. .pa_end = 0x44E0B000 + SZ_4K - 1,
  2267. .flags = ADDR_TYPE_RT,
  2268. },
  2269. { }
  2270. };
  2271. static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
  2272. .master = &am33xx_l4_wkup_hwmod,
  2273. .slave = &am33xx_i2c1_hwmod,
  2274. .clk = "dpll_core_m4_div2_ck",
  2275. .addr = am33xx_i2c1_addr_space,
  2276. .user = OCP_USER_MPU,
  2277. };
  2278. /* L4 WKUP -> GPIO1 */
  2279. static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
  2280. {
  2281. .pa_start = 0x44E07000,
  2282. .pa_end = 0x44E07000 + SZ_4K - 1,
  2283. .flags = ADDR_TYPE_RT,
  2284. },
  2285. { }
  2286. };
  2287. static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
  2288. .master = &am33xx_l4_wkup_hwmod,
  2289. .slave = &am33xx_gpio0_hwmod,
  2290. .clk = "dpll_core_m4_div2_ck",
  2291. .addr = am33xx_gpio0_addrs,
  2292. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2293. };
  2294. /* L4 WKUP -> ADC_TSC */
  2295. static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
  2296. {
  2297. .pa_start = 0x44E0D000,
  2298. .pa_end = 0x44E0D000 + SZ_8K - 1,
  2299. .flags = ADDR_TYPE_RT
  2300. },
  2301. { }
  2302. };
  2303. static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
  2304. .master = &am33xx_l4_wkup_hwmod,
  2305. .slave = &am33xx_adc_tsc_hwmod,
  2306. .clk = "dpll_core_m4_div2_ck",
  2307. .addr = am33xx_adc_tsc_addrs,
  2308. .user = OCP_USER_MPU,
  2309. };
  2310. static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
  2311. /* cpsw ss */
  2312. {
  2313. .pa_start = 0x4a100000,
  2314. .pa_end = 0x4a100000 + SZ_2K - 1,
  2315. },
  2316. /* cpsw wr */
  2317. {
  2318. .pa_start = 0x4a101200,
  2319. .pa_end = 0x4a101200 + SZ_256 - 1,
  2320. .flags = ADDR_TYPE_RT,
  2321. },
  2322. { }
  2323. };
  2324. static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
  2325. .master = &am33xx_l4_hs_hwmod,
  2326. .slave = &am33xx_cpgmac0_hwmod,
  2327. .clk = "cpsw_125mhz_gclk",
  2328. .addr = am33xx_cpgmac0_addr_space,
  2329. .user = OCP_USER_MPU,
  2330. };
  2331. static struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
  2332. {
  2333. .pa_start = 0x4A101000,
  2334. .pa_end = 0x4A101000 + SZ_256 - 1,
  2335. },
  2336. { }
  2337. };
  2338. static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
  2339. .master = &am33xx_cpgmac0_hwmod,
  2340. .slave = &am33xx_mdio_hwmod,
  2341. .addr = am33xx_mdio_addr_space,
  2342. .user = OCP_USER_MPU,
  2343. };
  2344. static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
  2345. {
  2346. .pa_start = 0x48080000,
  2347. .pa_end = 0x48080000 + SZ_8K - 1,
  2348. .flags = ADDR_TYPE_RT
  2349. },
  2350. { }
  2351. };
  2352. static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
  2353. .master = &am33xx_l4_ls_hwmod,
  2354. .slave = &am33xx_elm_hwmod,
  2355. .clk = "l4ls_gclk",
  2356. .addr = am33xx_elm_addr_space,
  2357. .user = OCP_USER_MPU,
  2358. };
  2359. static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
  2360. {
  2361. .pa_start = 0x48300000,
  2362. .pa_end = 0x48300000 + SZ_16 - 1,
  2363. .flags = ADDR_TYPE_RT
  2364. },
  2365. { }
  2366. };
  2367. static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
  2368. .master = &am33xx_l4_ls_hwmod,
  2369. .slave = &am33xx_epwmss0_hwmod,
  2370. .clk = "l4ls_gclk",
  2371. .addr = am33xx_epwmss0_addr_space,
  2372. .user = OCP_USER_MPU,
  2373. };
  2374. static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
  2375. {
  2376. .pa_start = 0x48300100,
  2377. .pa_end = 0x48300100 + SZ_128 - 1,
  2378. },
  2379. { }
  2380. };
  2381. static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
  2382. .master = &am33xx_epwmss0_hwmod,
  2383. .slave = &am33xx_ecap0_hwmod,
  2384. .clk = "l4ls_gclk",
  2385. .addr = am33xx_ecap0_addr_space,
  2386. .user = OCP_USER_MPU,
  2387. };
  2388. static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
  2389. {
  2390. .pa_start = 0x48300180,
  2391. .pa_end = 0x48300180 + SZ_128 - 1,
  2392. },
  2393. { }
  2394. };
  2395. static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
  2396. .master = &am33xx_epwmss0_hwmod,
  2397. .slave = &am33xx_eqep0_hwmod,
  2398. .clk = "l4ls_gclk",
  2399. .addr = am33xx_eqep0_addr_space,
  2400. .user = OCP_USER_MPU,
  2401. };
  2402. static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
  2403. {
  2404. .pa_start = 0x48300200,
  2405. .pa_end = 0x48300200 + SZ_128 - 1,
  2406. },
  2407. { }
  2408. };
  2409. static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
  2410. .master = &am33xx_epwmss0_hwmod,
  2411. .slave = &am33xx_ehrpwm0_hwmod,
  2412. .clk = "l4ls_gclk",
  2413. .addr = am33xx_ehrpwm0_addr_space,
  2414. .user = OCP_USER_MPU,
  2415. };
  2416. static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
  2417. {
  2418. .pa_start = 0x48302000,
  2419. .pa_end = 0x48302000 + SZ_16 - 1,
  2420. .flags = ADDR_TYPE_RT
  2421. },
  2422. { }
  2423. };
  2424. static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
  2425. .master = &am33xx_l4_ls_hwmod,
  2426. .slave = &am33xx_epwmss1_hwmod,
  2427. .clk = "l4ls_gclk",
  2428. .addr = am33xx_epwmss1_addr_space,
  2429. .user = OCP_USER_MPU,
  2430. };
  2431. static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
  2432. {
  2433. .pa_start = 0x48302100,
  2434. .pa_end = 0x48302100 + SZ_128 - 1,
  2435. },
  2436. { }
  2437. };
  2438. static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
  2439. .master = &am33xx_epwmss1_hwmod,
  2440. .slave = &am33xx_ecap1_hwmod,
  2441. .clk = "l4ls_gclk",
  2442. .addr = am33xx_ecap1_addr_space,
  2443. .user = OCP_USER_MPU,
  2444. };
  2445. static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
  2446. {
  2447. .pa_start = 0x48302180,
  2448. .pa_end = 0x48302180 + SZ_128 - 1,
  2449. },
  2450. { }
  2451. };
  2452. static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
  2453. .master = &am33xx_epwmss1_hwmod,
  2454. .slave = &am33xx_eqep1_hwmod,
  2455. .clk = "l4ls_gclk",
  2456. .addr = am33xx_eqep1_addr_space,
  2457. .user = OCP_USER_MPU,
  2458. };
  2459. static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
  2460. {
  2461. .pa_start = 0x48302200,
  2462. .pa_end = 0x48302200 + SZ_128 - 1,
  2463. },
  2464. { }
  2465. };
  2466. static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
  2467. .master = &am33xx_epwmss1_hwmod,
  2468. .slave = &am33xx_ehrpwm1_hwmod,
  2469. .clk = "l4ls_gclk",
  2470. .addr = am33xx_ehrpwm1_addr_space,
  2471. .user = OCP_USER_MPU,
  2472. };
  2473. static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
  2474. {
  2475. .pa_start = 0x48304000,
  2476. .pa_end = 0x48304000 + SZ_16 - 1,
  2477. .flags = ADDR_TYPE_RT
  2478. },
  2479. { }
  2480. };
  2481. static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
  2482. .master = &am33xx_l4_ls_hwmod,
  2483. .slave = &am33xx_epwmss2_hwmod,
  2484. .clk = "l4ls_gclk",
  2485. .addr = am33xx_epwmss2_addr_space,
  2486. .user = OCP_USER_MPU,
  2487. };
  2488. static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
  2489. {
  2490. .pa_start = 0x48304100,
  2491. .pa_end = 0x48304100 + SZ_128 - 1,
  2492. },
  2493. { }
  2494. };
  2495. static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
  2496. .master = &am33xx_epwmss2_hwmod,
  2497. .slave = &am33xx_ecap2_hwmod,
  2498. .clk = "l4ls_gclk",
  2499. .addr = am33xx_ecap2_addr_space,
  2500. .user = OCP_USER_MPU,
  2501. };
  2502. static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
  2503. {
  2504. .pa_start = 0x48304180,
  2505. .pa_end = 0x48304180 + SZ_128 - 1,
  2506. },
  2507. { }
  2508. };
  2509. static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
  2510. .master = &am33xx_epwmss2_hwmod,
  2511. .slave = &am33xx_eqep2_hwmod,
  2512. .clk = "l4ls_gclk",
  2513. .addr = am33xx_eqep2_addr_space,
  2514. .user = OCP_USER_MPU,
  2515. };
  2516. static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
  2517. {
  2518. .pa_start = 0x48304200,
  2519. .pa_end = 0x48304200 + SZ_128 - 1,
  2520. },
  2521. { }
  2522. };
  2523. static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
  2524. .master = &am33xx_epwmss2_hwmod,
  2525. .slave = &am33xx_ehrpwm2_hwmod,
  2526. .clk = "l4ls_gclk",
  2527. .addr = am33xx_ehrpwm2_addr_space,
  2528. .user = OCP_USER_MPU,
  2529. };
  2530. /* l3s cfg -> gpmc */
  2531. static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
  2532. {
  2533. .pa_start = 0x50000000,
  2534. .pa_end = 0x50000000 + SZ_8K - 1,
  2535. .flags = ADDR_TYPE_RT,
  2536. },
  2537. { }
  2538. };
  2539. static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
  2540. .master = &am33xx_l3_s_hwmod,
  2541. .slave = &am33xx_gpmc_hwmod,
  2542. .clk = "l3s_gclk",
  2543. .addr = am33xx_gpmc_addr_space,
  2544. .user = OCP_USER_MPU,
  2545. };
  2546. /* i2c2 */
  2547. static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
  2548. {
  2549. .pa_start = 0x4802A000,
  2550. .pa_end = 0x4802A000 + SZ_4K - 1,
  2551. .flags = ADDR_TYPE_RT,
  2552. },
  2553. { }
  2554. };
  2555. static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
  2556. .master = &am33xx_l4_ls_hwmod,
  2557. .slave = &am33xx_i2c2_hwmod,
  2558. .clk = "l4ls_gclk",
  2559. .addr = am33xx_i2c2_addr_space,
  2560. .user = OCP_USER_MPU,
  2561. };
  2562. static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
  2563. {
  2564. .pa_start = 0x4819C000,
  2565. .pa_end = 0x4819C000 + SZ_4K - 1,
  2566. .flags = ADDR_TYPE_RT
  2567. },
  2568. { }
  2569. };
  2570. static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
  2571. .master = &am33xx_l4_ls_hwmod,
  2572. .slave = &am33xx_i2c3_hwmod,
  2573. .clk = "l4ls_gclk",
  2574. .addr = am33xx_i2c3_addr_space,
  2575. .user = OCP_USER_MPU,
  2576. };
  2577. static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
  2578. {
  2579. .pa_start = 0x4830E000,
  2580. .pa_end = 0x4830E000 + SZ_8K - 1,
  2581. .flags = ADDR_TYPE_RT,
  2582. },
  2583. { }
  2584. };
  2585. static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
  2586. .master = &am33xx_l3_main_hwmod,
  2587. .slave = &am33xx_lcdc_hwmod,
  2588. .clk = "dpll_core_m4_ck",
  2589. .addr = am33xx_lcdc_addr_space,
  2590. .user = OCP_USER_MPU,
  2591. };
  2592. static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
  2593. {
  2594. .pa_start = 0x480C8000,
  2595. .pa_end = 0x480C8000 + (SZ_4K - 1),
  2596. .flags = ADDR_TYPE_RT
  2597. },
  2598. { }
  2599. };
  2600. /* l4 ls -> mailbox */
  2601. static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
  2602. .master = &am33xx_l4_ls_hwmod,
  2603. .slave = &am33xx_mailbox_hwmod,
  2604. .clk = "l4ls_gclk",
  2605. .addr = am33xx_mailbox_addrs,
  2606. .user = OCP_USER_MPU,
  2607. };
  2608. /* l4 ls -> spinlock */
  2609. static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
  2610. {
  2611. .pa_start = 0x480Ca000,
  2612. .pa_end = 0x480Ca000 + SZ_4K - 1,
  2613. .flags = ADDR_TYPE_RT
  2614. },
  2615. { }
  2616. };
  2617. static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
  2618. .master = &am33xx_l4_ls_hwmod,
  2619. .slave = &am33xx_spinlock_hwmod,
  2620. .clk = "l4ls_gclk",
  2621. .addr = am33xx_spinlock_addrs,
  2622. .user = OCP_USER_MPU,
  2623. };
  2624. /* l4 ls -> mcasp0 */
  2625. static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
  2626. {
  2627. .pa_start = 0x48038000,
  2628. .pa_end = 0x48038000 + SZ_8K - 1,
  2629. .flags = ADDR_TYPE_RT
  2630. },
  2631. { }
  2632. };
  2633. static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
  2634. .master = &am33xx_l4_ls_hwmod,
  2635. .slave = &am33xx_mcasp0_hwmod,
  2636. .clk = "l4ls_gclk",
  2637. .addr = am33xx_mcasp0_addr_space,
  2638. .user = OCP_USER_MPU,
  2639. };
  2640. /* l3 s -> mcasp0 data */
  2641. static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
  2642. {
  2643. .pa_start = 0x46000000,
  2644. .pa_end = 0x46000000 + SZ_4M - 1,
  2645. .flags = ADDR_TYPE_RT
  2646. },
  2647. { }
  2648. };
  2649. static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
  2650. .master = &am33xx_l3_s_hwmod,
  2651. .slave = &am33xx_mcasp0_hwmod,
  2652. .clk = "l3s_gclk",
  2653. .addr = am33xx_mcasp0_data_addr_space,
  2654. .user = OCP_USER_SDMA,
  2655. };
  2656. /* l4 ls -> mcasp1 */
  2657. static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
  2658. {
  2659. .pa_start = 0x4803C000,
  2660. .pa_end = 0x4803C000 + SZ_8K - 1,
  2661. .flags = ADDR_TYPE_RT
  2662. },
  2663. { }
  2664. };
  2665. static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
  2666. .master = &am33xx_l4_ls_hwmod,
  2667. .slave = &am33xx_mcasp1_hwmod,
  2668. .clk = "l4ls_gclk",
  2669. .addr = am33xx_mcasp1_addr_space,
  2670. .user = OCP_USER_MPU,
  2671. };
  2672. /* l3 s -> mcasp1 data */
  2673. static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
  2674. {
  2675. .pa_start = 0x46400000,
  2676. .pa_end = 0x46400000 + SZ_4M - 1,
  2677. .flags = ADDR_TYPE_RT
  2678. },
  2679. { }
  2680. };
  2681. static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
  2682. .master = &am33xx_l3_s_hwmod,
  2683. .slave = &am33xx_mcasp1_hwmod,
  2684. .clk = "l3s_gclk",
  2685. .addr = am33xx_mcasp1_data_addr_space,
  2686. .user = OCP_USER_SDMA,
  2687. };
  2688. /* l4 ls -> mmc0 */
  2689. static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
  2690. {
  2691. .pa_start = 0x48060100,
  2692. .pa_end = 0x48060100 + SZ_4K - 1,
  2693. .flags = ADDR_TYPE_RT,
  2694. },
  2695. { }
  2696. };
  2697. static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
  2698. .master = &am33xx_l4_ls_hwmod,
  2699. .slave = &am33xx_mmc0_hwmod,
  2700. .clk = "l4ls_gclk",
  2701. .addr = am33xx_mmc0_addr_space,
  2702. .user = OCP_USER_MPU,
  2703. };
  2704. /* l4 ls -> mmc1 */
  2705. static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
  2706. {
  2707. .pa_start = 0x481d8100,
  2708. .pa_end = 0x481d8100 + SZ_4K - 1,
  2709. .flags = ADDR_TYPE_RT,
  2710. },
  2711. { }
  2712. };
  2713. static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
  2714. .master = &am33xx_l4_ls_hwmod,
  2715. .slave = &am33xx_mmc1_hwmod,
  2716. .clk = "l4ls_gclk",
  2717. .addr = am33xx_mmc1_addr_space,
  2718. .user = OCP_USER_MPU,
  2719. };
  2720. /* l3 s -> mmc2 */
  2721. static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
  2722. {
  2723. .pa_start = 0x47810100,
  2724. .pa_end = 0x47810100 + SZ_64K - 1,
  2725. .flags = ADDR_TYPE_RT,
  2726. },
  2727. { }
  2728. };
  2729. static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
  2730. .master = &am33xx_l3_s_hwmod,
  2731. .slave = &am33xx_mmc2_hwmod,
  2732. .clk = "l3s_gclk",
  2733. .addr = am33xx_mmc2_addr_space,
  2734. .user = OCP_USER_MPU,
  2735. };
  2736. /* l4 ls -> mcspi0 */
  2737. static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
  2738. {
  2739. .pa_start = 0x48030000,
  2740. .pa_end = 0x48030000 + SZ_1K - 1,
  2741. .flags = ADDR_TYPE_RT,
  2742. },
  2743. { }
  2744. };
  2745. static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
  2746. .master = &am33xx_l4_ls_hwmod,
  2747. .slave = &am33xx_spi0_hwmod,
  2748. .clk = "l4ls_gclk",
  2749. .addr = am33xx_mcspi0_addr_space,
  2750. .user = OCP_USER_MPU,
  2751. };
  2752. /* l4 ls -> mcspi1 */
  2753. static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
  2754. {
  2755. .pa_start = 0x481A0000,
  2756. .pa_end = 0x481A0000 + SZ_1K - 1,
  2757. .flags = ADDR_TYPE_RT,
  2758. },
  2759. { }
  2760. };
  2761. static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
  2762. .master = &am33xx_l4_ls_hwmod,
  2763. .slave = &am33xx_spi1_hwmod,
  2764. .clk = "l4ls_gclk",
  2765. .addr = am33xx_mcspi1_addr_space,
  2766. .user = OCP_USER_MPU,
  2767. };
  2768. /* l4 wkup -> timer1 */
  2769. static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
  2770. {
  2771. .pa_start = 0x44E31000,
  2772. .pa_end = 0x44E31000 + SZ_1K - 1,
  2773. .flags = ADDR_TYPE_RT
  2774. },
  2775. { }
  2776. };
  2777. static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
  2778. .master = &am33xx_l4_wkup_hwmod,
  2779. .slave = &am33xx_timer1_hwmod,
  2780. .clk = "dpll_core_m4_div2_ck",
  2781. .addr = am33xx_timer1_addr_space,
  2782. .user = OCP_USER_MPU,
  2783. };
  2784. /* l4 per -> timer2 */
  2785. static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
  2786. {
  2787. .pa_start = 0x48040000,
  2788. .pa_end = 0x48040000 + SZ_1K - 1,
  2789. .flags = ADDR_TYPE_RT
  2790. },
  2791. { }
  2792. };
  2793. static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
  2794. .master = &am33xx_l4_ls_hwmod,
  2795. .slave = &am33xx_timer2_hwmod,
  2796. .clk = "l4ls_gclk",
  2797. .addr = am33xx_timer2_addr_space,
  2798. .user = OCP_USER_MPU,
  2799. };
  2800. /* l4 per -> timer3 */
  2801. static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
  2802. {
  2803. .pa_start = 0x48042000,
  2804. .pa_end = 0x48042000 + SZ_1K - 1,
  2805. .flags = ADDR_TYPE_RT
  2806. },
  2807. { }
  2808. };
  2809. static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
  2810. .master = &am33xx_l4_ls_hwmod,
  2811. .slave = &am33xx_timer3_hwmod,
  2812. .clk = "l4ls_gclk",
  2813. .addr = am33xx_timer3_addr_space,
  2814. .user = OCP_USER_MPU,
  2815. };
  2816. /* l4 per -> timer4 */
  2817. static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
  2818. {
  2819. .pa_start = 0x48044000,
  2820. .pa_end = 0x48044000 + SZ_1K - 1,
  2821. .flags = ADDR_TYPE_RT
  2822. },
  2823. { }
  2824. };
  2825. static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
  2826. .master = &am33xx_l4_ls_hwmod,
  2827. .slave = &am33xx_timer4_hwmod,
  2828. .clk = "l4ls_gclk",
  2829. .addr = am33xx_timer4_addr_space,
  2830. .user = OCP_USER_MPU,
  2831. };
  2832. /* l4 per -> timer5 */
  2833. static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
  2834. {
  2835. .pa_start = 0x48046000,
  2836. .pa_end = 0x48046000 + SZ_1K - 1,
  2837. .flags = ADDR_TYPE_RT
  2838. },
  2839. { }
  2840. };
  2841. static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
  2842. .master = &am33xx_l4_ls_hwmod,
  2843. .slave = &am33xx_timer5_hwmod,
  2844. .clk = "l4ls_gclk",
  2845. .addr = am33xx_timer5_addr_space,
  2846. .user = OCP_USER_MPU,
  2847. };
  2848. /* l4 per -> timer6 */
  2849. static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
  2850. {
  2851. .pa_start = 0x48048000,
  2852. .pa_end = 0x48048000 + SZ_1K - 1,
  2853. .flags = ADDR_TYPE_RT
  2854. },
  2855. { }
  2856. };
  2857. static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
  2858. .master = &am33xx_l4_ls_hwmod,
  2859. .slave = &am33xx_timer6_hwmod,
  2860. .clk = "l4ls_gclk",
  2861. .addr = am33xx_timer6_addr_space,
  2862. .user = OCP_USER_MPU,
  2863. };
  2864. /* l4 per -> timer7 */
  2865. static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
  2866. {
  2867. .pa_start = 0x4804A000,
  2868. .pa_end = 0x4804A000 + SZ_1K - 1,
  2869. .flags = ADDR_TYPE_RT
  2870. },
  2871. { }
  2872. };
  2873. static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
  2874. .master = &am33xx_l4_ls_hwmod,
  2875. .slave = &am33xx_timer7_hwmod,
  2876. .clk = "l4ls_gclk",
  2877. .addr = am33xx_timer7_addr_space,
  2878. .user = OCP_USER_MPU,
  2879. };
  2880. /* l3 main -> tpcc */
  2881. static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
  2882. {
  2883. .pa_start = 0x49000000,
  2884. .pa_end = 0x49000000 + SZ_32K - 1,
  2885. .flags = ADDR_TYPE_RT
  2886. },
  2887. { }
  2888. };
  2889. static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
  2890. .master = &am33xx_l3_main_hwmod,
  2891. .slave = &am33xx_tpcc_hwmod,
  2892. .clk = "l3_gclk",
  2893. .addr = am33xx_tpcc_addr_space,
  2894. .user = OCP_USER_MPU,
  2895. };
  2896. /* l3 main -> tpcc0 */
  2897. static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
  2898. {
  2899. .pa_start = 0x49800000,
  2900. .pa_end = 0x49800000 + SZ_8K - 1,
  2901. .flags = ADDR_TYPE_RT,
  2902. },
  2903. { }
  2904. };
  2905. static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
  2906. .master = &am33xx_l3_main_hwmod,
  2907. .slave = &am33xx_tptc0_hwmod,
  2908. .clk = "l3_gclk",
  2909. .addr = am33xx_tptc0_addr_space,
  2910. .user = OCP_USER_MPU,
  2911. };
  2912. /* l3 main -> tpcc1 */
  2913. static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
  2914. {
  2915. .pa_start = 0x49900000,
  2916. .pa_end = 0x49900000 + SZ_8K - 1,
  2917. .flags = ADDR_TYPE_RT,
  2918. },
  2919. { }
  2920. };
  2921. static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
  2922. .master = &am33xx_l3_main_hwmod,
  2923. .slave = &am33xx_tptc1_hwmod,
  2924. .clk = "l3_gclk",
  2925. .addr = am33xx_tptc1_addr_space,
  2926. .user = OCP_USER_MPU,
  2927. };
  2928. /* l3 main -> tpcc2 */
  2929. static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
  2930. {
  2931. .pa_start = 0x49a00000,
  2932. .pa_end = 0x49a00000 + SZ_8K - 1,
  2933. .flags = ADDR_TYPE_RT,
  2934. },
  2935. { }
  2936. };
  2937. static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
  2938. .master = &am33xx_l3_main_hwmod,
  2939. .slave = &am33xx_tptc2_hwmod,
  2940. .clk = "l3_gclk",
  2941. .addr = am33xx_tptc2_addr_space,
  2942. .user = OCP_USER_MPU,
  2943. };
  2944. /* l4 wkup -> uart1 */
  2945. static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
  2946. {
  2947. .pa_start = 0x44E09000,
  2948. .pa_end = 0x44E09000 + SZ_8K - 1,
  2949. .flags = ADDR_TYPE_RT,
  2950. },
  2951. { }
  2952. };
  2953. static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
  2954. .master = &am33xx_l4_wkup_hwmod,
  2955. .slave = &am33xx_uart1_hwmod,
  2956. .clk = "dpll_core_m4_div2_ck",
  2957. .addr = am33xx_uart1_addr_space,
  2958. .user = OCP_USER_MPU,
  2959. };
  2960. /* l4 ls -> uart2 */
  2961. static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
  2962. {
  2963. .pa_start = 0x48022000,
  2964. .pa_end = 0x48022000 + SZ_8K - 1,
  2965. .flags = ADDR_TYPE_RT,
  2966. },
  2967. { }
  2968. };
  2969. static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
  2970. .master = &am33xx_l4_ls_hwmod,
  2971. .slave = &am33xx_uart2_hwmod,
  2972. .clk = "l4ls_gclk",
  2973. .addr = am33xx_uart2_addr_space,
  2974. .user = OCP_USER_MPU,
  2975. };
  2976. /* l4 ls -> uart3 */
  2977. static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
  2978. {
  2979. .pa_start = 0x48024000,
  2980. .pa_end = 0x48024000 + SZ_8K - 1,
  2981. .flags = ADDR_TYPE_RT,
  2982. },
  2983. { }
  2984. };
  2985. static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
  2986. .master = &am33xx_l4_ls_hwmod,
  2987. .slave = &am33xx_uart3_hwmod,
  2988. .clk = "l4ls_gclk",
  2989. .addr = am33xx_uart3_addr_space,
  2990. .user = OCP_USER_MPU,
  2991. };
  2992. /* l4 ls -> uart4 */
  2993. static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
  2994. {
  2995. .pa_start = 0x481A6000,
  2996. .pa_end = 0x481A6000 + SZ_8K - 1,
  2997. .flags = ADDR_TYPE_RT,
  2998. },
  2999. { }
  3000. };
  3001. static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
  3002. .master = &am33xx_l4_ls_hwmod,
  3003. .slave = &am33xx_uart4_hwmod,
  3004. .clk = "l4ls_gclk",
  3005. .addr = am33xx_uart4_addr_space,
  3006. .user = OCP_USER_MPU,
  3007. };
  3008. /* l4 ls -> uart5 */
  3009. static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
  3010. {
  3011. .pa_start = 0x481A8000,
  3012. .pa_end = 0x481A8000 + SZ_8K - 1,
  3013. .flags = ADDR_TYPE_RT,
  3014. },
  3015. { }
  3016. };
  3017. static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
  3018. .master = &am33xx_l4_ls_hwmod,
  3019. .slave = &am33xx_uart5_hwmod,
  3020. .clk = "l4ls_gclk",
  3021. .addr = am33xx_uart5_addr_space,
  3022. .user = OCP_USER_MPU,
  3023. };
  3024. /* l4 ls -> uart6 */
  3025. static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
  3026. {
  3027. .pa_start = 0x481aa000,
  3028. .pa_end = 0x481aa000 + SZ_8K - 1,
  3029. .flags = ADDR_TYPE_RT,
  3030. },
  3031. { }
  3032. };
  3033. static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
  3034. .master = &am33xx_l4_ls_hwmod,
  3035. .slave = &am33xx_uart6_hwmod,
  3036. .clk = "l4ls_gclk",
  3037. .addr = am33xx_uart6_addr_space,
  3038. .user = OCP_USER_MPU,
  3039. };
  3040. /* l4 wkup -> wd_timer1 */
  3041. static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
  3042. {
  3043. .pa_start = 0x44e35000,
  3044. .pa_end = 0x44e35000 + SZ_4K - 1,
  3045. .flags = ADDR_TYPE_RT
  3046. },
  3047. { }
  3048. };
  3049. static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
  3050. .master = &am33xx_l4_wkup_hwmod,
  3051. .slave = &am33xx_wd_timer1_hwmod,
  3052. .clk = "dpll_core_m4_div2_ck",
  3053. .addr = am33xx_wd_timer1_addrs,
  3054. .user = OCP_USER_MPU,
  3055. };
  3056. /* usbss */
  3057. /* l3 s -> USBSS interface */
  3058. static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
  3059. {
  3060. .name = "usbss",
  3061. .pa_start = 0x47400000,
  3062. .pa_end = 0x47400000 + SZ_4K - 1,
  3063. .flags = ADDR_TYPE_RT
  3064. },
  3065. {
  3066. .name = "musb0",
  3067. .pa_start = 0x47401000,
  3068. .pa_end = 0x47401000 + SZ_2K - 1,
  3069. .flags = ADDR_TYPE_RT
  3070. },
  3071. {
  3072. .name = "musb1",
  3073. .pa_start = 0x47401800,
  3074. .pa_end = 0x47401800 + SZ_2K - 1,
  3075. .flags = ADDR_TYPE_RT
  3076. },
  3077. { }
  3078. };
  3079. static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
  3080. .master = &am33xx_l3_s_hwmod,
  3081. .slave = &am33xx_usbss_hwmod,
  3082. .clk = "l3s_gclk",
  3083. .addr = am33xx_usbss_addr_space,
  3084. .user = OCP_USER_MPU,
  3085. .flags = OCPIF_SWSUP_IDLE,
  3086. };
  3087. /* l3 main -> ocmc */
  3088. static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
  3089. .master = &am33xx_l3_main_hwmod,
  3090. .slave = &am33xx_ocmcram_hwmod,
  3091. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3092. };
  3093. /* l3 main -> sha0 HIB2 */
  3094. static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = {
  3095. {
  3096. .pa_start = 0x53100000,
  3097. .pa_end = 0x53100000 + SZ_512 - 1,
  3098. .flags = ADDR_TYPE_RT
  3099. },
  3100. { }
  3101. };
  3102. static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
  3103. .master = &am33xx_l3_main_hwmod,
  3104. .slave = &am33xx_sha0_hwmod,
  3105. .clk = "sha0_fck",
  3106. .addr = am33xx_sha0_addrs,
  3107. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3108. };
  3109. /* l3 main -> AES0 HIB2 */
  3110. static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {
  3111. {
  3112. .pa_start = 0x53500000,
  3113. .pa_end = 0x53500000 + SZ_1M - 1,
  3114. .flags = ADDR_TYPE_RT
  3115. },
  3116. { }
  3117. };
  3118. static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
  3119. .master = &am33xx_l3_main_hwmod,
  3120. .slave = &am33xx_aes0_hwmod,
  3121. .clk = "aes0_fck",
  3122. .addr = am33xx_aes0_addrs,
  3123. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3124. };
  3125. static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
  3126. &am33xx_l4_fw__emif_fw,
  3127. &am33xx_l3_main__emif,
  3128. &am33xx_mpu__l3_main,
  3129. &am33xx_mpu__prcm,
  3130. &am33xx_l3_s__l4_ls,
  3131. &am33xx_l3_s__l4_wkup,
  3132. &am33xx_l3_s__l4_fw,
  3133. &am33xx_l3_main__l4_hs,
  3134. &am33xx_l3_main__l3_s,
  3135. &am33xx_l3_main__l3_instr,
  3136. &am33xx_l3_main__gfx,
  3137. &am33xx_l3_s__l3_main,
  3138. &am33xx_pruss__l3_main,
  3139. &am33xx_wkup_m3__l4_wkup,
  3140. &am33xx_gfx__l3_main,
  3141. &am33xx_l4_wkup__wkup_m3,
  3142. &am33xx_l4_wkup__control,
  3143. &am33xx_l4_wkup__smartreflex0,
  3144. &am33xx_l4_wkup__smartreflex1,
  3145. &am33xx_l4_wkup__uart1,
  3146. &am33xx_l4_wkup__timer1,
  3147. &am33xx_l4_wkup__rtc,
  3148. &am33xx_l4_wkup__i2c1,
  3149. &am33xx_l4_wkup__gpio0,
  3150. &am33xx_l4_wkup__adc_tsc,
  3151. &am33xx_l4_wkup__wd_timer1,
  3152. &am33xx_l4_hs__pruss,
  3153. &am33xx_l4_per__dcan0,
  3154. &am33xx_l4_per__dcan1,
  3155. &am33xx_l4_per__gpio1,
  3156. &am33xx_l4_per__gpio2,
  3157. &am33xx_l4_per__gpio3,
  3158. &am33xx_l4_per__i2c2,
  3159. &am33xx_l4_per__i2c3,
  3160. &am33xx_l4_per__mailbox,
  3161. &am33xx_l4_ls__mcasp0,
  3162. &am33xx_l3_s__mcasp0_data,
  3163. &am33xx_l4_ls__mcasp1,
  3164. &am33xx_l3_s__mcasp1_data,
  3165. &am33xx_l4_ls__mmc0,
  3166. &am33xx_l4_ls__mmc1,
  3167. &am33xx_l3_s__mmc2,
  3168. &am33xx_l4_ls__timer2,
  3169. &am33xx_l4_ls__timer3,
  3170. &am33xx_l4_ls__timer4,
  3171. &am33xx_l4_ls__timer5,
  3172. &am33xx_l4_ls__timer6,
  3173. &am33xx_l4_ls__timer7,
  3174. &am33xx_l3_main__tpcc,
  3175. &am33xx_l4_ls__uart2,
  3176. &am33xx_l4_ls__uart3,
  3177. &am33xx_l4_ls__uart4,
  3178. &am33xx_l4_ls__uart5,
  3179. &am33xx_l4_ls__uart6,
  3180. &am33xx_l4_ls__spinlock,
  3181. &am33xx_l4_ls__elm,
  3182. &am33xx_l4_ls__epwmss0,
  3183. &am33xx_epwmss0__ecap0,
  3184. &am33xx_epwmss0__eqep0,
  3185. &am33xx_epwmss0__ehrpwm0,
  3186. &am33xx_l4_ls__epwmss1,
  3187. &am33xx_epwmss1__ecap1,
  3188. &am33xx_epwmss1__eqep1,
  3189. &am33xx_epwmss1__ehrpwm1,
  3190. &am33xx_l4_ls__epwmss2,
  3191. &am33xx_epwmss2__ecap2,
  3192. &am33xx_epwmss2__eqep2,
  3193. &am33xx_epwmss2__ehrpwm2,
  3194. &am33xx_l3_s__gpmc,
  3195. &am33xx_l3_main__lcdc,
  3196. &am33xx_l4_ls__mcspi0,
  3197. &am33xx_l4_ls__mcspi1,
  3198. &am33xx_l3_main__tptc0,
  3199. &am33xx_l3_main__tptc1,
  3200. &am33xx_l3_main__tptc2,
  3201. &am33xx_l3_main__ocmc,
  3202. &am33xx_l3_s__usbss,
  3203. &am33xx_l4_hs__cpgmac0,
  3204. &am33xx_cpgmac0__mdio,
  3205. &am33xx_l3_main__sha0,
  3206. &am33xx_l3_main__aes0,
  3207. NULL,
  3208. };
  3209. int __init am33xx_hwmod_init(void)
  3210. {
  3211. omap_hwmod_init();
  3212. return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
  3213. }