omap4-common.c 8.4 KB

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  1. /*
  2. * OMAP4 specific common source file.
  3. *
  4. * Copyright (C) 2010 Texas Instruments, Inc.
  5. * Author:
  6. * Santosh Shilimkar <santosh.shilimkar@ti.com>
  7. *
  8. *
  9. * This program is free software,you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/io.h>
  16. #include <linux/irq.h>
  17. #include <linux/irqchip.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/memblock.h>
  20. #include <linux/of_irq.h>
  21. #include <linux/of_platform.h>
  22. #include <linux/export.h>
  23. #include <linux/irqchip/arm-gic.h>
  24. #include <linux/of_address.h>
  25. #include <asm/hardware/cache-l2x0.h>
  26. #include <asm/mach/map.h>
  27. #include <asm/memblock.h>
  28. #include <asm/smp_twd.h>
  29. #include "omap-wakeupgen.h"
  30. #include "soc.h"
  31. #include "iomap.h"
  32. #include "common.h"
  33. #include "mmc.h"
  34. #include "hsmmc.h"
  35. #include "prminst44xx.h"
  36. #include "prcm_mpu44xx.h"
  37. #include "omap4-sar-layout.h"
  38. #include "omap-secure.h"
  39. #include "sram.h"
  40. #ifdef CONFIG_CACHE_L2X0
  41. static void __iomem *l2cache_base;
  42. #endif
  43. static void __iomem *sar_ram_base;
  44. static void __iomem *gic_dist_base_addr;
  45. static void __iomem *twd_base;
  46. #define IRQ_LOCALTIMER 29
  47. #ifdef CONFIG_OMAP4_ERRATA_I688
  48. /* Used to implement memory barrier on DRAM path */
  49. #define OMAP4_DRAM_BARRIER_VA 0xfe600000
  50. void __iomem *dram_sync, *sram_sync;
  51. static phys_addr_t paddr;
  52. static u32 size;
  53. void omap_bus_sync(void)
  54. {
  55. if (dram_sync && sram_sync) {
  56. writel_relaxed(readl_relaxed(dram_sync), dram_sync);
  57. writel_relaxed(readl_relaxed(sram_sync), sram_sync);
  58. isb();
  59. }
  60. }
  61. EXPORT_SYMBOL(omap_bus_sync);
  62. /* Steal one page physical memory for barrier implementation */
  63. int __init omap_barrier_reserve_memblock(void)
  64. {
  65. size = ALIGN(PAGE_SIZE, SZ_1M);
  66. paddr = arm_memblock_steal(size, SZ_1M);
  67. return 0;
  68. }
  69. void __init omap_barriers_init(void)
  70. {
  71. struct map_desc dram_io_desc[1];
  72. dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
  73. dram_io_desc[0].pfn = __phys_to_pfn(paddr);
  74. dram_io_desc[0].length = size;
  75. dram_io_desc[0].type = MT_MEMORY_SO;
  76. iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
  77. dram_sync = (void __iomem *) dram_io_desc[0].virtual;
  78. sram_sync = (void __iomem *) OMAP4_SRAM_VA;
  79. pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
  80. (long long) paddr, dram_io_desc[0].virtual);
  81. }
  82. #else
  83. void __init omap_barriers_init(void)
  84. {}
  85. #endif
  86. void __init gic_init_irq(void)
  87. {
  88. void __iomem *omap_irq_base;
  89. /* Static mapping, never released */
  90. gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
  91. BUG_ON(!gic_dist_base_addr);
  92. twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_4K);
  93. BUG_ON(!twd_base);
  94. /* Static mapping, never released */
  95. omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
  96. BUG_ON(!omap_irq_base);
  97. omap_wakeupgen_init();
  98. gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
  99. }
  100. void gic_dist_disable(void)
  101. {
  102. if (gic_dist_base_addr)
  103. __raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
  104. }
  105. bool gic_dist_disabled(void)
  106. {
  107. return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
  108. }
  109. void gic_timer_retrigger(void)
  110. {
  111. u32 twd_int = __raw_readl(twd_base + TWD_TIMER_INTSTAT);
  112. u32 gic_int = __raw_readl(gic_dist_base_addr + GIC_DIST_PENDING_SET);
  113. u32 twd_ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
  114. if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
  115. /*
  116. * The local timer interrupt got lost while the distributor was
  117. * disabled. Ack the pending interrupt, and retrigger it.
  118. */
  119. pr_warn("%s: lost localtimer interrupt\n", __func__);
  120. __raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
  121. if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
  122. __raw_writel(1, twd_base + TWD_TIMER_COUNTER);
  123. twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
  124. __raw_writel(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
  125. }
  126. }
  127. }
  128. #ifdef CONFIG_CACHE_L2X0
  129. void __iomem *omap4_get_l2cache_base(void)
  130. {
  131. return l2cache_base;
  132. }
  133. static void omap4_l2x0_disable(void)
  134. {
  135. /* Disable PL310 L2 Cache controller */
  136. omap_smc1(0x102, 0x0);
  137. }
  138. static void omap4_l2x0_set_debug(unsigned long val)
  139. {
  140. /* Program PL310 L2 Cache controller debug register */
  141. omap_smc1(0x100, val);
  142. }
  143. static int __init omap_l2_cache_init(void)
  144. {
  145. u32 aux_ctrl = 0;
  146. /*
  147. * To avoid code running on other OMAPs in
  148. * multi-omap builds
  149. */
  150. if (!cpu_is_omap44xx())
  151. return -ENODEV;
  152. /* Static mapping, never released */
  153. l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
  154. if (WARN_ON(!l2cache_base))
  155. return -ENOMEM;
  156. /*
  157. * 16-way associativity, parity disabled
  158. * Way size - 32KB (es1.0)
  159. * Way size - 64KB (es2.0 +)
  160. */
  161. aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
  162. (0x1 << 25) |
  163. (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
  164. (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
  165. if (omap_rev() == OMAP4430_REV_ES1_0) {
  166. aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
  167. } else {
  168. aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
  169. (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
  170. (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
  171. (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
  172. (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
  173. }
  174. if (omap_rev() != OMAP4430_REV_ES1_0)
  175. omap_smc1(0x109, aux_ctrl);
  176. /* Enable PL310 L2 Cache controller */
  177. omap_smc1(0x102, 0x1);
  178. if (of_have_populated_dt())
  179. l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
  180. else
  181. l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
  182. /*
  183. * Override default outer_cache.disable with a OMAP4
  184. * specific one
  185. */
  186. outer_cache.disable = omap4_l2x0_disable;
  187. outer_cache.set_debug = omap4_l2x0_set_debug;
  188. return 0;
  189. }
  190. omap_early_initcall(omap_l2_cache_init);
  191. #endif
  192. void __iomem *omap4_get_sar_ram_base(void)
  193. {
  194. return sar_ram_base;
  195. }
  196. /*
  197. * SAR RAM used to save and restore the HW
  198. * context in low power modes
  199. */
  200. static int __init omap4_sar_ram_init(void)
  201. {
  202. unsigned long sar_base;
  203. /*
  204. * To avoid code running on other OMAPs in
  205. * multi-omap builds
  206. */
  207. if (cpu_is_omap44xx())
  208. sar_base = OMAP44XX_SAR_RAM_BASE;
  209. else if (soc_is_omap54xx())
  210. sar_base = OMAP54XX_SAR_RAM_BASE;
  211. else
  212. return -ENOMEM;
  213. /* Static mapping, never released */
  214. sar_ram_base = ioremap(sar_base, SZ_16K);
  215. if (WARN_ON(!sar_ram_base))
  216. return -ENOMEM;
  217. return 0;
  218. }
  219. omap_early_initcall(omap4_sar_ram_init);
  220. void __init omap_gic_of_init(void)
  221. {
  222. struct device_node *np;
  223. /* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
  224. if (!cpu_is_omap446x())
  225. goto skip_errata_init;
  226. np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
  227. gic_dist_base_addr = of_iomap(np, 0);
  228. WARN_ON(!gic_dist_base_addr);
  229. np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
  230. twd_base = of_iomap(np, 0);
  231. WARN_ON(!twd_base);
  232. skip_errata_init:
  233. omap_wakeupgen_init();
  234. irqchip_init();
  235. }
  236. #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
  237. static int omap4_twl6030_hsmmc_late_init(struct device *dev)
  238. {
  239. int irq = 0;
  240. struct platform_device *pdev = container_of(dev,
  241. struct platform_device, dev);
  242. struct omap_mmc_platform_data *pdata = dev->platform_data;
  243. /* Setting MMC1 Card detect Irq */
  244. if (pdev->id == 0) {
  245. irq = twl6030_mmc_card_detect_config();
  246. if (irq < 0) {
  247. dev_err(dev, "%s: Error card detect config(%d)\n",
  248. __func__, irq);
  249. return irq;
  250. }
  251. pdata->slots[0].card_detect_irq = irq;
  252. pdata->slots[0].card_detect = twl6030_mmc_card_detect;
  253. }
  254. return 0;
  255. }
  256. static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
  257. {
  258. struct omap_mmc_platform_data *pdata;
  259. /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
  260. if (!dev) {
  261. pr_err("Failed %s\n", __func__);
  262. return;
  263. }
  264. pdata = dev->platform_data;
  265. pdata->init = omap4_twl6030_hsmmc_late_init;
  266. }
  267. int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
  268. {
  269. struct omap2_hsmmc_info *c;
  270. omap_hsmmc_init(controllers);
  271. for (c = controllers; c->mmc; c++) {
  272. /* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
  273. if (!c->pdev)
  274. continue;
  275. omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
  276. }
  277. return 0;
  278. }
  279. #else
  280. int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
  281. {
  282. return 0;
  283. }
  284. #endif
  285. /**
  286. * omap44xx_restart - trigger a software restart of the SoC
  287. * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
  288. * @cmd: passed from the userspace program rebooting the system (if provided)
  289. *
  290. * Resets the SoC. For @cmd, see the 'reboot' syscall in
  291. * kernel/sys.c. No return value.
  292. */
  293. void omap44xx_restart(char mode, const char *cmd)
  294. {
  295. /* XXX Should save 'cmd' into scratchpad for use after reboot */
  296. omap4_prminst_global_warm_sw_reset(); /* never returns */
  297. while (1);
  298. }